Hardware Implementation of Canonic Signed Digit Recoding

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1 IOSR Journal of VLSI and Signal Proceing (IOSR-JVSP) Volume 6, Iue 2, Ver. I (Mar. -Apr. 2016), PP e-issn: , p-issn No. : Hardware Implementation of Canonic Signed Digit Recoding B.V.V.Kiran, Kumar, B.Kai babu, M.Sri Vijay Abtract: Thi paper preent the implementation of convert a two complement binary number into it canonic igned digit repreentation. In thee CSD recoding circuit are functionally equivalent carrier H and K are decribed. They are computed in parallel reducing the critical path. They poe ome propertie that led to a implification of the algebraic expreion minimizing the overall hardware implementation. When compared with other binary CSD with other architecture, new CSD recoding i more efficient. Power analyi and area etimation are performed for the deigned CSD. Keyword: canonic Signed Digit (CSD) I. Introduction The canonic igned digit (CSD) repreentation i one of the exiting igned digit repreentation. It i ueful in certain DSP application focuing on low power, efficient area and high peed arithmetic [1].The CSD code i a ternary number with the digit et {1, 0,-1}.The correponding repreentation i unique and it ha two propertie.1.the number of nonzero digit i minimal, and 2.No two conecutive digit are both nonzero, i.e; two nonzero digit are not adjacent. CSD repreentation ha proven to be ueful for the deign and implementation of digital filter uch a the area efficient programmable FIR digital filter architecture[2] and the low complexity algorithm for deigning filter in [3],Two dimenional IIR and FIR filter deign in[4].csd code ha been largely exploited to implement efficient multiplier[5]. In 1960, Reitwieener propoed an algorithm for converting two complement number number to a minimum weight radix-2 igned digit repreentation [6]. All of thee algorithm generate the CSD code recurively from the leat ignificant bit (LSB) to mot ignificant bit (MSB)[7].In order to generate binary from CSD, the algorithm recurively generate from MSB to LSB[8].CSD repreentation ha no conecutive digit. A novel efficient cell-baed implementation to convert a two complement binary number into it CSD repreentation baed on two ignal H and K functionally equivalent to two carrier i preented. CSD Recoding The CSD recoding of an integer number i a igned and unique repreentation that contain no adjacent nonzero digit. Given an n-digit binary number unigned number X = Then the (n+1) digit CSD repreentation Y of X i given by y = x i n 2 i x i 0,1 x i 2 i = y i 2 i y i 1, 0,1 Thi condition that all nonzero digit in a CSD number are eparated by zero implie that y i+1 y i = 0 0 i n 1 From thi property, the probability that a CSD n-digit ha a nonzero value i given by P y i = 1 = [1 9 2 A n become large, the probability tend to 1/3 while thi probability become ½ in a binary code, uing thi property, the number of addition/ubtraction i reduced to a minimum number of multiplier and an overall peed-up can be achieved. The adapation of a ternary number ytem add ome flexibility to the CSD repreentation, it allow the number of nonzero digit to be mimimized,but it require that each digit y i be encoded two over bit {y i d, y i }.Since it atiifie the following relation. y i = y i d y i Wherey i d repreent the data bit and y i repreent the ign bit.thi encoding alo allow an additional valid repreentation of 0 when y i =1 and y i d =1 which i ueful in ome arithmetic implementation. n ] DOI: / Page

Hah main preented the binary coded CSD (BCSD) number to avoid extra data word repreentation. The BCSD recoding i baed on a imple binary repreentation B = {b 0, b 1,.

2 Hah main preented the binary coded CSD (BCSD) number to avoid extra data word repreentation. The BCSD recoding i baed on a imple binary repreentation B = {b 0, b 1,.., b } of a CSD code ue the ame number of bit a it original two complement repreentation. If the bit i in a CSD code i non zero y i 0, then the bit i i nonzero in the BCSD code, b i 0 and the following bit b i+1 act a a ign bit; b i+1 = 0 mean y i i poitive and b i+1 = 1 mean y i i negative.a imple converion between a CSD recoding and BCSD coding i b i = y i d + y i+1 b i+1 = y i+1 d + y i The converion from a binary repreentation to CSD repreentation i motly baed on the identity. 2 i+j i+j i = 2 i+j 2 i A converion proce from binary to CSD algorithm i hown. a 1 = 0 γ 1 = 0 a w = a w 1 for(i = 0 to w 1) θ i = a i ^^ a i 1 γ i = γ i 1 θ i a i = 1 2a i+1 γ i The encoding i performed from LSB to MSB uing two adjacent digit and a carry ignal. Here, the carry-out c i = 1 if and only if there i two of three 1 among the three input x i+1, x i and c i 1 c i = x i x i+1 + x i + x i+1 c i 1 c 1 = 0 The variable D = d 0, d 1, d in which all nonzero digit in the CSD repreentation i defined a d i =x i^c i 1 Since y i take one of the three value{0,1, 1}, it i neceary to encode it. y i d = x i+1 (x i^^c i 1 ) = x i+1 d i y i = x i+1 (x i^^c i 1 ) = x i+1 d i In the cae of an n-bit two complement binary number X; the CSD repreentation i given by Y = X 2 + n 2 x i 2 i = y i Here, only n CSD digit are neceary a the value of the binary number i limited to [ 2 n, 2 ].Negative integer in CSD can be obtained from their poitive counterpart by changing the ign of all nonzero digit. To convert a binary number into it CSD repreentation, valid for both unigned and two complemented binary number. The only difference arie in the lat CSD digit. An extra ign extenion, x n = 0 for unigned number and x n = x for two complement number, the lat ection change depending on the ign of X in the following general expreion. y d = d y = 0 For an unigned number X y d n = d n = c = x n c n 2 y n = 0 2 i For a igned number X y d = x n d i = x c n 2 y = x n d i = x c n 2 The imulated waveform for the converion of binary number to it CSD repreentation (n=6) i hown in Figure 1 and the RTL ynthei from RC i hown in Figure 2. Figure1. Simulated Waveform for converion of binary number to CSD repreentation (n=6) DOI: / Page

Figure 2.RTL compiler for binary to CSD code repreentation (n=6). New Cd Recoding Let X i an n-digit binary number. If we denote the two ignal, the ignal are H = h 0, h 1,.

3 Figure 2.RTL compiler for binary to CSD code repreentation (n=6). New Cd Recoding Let X i an n-digit binary number. If we denote the two ignal, the ignal are H = h 0, h 1,.. h and K = {k 0, k 1, k } a h i = x i h i 1 for i odd x i + h i 1 for i even k i = x i + k i 1 for i odd x i k i 1 for i even With h 1 = 0, k 1 = 0.Then c i can be formally expreed in term of odd or even index i mean the following relation. c i = h i + x i+1 k i for i odd x i+1 h i + k i for i even The two ignal H and K have ome propertie. h i k i = h i h For i odd i k i = 0 h i + k i = 1 h i + k i = k i h i k i = k i k For i even i h i = 0 k i + h i = 1 h i + k i = h i The variable D can be obtained from H and K following. For i even d i = h i k i For i odd d i = h i k i However, the variable Y for the CSD recoding in term of ignal H and K can be expreed a y i d = d i x i+1 = k ih i+1 h i k i+1 for i odd, even y i = d i x i+1 = k i+1h i for i odd, even h i+1 k i Only the lat bit changed depending on ign of X in the following general expreion For a igned number For an unigned number y d = k h n 2 h k n 2 y = k n 2h h n 2 k for n 1 odd, even for n 1 odd, even DOI: / Page

y d = k h for n 1 odd h k for n 1 even y = h for n 1 odd k for n 1 even The imulated waveform for binary to CSD new recoding (n=6) i hown in Figure 3.

RC compiler for new CSD recoding (n=6) The graph of the Power, Area, Gate of the Binary CSD and New Binary CSD i hown in the Figure 5, Figure 6 and Figure 7.

From Figure6, it i evident that Binary CSD occupie 426 μm², New Binary CSD occupie 293 μm².

4 y d = k h for n 1 odd h k for n 1 even y = h for n 1 odd k for n 1 even The imulated waveform for binary to CSD new recoding (n=6) i hown in Figure 3. The RTL ynthei from RC i hown in Figure 4. Figure 3.Simulated Waveform for new CSD recoding (n=6) Figure 4.RC compiler for new CSD recoding (n=6) The graph of the Power, Area, Gate of the Binary CSD and New Binary CSD i hown in the Figure 5, Figure 6 and Figure 7. From Figure5, it i evident that Binary CSD conume pw power, New Binary CSD conume pw. From Figure6, it i evident that Binary CSD occupie 426 μm², New Binary CSD occupie 293 μm². From Figure 7, it i evident that Binary CSD gate are 30 and New Binary CSD gate are 22. It i inferred that there i 38.31% reduction of power, 26.67% reduction of gate and 31.22% reduction of area for New Binary CSD compared with Binary CSD. Figure 5. Power for Binary CSD and New Binary CSD (n=6) DOI: / Page

, the New CSD recoding i better than the binary to CSD recoding becaue it reduce power, area and gate. Referance [1] I. Koren, Computer Arithmetic Algorithm (Second ed.), A.K. Peter, Ltd. (Ed.), 2002.

5 Figure 6. Area for Binary CSD and New Binary CSD (n=6) Figure 7. Gate for Binary CSD and New Binary CSD (n=6) II. Conculion The converion of a two complement number into it canonic igned digit(csd) repreentation can be efficiently implemented uing two ignal H and K., the New CSD recoding i better than the binary to CSD recoding becaue it reduce power, area and gate. Referance [1] I. Koren, Computer Arithmetic Algorithm (Second ed.), A.K. Peter, Ltd. (Ed.), [2] B. Phillip, N. Burge, Minimal weight digit et converion, IEEE Tranaction on Computer 53 (6) (2004) [3] K.Y. Khoo, A. Kwentu, A.N. Wilon, A programmable FIR digital filter uing CSD coefficient, IEEE Journal of Solid-State Circuit 31 (6) (June 1996) [4] J. Skaf, S.P. Boyd, Filter deign with low complexity coefficient, IEEE Tranaction on Signal Proceing 56 (7) (2008) [5] T. William, M. Ahmadi, W.C. Miller, Deign of 2D FIR and IIR digital filter with canonical igned digit coefficient uing ingular value decompoition and genetic algorithm, Circuit Sytem Signal Proceing 26 (1) (2007) [6] G.K. Ma, F.J. Taylor, Multiplier policie for digital ignal proceing, IEEE ASSP Magazine 1 (1990) [7] M.A. Sodertrand, CSD multiplier for FPGA DSP application, in: Proceeding of the International Sympoium on Circuit and Sytem (ISCAS), pp. V-469 V-472, [8] D.L. Iacono and M. Ronchi, Binary canonic igned digit multiplier for high- peed digital ignal proceing, in: Proceeding of the 47th IEEE International Midwet Sympoium on Circuit and Sytem, II, pp , DOI: / Page

PIPELINED DIVISION OF SIGNED NUMBERS WITH THE USE OF RESIDUE ARITHMETIC FOR SMALL NUMBER RANGE WITH THE PROGRAMMABLE GATE ARRAY

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