ISSN: ISO 9001:2008 Certified International Journal of Engineering and Innovative Technology (IJEIT) Volume 5, Issue 5, November 2015

Transcription

1 Optimum Deign of Charge Pump Circuit Uing Genetic Algorithm Dr. Ahmad T. Youni, Shamil H. Huein, and Ahmad A. Imail Abtract Integrated charge pump circuit are power converter ued to obtain a different d.c level. The mot important performance parameter that effect the operation of thee circuit may include voltage gain, ripple voltage, converion efficiency, power conumption, and the chip area required for fabrication. Improvement of thee parameter require a trade-off between the above variable. Genetic Algorithm (GA) i employed in thi paper a an optimization procedure to obtain an optimum deign that atifie a pecified requirement. The GA realization i performed to concentrate on power conumption and chip area required. The other performance parameter are bounded a contrained variable. The reultant parameter value atify the minimum requirement for the deigned fitne function while maintaing the other performance in their acceptable value. Index Term Integrated CP deign; Dickon CP; capacitive izing; Genetic Algorithm and witch boottrapped technique. I. INTRODUCTION Charge pump (CP) are power converter that convert a d.c power upply to higher or lower level voltage. Charge pump tranfer charge packet from the power upply to the output terminal uing only capacitor and witche to generate the required voltage level, thi configuration allow integrated realization [1]. Integrated realization of charge pump circuit ue integrated capacitor a torage element and tranitor a tranfer witche, where the drain and ource terminal are the two witch terminal, and the gate terminal i ued to control the witch tate. Many integrated ytem uch a Flah memorie, DRAM, OTP, RS-3 tranceiver, and driver circuit require multiple upply voltage level for their functional block and therefore charge pump are needed []. The mot important parameter that effect on performance of a CP i the number of tage, the required ilicon area occupation and power conumption. Moreover, in the deign of charge pump with purely capacitive load, alo the rie time and the charge conumption during the rie time are ignificant. However, it i worth noting that even if the clock frequency may appear a a deign parameter, it i uually fixed at the value of the clock frequency of the hot ytem [3]. Among many deign approache for charge pump, the witched-capacitor circuit uch a Dickon charge pump i very popular, becaue it can be implemented on the ame hot ytem chip. The voltage gain (A V ) of Dickon charge pump i proportional to the number of tage (N) in the pump []. Thi work preent an optimization method that baed on the ue of Genetic Algorithm that deal converion efficiency, voltage gain, load current a well a the ilicon area and capacitor izing of integrated CP. The aim of uing GA i to minimize the total ilicon area and power conumption while reerving the deired performance and pecification. II. CHARGE PUMP CIRCUITS Dickon Charge pump hown in Fig. (1) Comprie charge tranfer diode and charge pumping capacitor. Nonoverlapping clock pule i required to control the charge and dicharge procee on the pumping capacitor. The circuit pump charge from the power upply to the output terminal tage by tage to increae the output voltage V o. The diode are realized uing NMOS tranitor (Pa tranitor). However, thee diode uffer from voltage lo becaue of the threhold voltage and body effect. The efficiency of the ingle Dickon CP i very low, epecially at low input voltage. The double CP i conceived to reduce the output ripple by uing the ame total CP capacitance (C), a depicted in Fig. (), each half part of clock pule, which ha a total capacitance C/, feed the load in a different half period [3]. Hence, the charge pumped at the output i divided into two equal part, each for half period of clock pule. The output voltage i the ame a the ingle Dickon CP, but the ripple i half a given []: Where i the output ripple voltage, i the loading current, i the loading capacitance, and i the frequency of clock pule. In the boottrapped Dickon CP i hown in Fig. (3), the effect of witch voltage drop, varying on reitance, and low conduction are reduced by uing four non-overlapping clock phae (F 1, F, FB 1 and FB ), which alo prevent hortcircuit current from node at higher voltage to node at lower voltage. Thi configuration need the generation of four appropriate clock phae and MOS witche able to withtand high voltage,thi circuit involve izing the booting capacitor (C b ) adequately to boottrap the gate of the pa tranitor with the required overdrive voltage. The booted voltage on the gate of the pa tranitor i reduced becaue loading capacitance (C L ). The capacitor (C b ) mut be able to upply ufficient voltage wing to the gate of the pa tranitor and other paraitic capacitance. The booted voltage can be given a [6]: The boottrapped double CP i hown in Fig. () i ued to improve performance uch a output voltage ripple 9

2 reduction to half and increae efficiency and output voltage[3]. CP under tudied i contrained on power conumption and total chip area required for fabrication [9]. III. GENETIC ALGORITHM APPLICATION Genetic Algorithm i a earch technique baed on the mechanic of natural election ued in computing to find true or approximate olution to optimization and earch problem. The imple GA begin with the creation of an initial random population of individualwith value that are choen for the circuit variable, each of which repreent a candidate olution to a given optimization problem. Genetic Algorithm i realized to obtain the optimum parameter value uch a dimenion of the tranitor, pumping capacitance, output voltage and loading current. Thi i applied for the deign and realization of conventional and boottrapped charge pump circuit, ingle and double Dickon CP [7]. The firt tep in the GA proce i to determine the topology of the deign; the initial tak of the minimization procee are the determining of earch variable, pecification, and contraint in an appropriate manner. The variable are deigned to be the width of pa tranitor (w), loading current (I O ), output voltage (V O ) and riing time (tr) of the repone. It i required to atify the given deired pecification and contraint uch a pumping capacitance (C), voltage gain (A V ), efficiency (ƞ), current conumption (I DD ), charge conumption (Q TotN ), output ripple (V r ), output power (P O ) and minimum power conumption (P dip ), total ilicon area (A TotN ). The genetic algorithm proce wa realized a MATLAB program [3]. Two approache can be ued to repreent each variable, real and binary repreentation method are poible. In thi work binary form that contain different binary code for each variable i individually choen. Binary vector i deigned a a chromoome to repreent real value of the variable (I O, w 1, V O, V O (tr), and tr). The length of the gene (each part of chromoome) depend on the required preciion, which in thi algorithm i three place after the decimal point [7]. The total length of deigned chromoome found to be 7 bit. Uing population ize of 1, the total number of bit in population i 1 x 7 (randomly produced). IV. FITNESS FUNCTION FORMULATION The fitne function i formulated to include the pecified variable in ingle chromoome. The fitne ofeach chromoome in the current population i then evaluated and teted. In general, the fitne function can be expreed in ingle or multi-objective function. Generally fitne function i defined a[8]: m w i (x) = Fit i (x) (3) i 1 Where, w i i the weight coefficient of every ub-objective, Fit i (x) i the fitne of every performance objective, (x) i the overall fitne, and m i the number of the performance objective.the main objective function of the Where A T i the total area in (µm ), P i the total power conumption in (mw). The total area ( ) can be given a: Where are device dimenion, i the number of tranitor, and i the area required to fabricate pumping capacitance for CP circuit. The power conumption may be expreed a [3]: Where V DD i the poitive power upply voltage and i the current flow. Multi performance objective can be included in ingle fitne function with proper choice of weight function to include total ilicon area ( ) and power conumption (Pdip) minimization a follow: Where W 1 and W are the weighting factor. According to the propoed GA realization hown in Fig. (), evaluation of the fitne function for the current population (Pop_Size=1) i performed, and new population i generated if the requirement and contraint are found to be not atified. The new population i generated uing probability ditribution (Pc=.6) baed on fitne value, the election proce i baed on pinning the roulette wheel population ize time, each time it elect a ingle chromoome for a new population. The next operator i the recombination operator, a ingle point croover applied to the individual in the new population. One of the parameter of a genetic ytem i the probability of croover Pc (probability rate). Thi probability give the expected number (Pc x population ize) of chromoome which undergo to the croover operation.the next operator, mutation, i performed on a bit-by-bit bai. Another parameter of the genetic ytem; probability of mutation Pm, the expected number of mutated bit i (Pm x m x population ize), where m i the length of chromoome. Where (m=7, Pm=., and Pop_Size=1). The number of mutated bit ha been expected to be 317 bit mutation per generation. GA need a halt condition to end the generation proce. Among many topping criteria [9], thi work end the proce if a pecified number of generation i exceeded and the deired number of pecification i not 96

3 reached, the algorithm topped or when the fitne function evaluation i atified. V. PERFORMANCES EVALUATION The minimization of chip area and power conumption uing GA effect other performance of CP circuit. The deign equation forconventional and boottrapped Dickon CP configuration that govern the performance can be derived, under the aumption that all the tranitor in the circuit mut be kept in the aturation region. Thee pecification may include output voltage, converion efficiency, pumping capacitance, output ripple voltage, output power and current, charge conumption, and current conumption. The output voltage of the CP i given a [3]: Where N i the number of tage for CP circuit and i the pumping capacitance. The current and charge conumption can be employed by equation with. The number of tage in thi work i determined to be four tage [3] Where i the paraitic factor and. The pumping capacitance can be expreed a [3]: The converion efficiency of CP circuit i explained by follow a: VI. GA RESULTS AND COMPARISON The GA routine i ued in thi work to concentrate on minimization of power conumption and minimization of required chip area. The other performance that include voltage gain, pumping capacitance, efficiency, current and charge conumption, ripple output voltage, and output power are ued a contraint. The bound contraint for the elected variable are preented in Table (1). The GA reulted for thee variable give a ignificant improvement for the deired fitne variable compared with analytical counterpart a hown in Table (). It can be een from the above table that GA reult a ignificant improvement in chip area required and power conumption compared with the exiting analytical approache. However the other performance that elected a contraintare lightly divert but their value are till in it bound condition. Table (3) how thee performance for different load current. It i clear from thi table that a I o increae the pumping capacitance (C) increae ince thi capacitor i directly proportional to load current (I o ) [3]. VII. SIMULATION RESULTS To certify the operation of CP circuit under the GA reultant parameter value. Orcad PSPICE i ued to imulate the CP circuit under tudied etting I O = 6µA. The tranient repone of thee deign i hown in Fig. (6). It can be een from thi figure the optimum deign parameter reulted from GA atify the deired requirement (output voltage, ripple output, riing time and efficiency). All CP circuit are deigned and imulated under ame condition uch a include tage capacitance, upply voltage, clock frequency, and identical device dimenion [9]. The output ripple voltage of thee CP circuit are proportional to loading current, when increaing the current, the ripple output will be increae, the imulated of thi relationhip i hown in Fig. (7). The imulated output voltage of the CP deign with repected for changing in loading current i hown in Fig. (8). It can be een from thi figure the boottrapped double CP ha output voltage higher than from conventional ingle and double CP. Fig. (9) preent the output power for conventional and boottrapped of ingle and double CP veru loading current with a pumping capacitance of 66.6pf and f=1mhz []. Fig. (1) Show the imulated reult of CP circuit with only capacitive load (C L =pf) and loading current (I O =6µA) under different power upply voltage. The output voltage increae with increae power upply voltage. Alo the four CP circuit are deigned in the different input clock frequencie, the output voltage of thee circuit are increaed when the input clock ignal frequencie i increaed a hown in Fig. (11). However, the propoed charge pump (boottrapped double CP ) ha higher output voltage under the ame upply voltage and output current[3]. In the boottrapped double charge pump give a higher output voltage under the ame pumping capacitor, tage number (N=), capacitive load, upply voltage, and ame clock frequency, it indicate that the propoed CP circuit ha better pumping efficiency than the ingle and double CP. The imulated power converion efficiencie for the four tage charge pump circuit a function of loading current, input upply voltage and input clock ignal frequencie are hown in Figure 1, 13 and 1 repectively. The imulated maximum power efficiency of boottrapped double CP i about 88.9% at f=1mhz and V DD =1.8 V compared with the exiting reult in [3] a explained in table 1 and. VIII. CONCLUSIONS Thi paper wa concerned with the deign and imulation of integrated charge pump circuit. An optimization procedure that baed on the ue of GA were applied to 97

4 improve the circuit performance. A minimization of power conumption and total chip area required for fabrication were obtained compared with the exiting reult from analytical method. Simulation for different CP topologie uing the reultant parameter value from GA howed the atifaction between the pecified requirement and GA reult.a future extenion of thi work may include the ue of multi-objective function that concentrate on other performance like pumping capacitance, number of tage, and efficiency. REFERENCES [1] G. Palumbo, D. Pappalardo, and M. Gaibotti, "Charge Pump Circuit: Power Conumption Optimization", IEEE Tran. Circuit Syt. I, vol. 9, no. 11, pp. 13 1, Nov.. [] S. L.-K. Chang and C.-H. Hu, "High Efficiency MOS Charge Pump Baed On Exponential-Gain Structure With Pumping Gain Increae Circuit", IEEE Tran. Power Electronic, vol. 1, no. 3, pp , May 6. [3] G. Palumbo and D. Pappalardo, "Charge Pump Circuit: An Overview On Deign Strategie And Topologie", IEEE Circuit Syt. Mag., vol. 1, no. 1, pp. 31, 1. [] Aamna Anil and Ravi Kumar Sharma, "A High Efficiency Charge Pump For Low Voltage Device", International Journal of VLSI deign & Communication Sytem (VLSICS) Vol.3, No.3, Lovely Profeional Univerity, Jalandhar, Punjab, India, June 1. [] Robert J. and PrimitModi, "A Charge Pump Architecture With High Power Efficiency And Low Output Ripple Noie In. ΜmCMOS Proce Technology", M.Sc. Thei, Electrical and Microelectronic Engineering, Rocheter, New York, July, 1. [6] Stefano Gregori and YouniAllaameh, "Switch Boottrapping Technique For Voltage Doubler And Double Charge Pump", in Proc. IEEE Int. Symp. Circuit Syt. (ISCAS), 11, pp [7] Z. Michalewica, "Genetic Algorithm + Data Structure = Evolution Program", Springer-Verlag Berlin Heidelberg, Univerity of North Carolina, [8] M. Melanie, "An Introduction To Genetic Algorithm", MIT pre, [9] R. L. Haupt and S. E. Haupt, "Practical Genetic Algorithm", John Wiley and Son. Second edition,. Table : GA reult for integrated CP circuit deign with I o =6µA and CL= Deire GA Analytica Specification Type d reult l value Area (µm ) Power conumption(mw ) Voltage gain Av (db) Pumping capacitance C ( ) Efficiency η (%) I DD (mw) Q TotN (nc) Ripple Voltage Vr (Volt) Output power P O (mw) Function Function (Min) (Min) %.8% Table 3: Performance pecification for change Io from.1ma to 1.1mA w Io C Vr Av 1..w Po Pin I DD (mw (mw (µa) (V) (db) (ma) (µm) ) ) Table 1: GA reult for the deigned variable Variable Lower Upper bound bound GA reult Analytical Io (µa) w1(µm) Vo (V) Vo(tr) (V)..7. Tr (µ)

5 Ourput ripple voltage Vr (volt) Fig (1): Conventional ingle Dickon CP circuit Fig (): Conventional double Dickon CP circuit Fig (): Flow chart for GA proce V o. Volt Time (ec) Fig (3): Boottrapped ingle Dickon CP circuit.6. Fig (6): Tranient repone of the Dickon CP circuit Model - Single CP Simulation - Single CP Model - Double CP Simulation - Double CP Fig (): Boottrapped double Dickon CP circuit x 1 - Fig (7): Model and imulation of loading current veru output ripple voltage for ingle Dickon charge pump and double CP With

6 Output Voltage Vo (Volt) Output Voltage Vo (Volt) Efficiency (%) Output Power Po (Watt) Efficiency (%) Output Voltage Vo (Volt) Efficiency (%) Boottrapped Single CP Boottrapped Double CP Boottrapped Single CP Boottrapped Double CP x 1 - Fig (8): Simulated output voltage veru loading current for conventional and boottrapped of ingle and doublecp with x 1 - Fig (1): Simulated efficiency variation veru loading current for conventional and boottrapped of ingle and double Dickon CP with 7 x 1-3 Boottrapped Single CP 6 Boottrapped Double CP Boottrapped Single CP Boottrapped Double CP x 1 - Fig (9): Output power variation with repect loading current for conventional and boottrapped of ingle and double CP with Input Voltage VDD (Volt) Fig (13): Simulated efficiency variation veru input voltage for conventional and boottrapped of ingle and double Dickon charge pump with Boottrapped Single CP Boottrapped Double CP Input Voltage VDD (Volt) Fig (1): Simulated output with repect to change in the input voltage for conventional and boottrapped of ingle and double CP with 3 1 Boottrapped Single CP Boottrapped Double CP Frequencie F (Hz) x 1 7 Fig (1): Simulated efficiency variation veru input frequencie for conventional and boottrapped of ingle and double CP with Boottrapped Single CP Boottrapped Double CP Frequencie F (Hz) x 1 7 Fig (11): Simulated output variation veru input frequencie for conventional and boottrapped of ingle and double CP with 1

7 AUTHOR BIOGRAPHY Dr. Ahmad T. Yonni wa graduated in 1981 from MTC Baghdad_ Iraq, he finihed hi MSc in Modern Electronic from Nottingham univerity / UK in 198. And hi Ph.D. from Eex univerity / UK in Hi reearch interet in microelectronic and integrated circuit deign and optimization. He i now an aitant profeor in Electronic engineering and a head of ytem and control engineering in Moul univerity_ Iraq. Shamil H. Huein wa born in Moul 198 and he got her BSc degree from Electrical engineering department in univerity of Moul/Moul/Iraq. He finihed hi MSc in Electronic from Moul Univerity / Iraq in 1. Hi reearch interet in microelectronic and RF ytem deign. He i now an aitant lecturer in Electrical engineering in Moul univerity_ Iraq. Ahmed A. Imailwa born in Moul 1969 and he got her BSc degree from Electrical engineering department in univerity of Moul/Moul/Iraq. He finihed hi MSc in Electronic from Moul univerity / Iraq in 13. Hi reearch interet in power amplifier and RF ytem deign. He i now an aitant lecturer in Electrical engineering in Moul univerity_ Iraq. 11