Thermal noise in field-effect devices

Size: px
Start display at page:

Download "Thermal noise in field-effect devices"

Transcription

1 Thermal noise in field-effect devices J. W. Haslett, M.Sc, and F. N. Trofimenkoff, Ph.D. Abstract Thermal-noise calculations for both junction-gate and m.o.s. field-effect transistors are performed using a straightforward circuit-analysis technique based on the equivalent circuit. Expressions are obtained for i%, / and the correlation coefficient of i g and i d at moderately high frequencies. A comparison with van der Ziel's results for the bulk f.e.t. shows that the expression for the gate noise can be simplified considerably and that the expression for the correlation coefficient c is in error. The correct expression for c is given in terms of van der Ziel's equations and is also presented in simplified form. Approximate expressions for the noise factor of both bulk and m.o.s.f.e.t. amplifiers are presented in a form convenient for comparison with experimental measurements. It is found that, for the model under consideration, at higher frequencies the thermal-noise performance of the m.o.s.f.e.t. is similar to or better than that of the bulk f.e.t., for comparable gate capacitances and transconductances. List of symbols For junction-gate f.e.t. a = halfchannel height, defined in Fig. 1 c = correlation coefficient, defined by eqn. 25 Cj = magnitude of correlation coefficient C x gate-source capacitance of intrinsic device, defined by eqn. 4 C 2 = gate-drain capacitance of intrinsic device, defined by eqn. 5 C/, C,. = capacitances, defined by eqn. 22 C gs = total gate-source capacitance, including strays C gd = total gate-drain capacitance, including strays / = cyclical frequency /o = break frequency of the spot-noise factor, defined by eqn. 38 f\(y,z),f2{y,z),fi(y,z) = functions of the direct-bias conditions, defined by eqns. 4 and 5 F = noise factor, defined by eqn. 37 F min = minimum noise factor, defined by eqn. 40 F ch contribution to noise factor due to channel noise, defined by eqn. 36 %j,(y,z) = function of bias conditions, defined by eqn. 23 g 0 output conductance, defined by eqn. 2 g m = transconductance, defined by eqn. 3 g mo = maximum transconductance, defined by eqn. 7 i gr = noise current into gate resulting from thermal noise of R g ig = gate-noise current resulting from thermal noise in channel i d = thermal-noise current from the conducting channel i dl = total noise current in short-circuited drain 'dtr = noise current at drain due to thermal noise of R g I d = direct drain current, defined by eqn. I k = Boltzmann's constant L = active channel length N c = ionised-impurity density in channel p = function of bias conditions, defined by eqn. 23 P(f) = power spectrum, defined by eqn. 30 PTW) P R (f) = power spectrum of total output-noise current = power spectrum of drain-noise current due to the signal source conductance q = magnitude of electronic charge Q(l,z) = function of gate bias, defined by eqn. 16 /?/, R r = resistances at the point x in the channel, defined by eqns. 10 and 11 R n = equivalent noise resistance, defined by eqn. 18 R g gate resistance Rg O p, = gate resistance which defined by eqn. 39 S(f) Fourier spectrum of defined by eqn. 29 minimises noise factor, the noise current /(/) Paper 5929 E, first received 23rd January and in revised form 21st May 1969 Mr. Haslett and Dr. Trofimenkoff are with the Department of Electrical Engineering, University of Calgary, Calgary, Alta., Canada PROC. IEE, Vol. 116, No. II, NOVEMBER 1969 / = channel breadth T = absolute temperature, K V gs = direct gate-source voltage V ds = direct drain-source voltage dv n (x) = thermal-noise voltage generated by a length of channel dx at x W = gate-channel potential at a point x in the channel W d = gate-channel potential at drain W s = gate-channel potential at source = pinchoff potential x = distance along channel from the source y= w d iw p z= W s \ a conductivity of channel material i/> 0 = equilibrium contact potential 1 (1 + 7Z 1 ' 2 ) y = c 5 (1 + 3z'/ 2 ) For m.o.s.f.e.t. c' = correlation coefficient, defined by eqn. 56 c'i = magnitude of correlation coefficient C[ gate-source capacitance of intrinsic device defined by eqn. 41 C' 2 = gate-drain capacitance of intrinsic device, defined by eqn. 42 C' gs, C' gd total gate-source and gate-drain capacitances, respectively C ox oxide capacitance per unit length of channel W ^ gs + ^gd / 0 = break frequency of the noise factor, defined by F' '' min So m onto L' g igopt eqn. 60 noise factor, defined by eqn. 59 minimum noise factor, defined by eqn. 62 contribution to noise factor due to channel noise, defined by eqn. 58 output conductance, defined by eqn. 43 transconductance, defined by eqn. 44 transconductance at pinchoff, defined by eqn. 48 function of bias conditions, defined by eqn. 54 thermal noise due to conducting channel gate noise due to capacitive coupling with channel active channel length equivalent noise resistance, defined by eqn. 50 gate resistance which minimises noise factor, defined by eqn. 61 T ox = thickness of oxide insulating layer v s gate-channel potential at source v d = gate-channel potential at drain V' gs = direct gate-source voltage V' ds = direct drain-source voltage V T = threshold voltage Z = device breadth e ox permittivity of oxide insulating layer [x carrier mobility in channel 1863

2 1 Introduction Thermal-noise calculations for both junction- and insulated-gatefield-effecttransistors have been presented by a number of authors. 1 " 5 Since that time, additional work on the small-signal equivalent circuits of these devices has been published The purpose of the paper is to demonstrate that thermal-noise calculations can be performed simply by using an equivalent-circuit approach rather than by reverting to fundamental considerations of device operation. Results are presented in a compact form for both junction- and insulated-gate devices. 2 Junction-gate f.e.t. 2.1 Equivalent circuit A cross-section of an f.e.t. is shown in Fig. 1. The device can be divided into an 'intrinsic' portion involving the active channel and an 'extrinsic' portion, which accounts for stray capacitances and parasitic resistances as illustrated. Reddy and Trofimenkoff 6 have derived a small-signal equivalent circuit for the active device, which takes the form shown in Fig. 2. For frequencies well below the cutoff frequency of the f.e.t., the resistances r { and r 2 are negligible compared with the reactances of C { and C 2, and / 0 is very small, so that the active channel may be represented to a good approximation by the circuit shown in Fig. 3. Shockley 7 has shown that the direct drain current I d is given by /,, = loat _(«:y"l«r m where a = conductivity of the channel material. Utilising eqn. 1, it is easy to show that the output conductance g o is given by 80 L \ and the transconductance g m is 8m L \\ It should be noted that w d = «Ao + v gt - y ds where V gs and V ds are the gate-source and drain-source voltages, respectively, and </r 0 is the equilibrium contact potential. Van der Ziel 2 has derived expressions for the gate-source capacitance C x and the gate-drain capacitance C 2 in terms of device dimensions and bias conditions as follows: _ 2qN caltf 2 (y,z) where Cl _ 2qN c altmy,z) 23/2) _ (4) extrinsic capacitances f 2 (y,z) -y m ) - y) V/////&V/7///X//Y//, I type material parasitic parasitic resistance(r s ) resistance^ substrat< Fig. 1 Bulk f.e.t with bias voltages applied A(y,z) = (y - z) -\{y m - z" 2 ) and y=w d \ z= W s \ At pinchoff, W d = tv p, so that y = 1 and (6) (7) Fig. 2 General form of intrinsic equivalent circuit _ 3qN calt Tt can be shown that, at moderately high frequencies, the effects of the parasitic resistances R s and R d are negligible, so that stray capacitances from gate to source and gate to drain appear directly in parallel with C { and C 2, yielding a modified equivalent circuit for the complete device, as shown in Fig. 4. The capacitances C gs and C gd represent the total gate-source and gate-drain capacitances, respectively. (9) gd - d fls Fig. 3 Simplified equivalent circuit for the active channel 1864 Fig. 4 Modified equivalent circuit including stray capacitances PROC. IEE, Vol. 116, No. 11, NOVEMBER 1969

3 2.2 Thermal-noise calculations Trofimenkoff 8 has presented a method of evaluating the short-circuit drain-noise current by splitting the transistor Equating eqn. 15 and eqn. 17 yields (18) where Q(l, z) is of the order of 0 6 for normal bias conditions. 2.3 Gate noise An extension of the split-transistor technique may be used to calculate the gate noise which results from capacitive coupling with the channel at moderately high frequencies. The intrinsic capacitances are included in the 2-transistor equivalent circuit, as shown in Fig. 6. It should be noted that s,=s d,=d Fig. 6 2-transistor representation for gate-noise calculations b Fig. 5 Split-transistor technique a Schematic of bulk f.e.t. b 2-transistor representation of f.e.t. g at a point x in the channel, as shown in Fig. 5. The resistances R, and R r are given by _J laat) R,~ x \ 1 l^lu-t L-x\ \ (ID The thermal noise associated with the resistance of a length of channel dx at x is given by 2aat<\-(^ 4kTAfdx W n '/ 2 (12) where A/= equivalent noise bandwidth of the system. The contribution to the drain-noise current may then be expressed as (R, + R r ) 2 (13) Substitution for dx from eqn. 1, for dv n (x) 1 from eqn. 12, and integration from the source (W = W s ) to the drain {W = W d ) yield the mean-square drain-noise current in a bandwidth A/: in agreement with van der Ziel's 1 results. At pinchoff,.... (14) /J = 4kTAfg mo Q(l, z) (15) 1 (1 + 3z l/2 ) where Q(l, 2 ) = IL± I r/5 j (,«) The equivalent noise resistance at the input may be obtained by writing lf l = 4kTR n g 2 m0af (17) PROC. IEE, Vol. 116, No. II, NOVEMBER 1969 the source and drain terminals are a.c. short-circuited to the gate, eliminating the effects of stray capacitance. If it is assumed that capacitive currents flowing to the gate are small in comparison with conductive currents flowing through the channel, the channel current can be assumed to be constant. If this is the case, the voltage at d t is given by dv { = R,di d. (19) and the voltage at s 2 is dv 2 = - R r di d (20) dv n (x) where di,, = (R, + Rr ) (20 Using eqns. 19 and 20, we can show that the incremental gate current di g is W W.. (22) f W W \ The function A ( -, -~) is obtained by replacing y by V J (177 ) m ec l n - 5 > anc * h \ TTT ' 777 ) ' s obtained by replacing z \ WpJ \ J Substitution of appropriate values into eqn. 22 and integration from source to drain yields where '1 = 4A:7A/oi2 C 2 (l - z l/2 ) ) = [P 2 {(y ~ z) + i (y 2 - z 2 ) - f (y 3 ' 2 - z 3 ' 2 )} - lp& (y z 3 ' 2 ) - (y 2 - z 2 ) + i (y 5 ' 2 z 5 ' + {i (y 2 - z 2 ) - f (y 5 ' 2 - z 5 / 2 ) + i (y 3 - z 3 )}] $ (y z 3 ' 2 ) - i (y 2 - z 2 ) and p = A(y, again in agreement with van der Ziel's results. 2 At pinchoff, g 3 (y,z) may be simplified to yield (23) / 1 (1 + 7z'/ 2 ) 4kTR n A/oj 2 C 2 ~ 5 (1 + 3z" 2 (24) ) ' ' " This result is much simpler than that presented by van der 1865

4 Ziel, 2 and it can be shown that the two expressions are identical. 2.4 Correlation coefficient The degree of correlation between the gate and drain noise is expressed in terms of a correlation coefficient defined by l S l d / 25 \ A nodal analysis of the circuit yields. _., (i g + igr)xg(gmol dt l d + + jcor g (C gs +C gd ) (32) On replacing currents by equivalent current spectra in eqn. 32, g c a d Taking the product of eqn. 21 with the complex conjugate of eqn. 22 and integrating from source to drain: -4kTkfjaj2c/N c alt r l *' = I'M**) -z 3/2 )-i(/-z 2 )},. 2 - z 3 ' 2 ) (26) Substitution of eqns. 26, 23 and 14 into eqn. 25 and setting y = I yields l/go, showing thermal-noise sourcesc = - z)" 2 {5(l + 3z'/ 2 )(l + 7z'/ 2 )}'/ 2 (27) ' Van der Ziel has obtained an expression for c which is more complicated and which does not agree with the numerical data. 2 The expression in its correct form is given by Fig. 7 Simple f.e.t. amplifier with taking the product with the complex conjugate and performing the averaging procedure and noting that i g and i d are correlated, it can be shown that C gd )Y C gd ) {corjc gs + C gd )Y (33) l0.12 (1 +2z'/ 2 ) c = 3z'/ 2 ) z'/ 2 ) 15 2z'<' 2 ) 2 10 and it can be shown that this reduces to eqn Figure of merit The spot-noise factor is the most commonly used figure of merit for evaluating the noise performance of an amplifier and may be expressed as total output noise power output thermal noise power due to the source conductance.... (28) The noise power is usually described in terms of a power spectrum, which gives the mean-square noise voltage or current per unit bandwidth. In order to obtain the power spectrum of a random stationary process such as thermal noise, a transformation from the time domain to the frequency domain and a suitable averaging procedure are required. Montgomery 9 shows that it is possible to replace a steady-state noise current /(/) by a Fourier spectrum defined by 1 r' +T. S(f) = - ^^ i{t)e-^'dt (29) where T is any finite time interval. The power spectrum is then obtained by noting that "TT 00 P(f) = -T-,= \ E{S*(f)S(g)}dg (30) L±J J 00 where denotes the expected value, and the asterisk denotes the complex conjugate. The noise factor may then be written as c PTU) PR(/) (31) where P T (f) = power spectrum of the total output noise current PRU) ~ power spectrum of the noise at the output due to the signal source conductance only. The equivalent circuit of a simple amplifier including noise sources is shown in Fig. 7, where the symbols are as defined in the list of symbols z } 1/2 Similarly, the mean-square contribution to the output current from the gate resistance is given by <" R 1 + {a>r g (C gs + C gd )Y Substitution of eqns. 33 and 34 into eqn. 31 yields oj 2 C}Q(l,z)yR g where C, = C gc + C 7 gi " " ^gd ~ 5 (1 + 3z" 2 ) Smo Smo (34) ^ Smo.... (35) The first term is the contribution due to channel noise, the second is due to gate noise, and the third is a result of correlation between i g and i d. It should be noted that C ( is the gate-drain capacitance for the intrinsic portion of the f.e.t. only, while C gd represents the total gate-drain capacitance, including strays. At moderately high frequencies, o> <^ g mo IC gd, and, if R g > V<?mo» tne term ucgdlimo is mucn smaller than ojr g C,, so that the channel-noise contribution is approximately given by Smo "-g {1 + (cvr.c,) 2 } (36) A comparison of eqn. 36 with the contributions due to gate noise and correlation shows that the channel-noise term dominates, provided that C x < C,, which is always the case, so that ~ 1 + Q0,z) ' + ' (37) PROC. IEE, Vol. 116, No. II, NOVEMBER 1969

5 (38) The gate resistance that will minimise the noise factor is found by differentiating eqn. 35 with respect to R g and equating the result to zero. Again, at moderately high frequencies and for values of R g > l/# mo, and the minimum noise factor is given by (39) At pinchoff, J. 2 1 and R n = - -r- J mo The mean-square value of the gate-noise current is given by (51) (52) '7 = 9 ' 7 V 2 _ V2\2t v \ v ) Z( V s> V d) (53) /-,, ~ l ^ ' (40) where C o = L,'C 0X and Since the optimum gate resistor R g opt is frequency-dependent, it is not possible to minimise/'over a large range of frequencies using a fixed R g. 3 Metal-oxide-semiconductor f.e.t. 3.1 Equivalent circuit The equivalent circuit for a metal-oxide-semiconductor f.e.t. takes the same form as that for the junctiongate f.e.t., as shown in Figs. 3 and 4. In order to avoid confusion, primed values will be used to distinguish the m.o.s.f.e.t. parameters from those of the bulk f.e.t. Using the transmission-line equations derived by Candler and Jordan, 10 a small-signal equivalent circuit has been derived for the device, and the components have been expressed, in terms of bias conditions and device dimensions as follows: c;-!c.^.&±g> (40 At pinchoff, v d = 0 64 and ig 2 = 135 g m (54) (55) The correlation coefficient is independent of bias conditions for the pinchoff case and has a value (56) Utilising the expressions for the thermal-noise generators given by eqns. 49 and 53, the excess noise factor for a simple amplifier similar to that shown in Fig. 7 may be written in exact form as where C ox = It should be noted that (43) (44) 2 a> 2 R g C 0 C' t \ g' mo R 8 C' t + ( 7~) &mo ' (57) where C,' = C' g, + C gd The first term is the contribution due to channel noise, the second is that due to gate noise, and the third is that due to correlation. As for the bulk f.e.t. at moderately high frequencies, co < g m olc' g d> so tnat tne channel-noise contribution is approximately given by At pinchoff, v d = 0 and C[ = i C OX L' (45) C 2 = 0 (46) g'o = 0 (47) For R g > llg mo, it is found that the channel noise dominates, provided that C\ > C o, which is usually the case, so that the noise factor F' is (59) tonto /_' where /Q = 2-nRgC, (60) 3.2 Thermal noise The procedure involved in calculating the noise cpmponents for the m.o.s.f.e.t. is identical to that for the bulk f.e.t. just described. In order to avoid repetition, only the final results are quoted. The thermal noise of the conducting channel may be written as (v * + v ' v " + v ' d) Using a procedure similar to that for the bulk f.e.t., it is found that the optimum R g which will minimise the noise factor is given by yielding a minimum noise factor (62) yielding an equivalent noise resistance R' - 2 ' " ~ 377' ( v - v*) mo \ s d> PROC. 1EE, Vol. 116, No. II, NOVEMBER Comparison of results A comparison of eqn. 62 with eqn. 40 shows that the minimum noise factor for the m.o.s.f.e.t. is nearly the same 1867

6 as that for the bulk f.e.t., provided that the transconductances and input capacitances are comparable. It is possible to obtain m.o.s.f.e.t.s with high transconductance and low input capacitance, so that, for the model under consideration, the thermal-noise performance of the m.o.s.f.e.t. at higher frequencies is expected to be as good as or better than that of the bulk f.e.t. 5 References 1 VAN DER ZIEL, A.: 'Thermal noise in FET's', Proc. Inst. Radio Engrs., 1962, 50, pp VAN DER ZIEL, A.: 'Gate noise in FET's at moderately high frequencies', Proc. Inst. Elect. Electron. Engrs., 1963, 51, pp BRUNKE, w. c, and VAN DER ZIEL, A.: 'Thermal noise in junctiongate FET's', IEEE Trans., 1966, ED-13, (3), pp SHOJI, M. : 'Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors', ibid., 1966, ED-13, (6), pp JORDAN, A. c, and JORDAN, N. A. : 'Theory of noise in MOS devices', ibid., 1965, ED-12, (3), pp REDDY, B., and TROFIMENKOFF, F. N. : 'F.E.T. high-frequency analysis', Proc. IEE, 1966, 113, (11), pp SHOCKLEY, w.: 'A unipolar field-effect transistor', Proc. Inst. Radio Engrs., 1952, 40, pp TROFIMENKOFF, F. N.: 'Thermal noise in field-effect transistors', Proc. Inst. Elect. Electron. Engrs., 1965, 53, (9), pp MONTGOMERY, H. c.: 'Transistor noise in circuit applications', Proc. Inst. Radio Engrs., 1952, 40, pp CANDLER, D. p., and JORDAN, A. c: 'A Small-signal, high-frequency analysis of the insulated-gate FET', Internal. J. Electron., 1965, 19, (2), pp PROC. IEE, Vol. 116, No. 11, NOVEMBER 1969

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Lecture 11: J-FET and MOSFET

Lecture 11: J-FET and MOSFET ENE 311 Lecture 11: J-FET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

Chapter 6: Field-Effect Transistors

Chapter 6: Field-Effect Transistors Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

ECE 546 Lecture 10 MOS Transistors

ECE 546 Lecture 10 MOS Transistors ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

The Gradual Channel Approximation for the MOSFET:

The Gradual Channel Approximation for the MOSFET: 6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

More information

FIELD-EFFECT TRANSISTORS

FIELD-EFFECT TRANSISTORS FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)

EE105 Fall 2015 Microelectronic Devices and Circuits Frequency Response. Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH) EE05 Fall 205 Microelectronic Devices and Circuits Frequency Response Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Amplifier Frequency Response: Lower and Upper Cutoff Frequency Midband

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

Figure 1: MOSFET symbols.

Figure 1: MOSFET symbols. c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between

More information

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 10, Number 2, 2007, 189 197 MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations S. EFTIMIE 1, ALEX. RUSU

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The Long Channel Approximation MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

GaN based transistors

GaN based transistors GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute

More information

Transistor Noise Lecture 10 High Speed Devices

Transistor Noise Lecture 10 High Speed Devices Transistor Noise 1 Transistor Noise A very brief introduction to circuit and transistor noise. I an not an expert regarding noise Maas: Noise in Linear and Nonlinear Circuits Lee: The Design of CMOS RFIC

More information

Class 05: Device Physics II

Class 05: Device Physics II Topics: 1. Introduction 2. NFET Model and Cross Section with Parasitics 3. NFET as a Capacitor 4. Capacitance vs. Voltage Curves 5. NFET as a Capacitor - Band Diagrams at V=0 6. NFET as a Capacitor - Accumulation

More information

ECE315 / ECE515 Lecture-2 Date:

ECE315 / ECE515 Lecture-2 Date: Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Scaling Issues in Planar FET: Dual Gate FET and FinFETs Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar

More information

CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012

CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN. Hà Nội, 9/24/2012 1 CHAPTER 3: TRANSISTOR MOSFET DR. PHAM NGUYEN THANH LOAN Hà Nội, 9/24/2012 Chapter 3: MOSFET 2 Introduction Classifications JFET D-FET (Depletion MOS) MOSFET (Enhancement E-FET) DC biasing Small signal

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

The K-Input Floating-Gate MOS (FGMOS) Transistor

The K-Input Floating-Gate MOS (FGMOS) Transistor The K-Input Floating-Gate MOS (FGMOS) Transistor C 1 V D C 2 V D I V D I V S Q C 1 C 2 V S V K Q V K C K Layout V B V K C K Circuit Symbols V S Control Gate Floating Gate Interpoly Oxide Field Oxide Gate

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

Appendix 1: List of symbols

Appendix 1: List of symbols Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination

More information

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS 98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC

More information

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

More information

Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS )

Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS ) Studio 3 Review MOSFET as current source Small V DS : Resistor (value controlled by V GS ) Large V DS : Current source (value controlled by V GS ) 1 Simulation Review: Circuit Fixed V GS, Sweep V DS I

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

More information

Lecture 14: Electrical Noise

Lecture 14: Electrical Noise EECS 142 Lecture 14: Electrical Noise Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2008 by Ali M. Niknejad A.M.Niknejad University of California, Berkeley EECS 142 Lecture 14 p.1/20

More information

Digital Electronics Part II - Circuits

Digital Electronics Part II - Circuits Digital Electronics Part - Circuits Dr.. J. Wassell Gates from Transistors ntroduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits The

More information

LAYOUT TECHNIQUES. Dr. Ivan Grech

LAYOUT TECHNIQUES. Dr. Ivan Grech LAYOUT TECHNIQUES OUTLINE Transistor Layout Resistor Layout Capacitor Layout Floor planning Mixed A/D Layout Automatic Analog Layout Layout Techniques Main Layers in a typical Double-Poly, Double-Metal

More information

MOSFETs - An Introduction

MOSFETs - An Introduction Chapter 17. MOSFETs An Introduction Sung June Kim kimsj@snu.ac.kr http://helios.snu.ac.kr CONTENTS Qualitative Theory of Operation Quantitative I Relationships Subthreshold Swing ac Response Qualitative

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -

Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two - 6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large

More information

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation

Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Lecture 5 Review Current Source Active Load Modified Large / Small Signal Models Channel Length Modulation Text sec 1.2 pp. 28-32; sec 3.2 pp. 128-129 Current source Ideal goal Small signal model: Open

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the

More information

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150

More information

Analysis and Design of Analog Integrated Circuits Lecture 14. Noise Spectral Analysis for Circuit Elements

Analysis and Design of Analog Integrated Circuits Lecture 14. Noise Spectral Analysis for Circuit Elements Analysis and Design of Analog Integrated Circuits Lecture 14 Noise Spectral Analysis for Circuit Elements Michael H. Perrott March 18, 01 Copyright 01 by Michael H. Perrott All rights reserved. Recall

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current

More information

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers 6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,

More information

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information

Workshop WMB. Noise Modeling

Workshop WMB. Noise Modeling Workshop WMB Noise Modeling Manfred Berroth, Markus Grözing, Stefan Heck, Alexander Bräckle University of Stuttgart, Germany WMB (IMS) Parameter Extraction Strategies For Compact Transistor Models IMS

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Electronic Circuits Summary

Electronic Circuits Summary Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent

More information

Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type

Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type Complete Surface-Potential Modeling Approach Implemented in the HiSIM Compact Model Family for Any MOSFET Type WCM in Boston 15. June, 2011 M. Miura-Mattausch, M. Miyake, H. Kikuchihara, U. Feldmann and

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Extensive reading materials on reserve, including

Extensive reading materials on reserve, including Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

MOS Capacitors ECE 2204

MOS Capacitors ECE 2204 MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field

More information

The Physical Structure (NMOS)

The Physical Structure (NMOS) The Physical Structure (NMOS) Al SiO2 Field Oxide Gate oxide S n+ Polysilicon Gate Al SiO2 SiO2 D n+ L channel P Substrate Field Oxide contact Metal (S) n+ (G) L W n+ (D) Poly 1 Transistor Resistance Two

More information

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >

More information

EKV MOS Transistor Modelling & RF Application

EKV MOS Transistor Modelling & RF Application HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology,

More information

EE 434 Lecture 12. Process Flow (wrap up) Device Modeling in Semiconductor Processes

EE 434 Lecture 12. Process Flow (wrap up) Device Modeling in Semiconductor Processes EE 434 Lecture 12 Process Flow (wrap up) Device Modeling in Semiconductor Processes Quiz 6 How have process engineers configured a process to assure that the thickness of the gate oxide for the p-channel

More information

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste

More information

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

EE 560 MOS TRANSISTOR THEORY

EE 560 MOS TRANSISTOR THEORY 1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information