Compact Models for Giga-Scale Memory System. Mansun Chan, Dept. of ECE, HKUST

Transcription

1 Compact Models for Giga-Scale Memory System Mansun Chan, Dept. of ECE, HKUST

2 Memory System Needs BL0 Bitline Precharge Circuits BLn WL Read Address Address Decoder H.-S. P. Wong, Stanford Timing Circuits Sensing Circuits Dout (n-bit) v We are entering the age of Tera-byte of memory system v Memory are closely coupled to memory specific control signal v Need to perform simulation over a large memory array with many cells

3 Describing the Behavior of a Memory Device I in Compact Model Ab initio atomic simulation Resistance Model R PCM V fraction Set Programming I SET R SET C SET V control Reset Programming V RESET V sub I sub R sub C sub I out Temperature Sensing Grid based simulation v Compact model is the only choice for simulation of large scale system

4 Many Memory Modeling Papers Published

5 No Standard Memory Model in SPICE Yet v No standard models in Commercial SPICE or plans from the Compact Model Coalitions

6 Traditional Circuit Elements Device equations Constant bias V Word line V PL f PL Bit line M L1 M L2 M Ln f B C BL µ WC é ox I Dlin = VG -V L ë µ WCox I = V -V 2L ( ) 2 Dsat G T 2 V ù ê( ) - DS T VDS ú û Parameter set V T =0.7, C ox =xxx, W=xxx, L=xxx 2 t Device characteristics I conventional v The devices are static over time t

7 Memory Elements Device equations Constant bias V Word line V PL f PL M L1 Bit line M L2 f B C BL µ WC é ox I Dlin = VG -V L ë µ WCox I = V -V 2L ( ) 2 Dsat G T 2 V ù ê( ) - DS T VDS ú û Parameter set V T =f(t), C ox =xxx, W=xxx, L=xxx 2 t Device characteristics I conventional v Memory devices may change states over time with respect to operation memory t

8 Memory Simulation Methodology v Need an internal state variable to keep track on the state of the device for each instance instant parameters model parameters X1 1 0 L=1u W=1u Q=10p Vt=0.7.MODEL XMEM (VTO=-0.8V KP=16U ) SPICE input deck v The state variable has to be a dynamic variable changes with both terminal voltages (or currents) and time! "! #, Δ# ; '! #, Δ#

9 Simulating Time Dependence Property in Memory v Example: in FLASH memory, the floating gate charge is integrated " % / = " % /12 + Δ" #$ %, Δ% $ 4 % / = 5 " % / ( Δ" #$ %, Δ% = ) ()*+, - #$ %.% n+, - #$ % n+ " % / Constant bias V Constant bias Q(t) Constant bias V t (t) t t t

10 Physical Modeling v Relating electrical performance to physical geometries and material properties v In PCM, it is the dimension and material composition of the active region v in RRAM, it is the dimension and resistivity of the filament v An explicit equation to calculate the electrical property (e.g. resistance) from the physical parameters is needed

11 Defining Initial States v How to define at the initial values of the internal state variables? v Users maybe asked to enter the values Ø How to extract these parameters from observable measurement results? v Let users input some physically measureable quantity like resistance and the state variables are internally extracted? Ø No guarantee it can be achieved v Assume all cells start from one of the states and a pre-program run is needed if some cells starts with a different states

12 SPICE friendly implementation v The time dependence of the state variable should be expressed in term of time increment (Dt) instead of absolute time v For example, the popular Johnson-Mehl-Avrami (JMA) equation for PCM crystallization v Two methods: f ( ) 1 C t = -e - Kt K = K e 0 ì ï í ïî k B -E a é ë D T+ T top ü ï ý ù ûïþ Mathematical Equivalence Subcircuit (K. C. Wong et. al. EDSSC 2009) D C = f ( Cf ) 21- Dt 2 K + Dt

13 Reducing Simulation Time v Many memory models are based on macro-model approach with many internal nodes I in Resistance Model R PCM Set Programming V fraction V control Reset Programming I SET R SET C SET V RESET V sub I sub R sub C sub K. Sonoda, Renesas Technology I out Temperature Sensing v There are many internal nodes v Example, the temperature model for a PCM cell

14 Effects of Internal Nodes v Jacobian Matrix in SPICE + "# $ + "# $ "% $ "% ' + "# ' "% $ + "# ' "% ' *+, % $ -.$ % ' -.$ = # $ - # ' - + "# $ + "# $ "% $ "% ' + "# ' "% $ + "# ' "% ' *+, % $ - % ' - v Each internal node will create one entry in the matrix v As these nodes are isolated from other nodes, they directly increase the size of the Jacobian matrix v Example: one internal node will double the size of the matrix of an nxn array v Simulation time increase with O(n 1.4 )

15 Eliminating Internal Nodes v Jacobian Matrix in SPICE!" #!$ # 0 0!" )!Δ+,-. $ # /0# Δ+ /0# = " # / " ) /!" #!$ # 0 0!" )!Δ+,-. $ # / Δ+ / v As the node is loosely coupled, it can be directly evaluated without putting into the Jacobian matrix

16 Eliminating Internal Nodes v Jacobian Matrix in SPICE!" #!$ # 0 0!" )!Δ+,-. $ # /0# Δ+ /0# = " # / " ) /!" #!$ # 0 0!" )!Δ+,-. $ # / Δ+ / v As the node is loosely coupled, it can be directly evaluated without putting into the Jacobian matrix æ ö ç ë û è th ø C 1 th n+ 1 n n Cth + DTi = I é i D T ù i Vi + DTi - h R h 1

17 Simulation Flow v The internal node can be eliminated without making any differences (a) n th iteration, t i T n, V n (b) n th iteration, t i T n, V n Calc I n (T n,v n ) Calc I n (T n,v n ) n=n+1 Matrix with I n, T n,v n Obtain T n+1, V n+1 n=n+1 Calc T n+1 (I n,v n,t i-1 ) Matrix with V n,i n Obtain V n+1 N Conv? N Conv? Y Y Lining Zhang et. al., JEDS Jan. 2018

18 Convergence Issues v Some model contain switches causing convergence problem v a generic smoothing hysteresis function can be used I in Resistance Model R PCM K. C. Wong et. al. EDSSC 2009 Set Programming I SET R SET V fraction C SET V control Reset Programming V RESET 7 % = 7 %! "#$ % %! h23h % I sub R sub V sub C sub! "#$ % = )*+ % % -./ 0 I out Temperature Sensing! h23h % = )*+ % % S is a hysteresis function between 0-1 with V low and V high as the two triggering point

19 Some Dynamic Behavior v Some oscillation is observed with static signal input ϕ PL I prog Bit Line ϕ B M L0 M L1 M Ln C BL W L0 W L1 W L0 I prog C BL PCM R load GND

20 Possible Explanation TE TE v E > E crit, conductive filament path forms due to generation of excess carriers Crystal Amo (a) BE Crystal Amo (b) BE v The abrupt change of conductivity causes the voltage to drop Crystal TE Crystal TE v The high current is sustained by the excess charge and not able to disappear immediately with the voltage drop v Some partial crystallization takes place in the active region and a lower E-field is needed to triggler the next event Amo (c) Crystal Amo (e) BE TE BE Amo (d) Crystal Amo (f) BE TE BE

21 Current (A) Voltage (V) Threshold voltage for switching 1.0x x x x x10-4 SET Operation RESET Operation Threshold Voltage Voltage (V) Decreasing Threshold Voltage Increasing Recovery Voltage Time (µs) v Threshold voltage decreases with the increase in crystalized volume with less voltage for filament formation v Recovery voltage increase when the filament resistance is smaller than the crystallization region resistance

22 Filament Formation Model v Can be modelled with the hysteresis function with a time delay ( 1 C f ) s f - g f = é1 - Sf V z ë S f ( V) ' act 1 = æv -V ö T 1+ exp ç V è Sf ø ( ) ù û ( 1- C f ) g s f f g f = Sf ( V) + é1 - S ' f V 1+ exp éa( t td ) z ë ë - ùû zct ( ) k 4.0k 2.0k ù û Voltage Temperature Active Dimension Time (µs)

23 Dual Resistance Model v A dynamic resistor is added in parallel with the active region resistance which has a dynamic dependence on voltage across it v To reduce simulation time, the resistance is implemented as! "#$ =! # +! '! (! ' +! (

24 Simulation Example v Simulation of a PCM cell array without speed and convergence problems I bias V dd CTL BL0 BL1 BLm-1 BLm V REF CLR V out WL0 ck/ck WL1 V BL0 0 4 V WL0 0 1m I prog WLn-1 V out V pcm WLn C f R pcm 0 600k Time(µs)

25 Current (ma) How to do DC Simulation? v How to handle memoryless simulation? v Need to track the state variables when they are biased at steady state v May results in oscillation during iteration as the state-variable switches from one state to the other v Smoothing function is needed Crystalline state (experimental) Amorphous state (experimental) Crystalline state (simulation) Amorphous state (simulation) Crystalline transition transition amorphous Voltage (V) v Need some mechanism to prevent unnecessary switching of states

26 Summary v Memory device models have significant values for due to recent demand for abundant data application v The circuit simulation infrastructure is not designed for memory type of devices v Need to link physical changes to electrical characteristics v Linking dynamic physical behavior to electrical behavior v How to handle time dependent versus DC simulation?

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