MUDDLE Chip Report. David Harris December 6, 2003
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1 MUDDLE Chip Report David Harris December 6,
2 Table of Contents Introduction...2 Specifications...3 Chaos Generator...3 Random Logic...4 Circuit Families...4 Process Parameter Test Structures...4 Pinout Diagram...5 Actual Operation...6 Verification...7 Test Plan...7 Simulation Test Plan...8 Summary of Files...9 Schematics Layout Introduction The 2003 Freshman Digital Electronics and Chip Design seminar has designed and built a test chip named MUDDLE. The chip contains a number of logic circuits, some of which are functional and some of which are not. The circuits are intended to serve as a teaching tool to illustrate hardware test and debug for VLSI courses. The test chip is implemented on a MOSIS 1.5x1.5 mm TinyChip in the AMI 0.5 micron process (λ = 0.3) in a 40-pin DIP package. It was developed using the Electric CAD suite. The chip was designed by Amir Adibi, Fang-Yuan Chang, Ted Jiang, Cary Kawamoto, Pyry Matikainen, Joshua Utter- Leyton, Ivan Ventura, and Stephen Yu with George Koirr as lab assistant. 2
3 Specifications MUDDLE has the following inputs and outputs: Inputs Outputs reset Chaos7 Chaos0 phi1, phi2 InvRing, NandRing, Inv4xRing, Nand4xRing NMOSG, PMOSG NMOSS, NMOSD, PMOSS, PMOSD A, B, C, D DynamicInv, DynamicNand, DynamicNor, PseudoInv, DominoAnd Rand1, Rand2, Rand3 The chip also has 4 VDD pins and 4 GND pins. MUDDLE has four major units: the Chaos Generator, the Process Parameter Structures, the Circuit Families, and the Random Logic circuits. Each is described further below. Note that this section describes specification of how the chip ought to function if they had no errors. Errors were introduced into some of the units. These errors will be described in the Actual Operation section.. Chaos Generator (Pyry, Ted, and Ivan) The Chaos Generator accepts a reset signal and two-phase nonoverlapping clock. It produces eight Chaos outputs intended to drive LEDs. The outputs will initialize to a known state on reset, the follow a chaotic pattern on each clock cycle. The Chaos Generator may be viewed as a finite state automata. On reset, Chaos2-4 is initialized high and the others are initialized low. On each subsequent cycle, each output depends on its previous value and the values of its two neighbors according to the following rule Chaos[i-1] Chaos[i] Chaos[i+1] New Chaos[i] Thus the Chaos Generator should trace out the following pattern: Step Chaos[0] Chaos[1] Chaos[2] Chaos[3] Chaos[4] Chaos[5] Chaos[6] Chaos[7]
4 Random Logic (Amir & Josh) The circuit is supposed to compute the following logic table ( ABCD ): A B C D Rand1, 2, There are three copies of the circuit. Some of the copies may be good, while others may be bad. Circuit Families (Fang-Yuan and Cary) The circuit consists of five gates GATE that takes input INPUT and gives output OUTPUT as follows: GATE INPUT OUTPUT Dynamic NAND A, B, phi DynamicNand Dynamic NOR A, B, phi DynamicNor Dynamic Inverter A, phi DynamicInv Domino AND4 A, B, C, D, phi DominoAnd Pseudo-nMOS Inverter A PseudoInv Phi comes from the Phi1 input to the chip. Process Parameter Test Structures (George and Stephen) This portion of the chip contains four 49-stage ring oscillators. The oscillators are made of fanout-of-1 and fanout-of-4 inverters and NAND gates. The output of the oscillators is buffered and drives a pin off chip. By measuring the frequencies of the oscillators, one should be able to deduce τ, p inv, and the logical effort and parasitic delay of a NAND gate. It also contains 12-λ wide nmos and pmos transistors. The substrate and well are tied to GND and VDD, respectively. The source, drain, and gate of each transistor are tapped out to analog pads to measure transistor I-V characteristics. 4
5 Pinout Diagram GND Chaos0 Chaos1 Chaos2 Chaos3 Chaos4 Chaos5 Chaos6 Chaos7 VDD GND NMOSG NMOSD NMOSS PMOSG PMOSD PMOSS phi1 phi2 VDD Chaos Generator Process Parameter Test Structures Random Logic Circuit Families GND Rand1 Rand2 Rand3 D C B A Domino AND VDD VDD InvRing NandRingInv4xRing Nand4xRing Dynamic Inv Dynamic Nand Dynamic Nor Psuedo Inv GND 5
6 Summary of Files The master files needed to recreate the project are \\Charlie\Courses\Engineering\E158\fys1\MuddleFinal They include: muddle.elib: muddpads_ami05.elib: chip.cif: muddle.cmd: muddle.arr: muddle.arr the top-level design pad frame with HMC logo master CIF file IRSIM command file to test qbert pad arrangement file for layout pad arrangement file for schematic 9
7 chip Schematics 10
8 core chaos2 11
9 autologic register8bit reset8bit 12
10 RandomFinal random random_close random_wire 13
11 Families Dynamic_NAND Domino_And 14
12 Dynamic_NOR pseudo_n-mos Dynamic_inv 15
13 processparameters pmos nmos ringoscinv ringoscnand ringoscinv4 ringoscnand4 16
14 inv4 nand4 17
15 Layout muddle 18
16 core chaos2 19
17 autologic register8bit 20
18 reset8bit RandomFinal 21
19 random random_close 22
20 random_wire Families 23
21 Dynamic_NAND Domino_And Dynamic_NOR 24
22 pseudo_n-mos Dynamic_inv processparameters 25
23 pmos nmos ringoscinv ringoscnand ringoscinv4 ringoscnand4 26
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