Carbon Inside: Next-Generation Interconnects for Green Electronics. Kaustav Banerjee

Transcription

1 17 th IEEE Workshop on Signal and Power Integrity, Paris, France, May 12-15, 2013 UC Santa Barbara Carbon Inside: Next-Generation Interconnects for Green Electronics Kaustav Banerjee Department of Electrical and Computer Engineering Nan

2 Energy Consumption in IT Industry: Significant Fraction due to Data Centers Data center 41% 28% 31% IT equipment Power delivery Cooling IT equipment 63% 22% 15% Computer servers Storage servers Communication devices 31% 8% Computer servers 6% 13 % 4% 16% 20% Source: data center efficiency in the scalable enterprise, Dell power solutions, Feb CPUs CPU voltage rgulator loss Memory Miscellaneous components Chipset Power supply loss Hard disk drives

3 Why does Green Electronics Matter? CO2 (Million Metric Tons) -24% % % -33% Transportation Industruial Residential Commercial With Green Electronics Without Green Electronics With improved efficiency of IT usage, around 30% reduction per year in GHG is achievable, which is equivalent to gross energy and fuel savings of 315 billion U.S. dollars!!! Source: 2009 U.S. Greenhouse Gas Inventory Report, April

4 Relative On-Chip Communication On-die Global IC energy/mm Compute Energy 0.8 Interconnect Energy X X Technology (nm) S. Borkar (Intel) On-die global interconnect energy scales slower than compute On-die data movement energy will start to dominate Need Green Interconnections

5 J max (A/cm 2 ) Interconnect Reliability Requirements 2009 ITRS Revision Required current density is increasing with scaling Maximum allowed current density for Cu wire is decreasing Courtesy: ITRS Interconnect working group Also, see: Global (Interconnect) Warming, IEEE Circuits & Devices Magazine, Vol. 17, No. 5, pp , Sept Red Areas: no known solutions! from 2015 onwards Need Reliable Interconnections

6 Leakage (Wasted) Power in Active Devices Need Green Transistors

7 So, How can we design Green Electronics? I will use Carbon nanomaterials

8 Forms of Carbon allotropes 3D: diamond graphite 2D: graphene Carbon atom can form several distinct types of valence bonds. 1D: nanotube nanoribbon 0D: fullerenes

9 Crystal & Band Structure of Graphene Zero bandgap Linear E-k near Dirac point Close to zero effective mass Electrons and holes are equal

10 2D and 1D Carbon Nanomaterials Graphene: Thinnest 2D Crystal Roll-up Stack and Pattern Pattern Carbon Nanotubes Graphene Mono-layer Graphene Nano-Ribbon (GNR) Single-wall: 1/3 metallic Multi-wall: all conducting GNR Bandgap: inversely proportional to its width Multi-layer GNR

11 Superb Properties of CNT and Graphene Max current density (A/cm 2 ) Si Cu SWCNT MWCNT >1x10 9 Radosavljevic, et al., >1x109 Wei, et al., Appl. Phys. Lett., Phys. Rev. B, Melting point (K) (graphite) Tensile strength (GPa) ± Graphene or GNR >1x10 8 Novoselov, et al., Science, 2001 Mobility (cm 2 /V-s) 1400 >10000 >10000 Thermal conductivity ( 10 3 W/m-K) Temp. Coefficient of Resistance (10-3 /K) Mean free path room temp Hone, et al., Phys. Rev. B, 1999 <1.1 Kane, et al., Europhys. Lett., 1998 >1,000 McEuen, et al., Trans. Nano., Kim, et al., Phys. Rev. Lett., Kwano et al., Nano Lett., ,000 Li, et al., Phys. Rev. Lett., Balandin, et al., Nano Lett., Shao et al., Appl. Phys. Lett., 2008 ~1,000 Bolotin, et al., Phys. Rev. Lett., 2008

12 Circuit Model.for Predictive Analysis H. Li, C. Xu, N. Srivastava, and K. Banerjee TED, vol. 56, no. 9, pp , 2009 For SWCNTs and GNRs R mc /2 R Q /2 L M R Q /2 R mc /2 R S L K Driver Distributed C Q C E Load For MWCNTs (includes DWCNTs) R t Driver C out R mc /2 R Q1 /2 R Q2 /2 R Qp /2 R S2 L K1 R Sp L K2 L Kp R S1 C Q1C Q2 C S1 Distributed Elements M 12 L M1 M 1p L M2 G T1 L Mp G Tp-1 C E CQp C Sp-1 R Q1 /2 R Q2 /2 innermost shell R Qp /2 p 2 R mc /2 1, outermost shell Parameters extracted from available experimental data. C Load Load

13 Delay Comparison: Intermediate and Global SWCNT ( Fm=1) SWCNT (Fm =1/3) DWCNT (D=1.5nm) MWCNT (D=14nm) d-gnr ( p =0.41) d-gnr ( p=1) Delay Ratio w.r.t Cu Intermediate Length of Interconnect [ m] Delay Ratio w.r.t Cu nm technology node Global Length of Interconnect [ m] Almost all CNTs could outperform Cu (> 2x faster) H. Li et al., TED, vol. 56, no For GNR, intercalation doping and high specularity are needed

14 Interconnect Power Dissipation 51% 34% N. Magen et al., SLIP, pp. 7-13, Interconnect Logic (gate capacitance) Logic (diffusion capacitance) 15% Interconnect Delay Optimization under Power Constraints L l l FF FF FF s s s s s s Clock Clock Clock K. Banerjee and A. Mehrotra IEEE TED, vol. 49, no. 11, pp , 2002.

15 Low Power Interconnects Inverter insertion configuration: Cu SWCNT Fm=1 MWCNT GNR p=1 s s s s s Lower delay allows larger distance between inverters, thus reduces the power s s s Percentage (%) nm 14 nm If delay is kept identical to Cu optimal delay CNT/GNR global interconnect could save ~50% power!! H. Li, C. Xu and K. Banerjee, Carbon Nanomaterials: The Ideal Interconnect Technology for Next-Generation ICs IEEE Design and Test, vol. 27, no.4, pp , 2010

16 High-Frequency Behavior of CNT Bundle H. Li and K. Banerjee, TED, vol. 56, no. 10, 2009 I 2 E j E Skin Depth [ m] y z x E z W SW, D= 1nm, Fm=1/3 SW, D= 1nm, Fm= Frequency [GHz] H MW, D=40 nm MW, D=20 nm Cu τ~1 τ<< [( ) 1] ( ) 1 0 ~ s for standard metals > s for CNTs (Large Kinetic Inductance) CNT: skin depths saturate after certain frequencies Saturation depends on the momentum relaxation time ( ) MWCNT has largest skin depth and lowest saturation frequency due to large MFP or

17 Low Loss CNT Interconnects Resistance [ ] Cu wire SWCNT D=1nm, Fm=1 MWCNT D=20nm MWCNT D=40nm Length = 500 m Width=2 m, Height=1 m Frequency [GHz] Inductance [nh] MWCNT D=40nm MWCNT D=20nm SWCNT D=1nm Fm=1 Cu wire Length = 500 m Width=2 m, Height=1 m Frequency [GHz] H. Li and K. Banerjee, TED, vol. 56, no. 9, 2009 SWCNT: resistance/inductance saturates at high frequencies MWCNT: negligible shift in resistance/inductance Significantly reduced skin effect in CNT interconnects!

18 High-Q CNT/GNR based Low-Loss Inductors Quality Factor sub = 10 -cm Cu SWCNT Fm=1/3 SWCNT Fm=1 MWCNT D=10nm MWCNT D=20nm MWCNT D=40nm 142% H. Li and K. Banerjee, TED, vol. 56, no. 9, 2009 CNTs can provide better performance than Cu MWCNT gives 2.4X higher Q factor than that of Cu GNR shows an improvement of: ~20% over Cu ~50% over 1/3 metallic SWCNT Quality Factor Frequency [GHz] 50 GNR p=0 sub = 10 -cm GNR p=1 40 Cu SWCNT, Fm=1/3 MWCNT, D=10 nm 30 (a) Frequency (GHz) 10 D. Sarkar, C. Xu, H. Li and K. Banerjee, TED, Vol. 58, March 2011.

19 CNT based Through-Si-Vias for 3-D ICs Why Carbon Nanotubes for TSVs? High electrical and thermal conductivity Large current carrying capacity Reduced skin effect Bottom-up growth high aspect ratio K CNT [W/m-K] SW,D=0.47 nm SW,D=0.7 nm SW,D=1 nm MW,D=5 nm MW,D=10 nm T= 400K Length [nm] H. Li et al., IEEE TED, 58(8), Resistance (m / m) SWCNT: D = 1 nm, 1/3 Metallic MWCNT: D = 20 nm SWCNT MWCNT Cu W T. Xu et al., APL, Frequency (Hz) C. Xu et al., IEEE TED, 57(12), TSV Analysis

20 480 nm CNT Based High-Density Capacitors H. Li, C. Xu, N. Srivastava, and K. Banerjee, TED, vol. 56, no. 9, pp , 2009 Take advantage of bottom up approach to achieve high aspect ratio d 210 nm 460 nm 20 nm 20 nm (a) Circular Height = 1 m Electrostatic capacitance density (ff/μm 2 ) Total effective capacitance density (including C Q, ff/μm 2 ) Circular Square (Dense, d = 0.34 nm) Square (Sparse, d = 20 nm) 20 nm 20 nm (b) Square Much larger than ITRS requirement for 2014: 7 ff/ m 2

21 H. Li, C. Xu, N. Srivastava, and K. Banerjee, Carbon nanomaterials for next generation interconnects and passives: Physics, status, and prospects, TED, vol. 56, no. 9, pp , 2009.

22 CNT Interconnect Fabrication.Top-down Via Process all MWCNTs [Kreupl et. al., (Infineon) IEDM, 2004] [Sato et. al., (Fujitsu) IITC, 2006] [Awano et al., (Fujitsu) 2006] [Choi et. al., (Samsung), 2006] [Nihei et. al., (Fujitsu) IITC, 2007] [Dijon et. al., (LETI) 2009]

23 Status of Horizontal CNT Bundles Long CNTs are grown individually or in sparse monolayer array Not interconnects S. J. Kang et al., Nature Nano., 2007 Some good attempts (but short lengths ) Fujitsu s tryouts Courtesy: M. Nihei, Fujitsu Plasma induced E-field in-situ growth Y. Chai et al., APL, 2009 Law et al., APL, 2007

24 First Demonstration of Long Horizontal CNT Bundle UCSB [H. Li et. al., (UCSB), to appear in IEEE-TED, Sept. 2013] Longer than 120 m horizontal CNT bundle Thickness ranges from 100nm 2 m 50 m Raman TEM SEM

25 Characterization of Horizontal CNT Bundle Interconnects [H. Li et. al., (UCSB), to appear in IEEE-TED, Sept. 2013] W30-T7 W30-T14 W30-T21 W30-T28 TLM Measurement Result Linear TLM curves prove the success of our process Resistivity < 2 m -cm, the lowest reported value for H-CNT bundle (2-100 m -cm for other works) Still more than 100x higher resistivity than same size Cu (~2 m-cm) To lower the resistivity: (1) higher density; (2) smaller diameter; (3) higher quality of as-grown CNT

26 First Demonstration of Horizontal CNT Bundle Based Manhattan Structure [H. Li et. al., (UCSB), to appear in IEEE-TED, Sept. 2013] First demonstration of a Kanji (b) character using horizontal CNT bundles 100 m

27 Fabrication of First CNT Inductor [H. Li et. al., (UCSB), to appear in IEEE-TED, Sept. 2013] First time demonstration of CNT bundle based inductor Single turn with diameter m Segment width m, thickness 300nm - 2 m 100 m

28 CMOS Scaling and Energy Issue Dimension scaling Oxide thickness scaling V DD scaling Increase transistor density Higher Performance Energy Efficiency E V DD 2 log(i D ) High Off Current Low Off Current V DD scaling Solution to leakage Issue: Steeper turn on Aggressive scaling leads to an exponential increase in leakage power!!! V G

29 Ideal-Switch: Greenest Transistor! An ideal switch Drain current (log(id)) Δlog(I d ) ΔV gs Solid-state devices S = ΔV gs /Δlog(I d ) V th Gate voltage (V gs ) Subthreshold Swing (S) should be as low as possible!!

30 MOSFET vs. Tunnel-FET Source Gate Oxide Drain n + Channel n + p Source Gate Oxide Drain p + i Channel n( + ) Oxide Gate E C (Leakage) OFF Current barrier(φ bi ) barrier(e g ) E C (Nearly No Leakage) OFF Current Source E V Drain Source E V Drain Channel Channel Source E C E V Channel S 60 mv/decade (Tunnel Current) ON Current ON Current Drain Source Channel Drain Y. Khatami and K. Banerjee, TED, vol. 56, no. 11, S << 60 mv/decade

31 Graphene for Tunnel-FET Source Gate Drain E g1 W 1 E g2 W 2 C - Heterojunction GNR T-FET 1x10-3 Due to their ZERO BANDGAP Graphene is a great material for Tunnel-FETs.. I DS (A/ m) 1x10-5 1x10-7 1x V DD =0.5 V R C =13 k L g =20 nm W1(nm) W2(nm) V GS (V) I ON = 1 ma/μm, I ON /I OFF = 10 9, SS = 10 mv/dec V DD = 0.5 V, and L ch = 20 nm Y. Khatami, M. Krall, H. Li, C. Xu and K. Banerjee, Device Research Conference, 2010, pp

32 All-Graphene Monolithic Logic Circuits Patterning by Deposition and Doping Lithography Patterning Source andofdrain metal and oxide VDD Graphene interconnects Via N+ Inverter 1 VIN GNR PTFET GNR i PTFET P VG1 VOUT2 VG2 V N-Drain OUT i-channel GNR P+-Source NTFET GND Via VIN Inverter 2 Graphene interconnects Inverter 1 VOUT Inverter 2 (Size=2) (Unit size) VOUT2 J. Kang, D. Sarkar, Y. Khatami and K. Banerjee, UCSB, (2013) under review Kaustav Banerjee, UCSB MRS Fall Symposium, Nov 30, 2010, IEEE SPI,Boston, Paris, MA May 14, 2013 Nan

33 Performance Evaluation 22nm-CMOS (Low Power Model) 22nm-CMOS (High Performance Model) All-Graphene Monolithic Logic Circuits Noise Margin (/V DD ) Minimum Delay (s) Inverter Noise Margin V DD (V) Inverter Delay V DD (V) P dym (W)(Log) Inverter Gain V DD (V) Power Consumption Max Frequency (Hz) Inverter Gain

34 Graphene FETs with Record Mobility: synthesized using CVD; controlled synthesis of monolayer and bilayer graphene demonstrated W. Liu, H. Li, C. Xu, Y. Khatami and K. Banerjee, "Synthesis of High-Quality Monolayer and Bilayer Graphene on Copper using Chemical Vapor Deposition," CARBON, Vol. 49, No. 13, pp , 2011.

35 First ESD Characterization of Graphene (UCSB/Intel) H. Li, C. Russ, W. Liu, D. Johnsson, H. Gossner and K. Banerjee, 34 th EOS/ESD Symp., 2012, pp It2 per Micron (ma/ m) layer 3 layer TLP Currrent (ma) W=3.8 m L = TLP Voltage (V) open 0 a b c d e f Devices Breakdown current: 4.5mA/ m for 100 ns TLP and 8mA/ m for 10 ns TLP Maximum Current density: 2-5x 10 8 A/cm 2 Graphene devices show clear open cut in the channel after breakdown

36 First Proposal for Tunnel-FET Biosensors: Ultra-Low Power and Ultra-Sensitive CNT and Graphene are excellent candidates. D. Sarkar and K. Banerjee, APL, 100, , 2012.

37 TFET Biosensor in Research Highlights of Nature Nanotechnology (May 2012)

38 PNAS 2005 Beyond-Graphene 2D-Materials Transition Metal Dichalcogenides TMD Family Layered; hexagonal ev Bandgaps Demonstration of exfoliated MoS 2 Measured mobility 0.5 ~ 3 cm 2 /Vs Low gate modulation

39 High Performance Monolayer n-type WSe 2 FET a b (a) 3L 2L c 1.6 ev 1L Monolayer WSe 2 with a bandage of ev Optical contrast and Raman mapping can estimate thickness of few layer WSe 2 High mobility: 142 cm 2 /V.s Record On Current : 210 µa/µm L: 3.5µm W: 3µm W. Liu et al., Nano Letters, Vol. 13, no. 5, pp , 2013.

40 Conclusion 2D dielectric E 2D metal 2D semiconductors k x k y N B h-bn Bandgap: 5 ev Graphene Bandgap: 0 ev Transition Metal Dichalcogenides MoS 2, WSe 2, etc. Bandgap: ev Graphene and emerging 2D materials offer unique platform for designing energy-efficient green electronics Carbon-based interconnects/electrodes as well as active devices could provide unprecedented opportunities

41 Acknowledgments NRL Members: Wei Liu Postdoctoral Fellow PhD 2008, Institute of Chemistry- Chinese Academy of Sciences Navin Srivstava PhD March 2009 now with Mentor Graphics, R&D group, Oregon Hong Li PhD Sept 2012 now with Micron Technology, R&D group, Idaho Deblina Sarkar PhD Candidate Chuan Xu PhD June 2012 now with Maxim Integrated Systems, R&D group, Oregon Yasin Khatami PhD Candidate Xuejun Xie PhD Student Jiahao Kang PhD Student Wei Cao PhD Student