Equation Sheet Please tear off this page and keep it with you

Size: px
Start display at page:

Download "Equation Sheet Please tear off this page and keep it with you"

Transcription

1 ECE 30L, Exam Fall 05 Equatio Sht Plas tar off this ag ad k it with you Gral Smicoductor: 0 i ( EF EFi ) kt 0 i ( EFi EF ) kt Eg i N C NV kt 0 0 V IR L, D, τ, d d τ c g L D kt I J diff D D µ * m σ (µ + µ ) J dx dx A m V C ρ µ J drift σ E Juctios: kt! N a N d Vbi l i c DS ox! ε ε Na s 0 x V bi N d ( N a + N d )! ε ε Nd x s 0 Vbi N a ( N a + N d ) V! V a a! ε sε 0 N a + N d! ε sε 0 N a + N d kt kt x x W Vbi WRB Vbi + VR ) ( ) 0 ( ) 0 ( Na Nd Na Nd! (! Va + xl x (! Va +! x +x! kt L δ (x) 0 * kt - EF EFi + kt l EF EFi kt l δ (x) 0 * - *) -, *) -, i i! V!! Va Wi kta kt D D I 0 0 J J ID J S J S + gd DQ Cd ( I 0τ 0 + I 0τ 0 ) rc τ V L L r V 0 t d t MOS Caacitors: C ( acc ) Cox tox C ( dl )!ε tox + ox xd εs C mi!ε tox + ox xdt εs C FB VFB φ ms Qss φ s EFi Cox - ty: φms! ε ε φ E! φ χ + g + φ f φ f Vt l N a xd s 0 s N a i - ty: φms! ε ε φ E! φ m χ + g φ f φ f Vt l N d xd s 0 s N d i bulk EFi surf VTN QSD ( max) Cox! εε! ε ox s 0 tox + Vt εs N a,d + VFB + φ f VTP m QSD ( max) Cox! 4ε sε 0φ f xdt N a xdt! 4ε ε φ s 0 f N d + VFB φ f QSD ( max) N a xdt QSD ( max) N d xdt MOSFETs: gm! δ ( log ( I D )) δid gm gm SS δv ft π (C + C ) π C δvgs gst M G GS CM CgdT (+ gm RL ) W µ Cox W µ Cox Wµ C ID (VSG + VT ) VSD VSD I D ( sat ) (VSG + VT ) K ox k µ Cox - ty: L L L W µ Cox W µ Cox W µ Cox k µ Cox - ty: I D L (VGS VT ) VDS VDS I D ( sat ) L (VGS VT ) K L h π q.60x0 9 C Si at T 300 K: i.5x00 cm- 3, Eg. V, εs.7 SiO: εox 3.9 k 8.6x0 5 V / K.38x0 3 J / K h 4.4x0 5 V s 6.63x0 34 J s! kt 0.06 V at room tmratur

2 Exam Smicoductor Dvics ECE 30L, Exam Fall 05 Nam: Nt ID: 5 qustios. 0 oits r qustio. Partial crdit will b giv wh ossibl (MUST show work). Plas writ atly (lgibly). Wh giv, writ fial aswrs i th rovidd boxs. Show your work (NEATLY) whvr it is ossibl (us th back of ags if dd)! Good luck!

3 ECE 30L, Exam Fall 05 ) Juctio Diods Cosidr a silico juctio diod with ara of 0-4 cm at T 300K ad th followig aramtrs: - sid: N a 0 4 cm sid: N d 0 7 cm - 3 τ 0-7 s τ 0-6 s µ 00 cm /V- s µ 800 cm /V- s µ 400 cm /V- s µ 300 cm /V- s a. Sktch th thrmal quilibrium rgy bad diagram for this diod i th sac rovidd. B sur to iclud a accurat valu (ad rasoably accurat sktch) for E F E Fi o both sids of th juctio ad of V bi. B sur to labl E c, E v, E F, ad E Fi. Tak ach box to b 0.5 V o all sids b. Now sktch th rgy bad diagram udr a alid forward bias, V a 0.5 V. B sur to idicat V a i som fashio o your diagram ad sktch i th quasi- Frmi lvls. c. Calculat th amout of currt (I ) flowig through th diod if V a 0.5 V. I d. Comlt th qualitativ sktch (giv o th right) of th currt dsity i th diod, icludig th curvs for J total, J ad J o ach sid of th juctio ad labl J (- x ) ad J (x ). J. If this diod wr itgratd ito th circuit giv blow ad V a 0.5 V was th voltag drod across th diod, what would th voltag dro ad currt flow b for th rsistor? V a + ( x x x 3V kω VR IR

4 ECE 30L, Exam Fall 05 ) MOS Caacitors Giv th rgy bad diagram of a MOS caacitor o th right, with th aramtrs idicatd blow, aswr th qustios. V FB 0.06 V, Q ss 0, t ox 7 m, f 0 Hz, ϕ f V a. I th sac rovidd blow th bad diagram, sktch th bad diagram for wh th MOS caacitor is at V G 0 V, lablig E Fs, E Fi, E C, E V, ad ϕ s. E Fm 0.V E Fi E Fs 0.3V b. O th giv bad diagram, sktch i th alid gat voltag, V G. c. What is th alid gat voltag, V G? d. What is th doig ty ad dsity?. What is th surfac ottial? a. f. Calculat th thrshold voltag, V T. Is this MOS caacitor oratig i strog ivrsio? g. Sktch th C- V curv for this caacitor o th axs blow ad labl th oit at which th caacitor is oratig alog with V T, V FB, C ox, ad C mi. E Fm *Show your work (atly) whvr ossibl (us back of ag if dd)! g. C V G d. ty c.. VG N ϕs f. VT Strog Ivrsio?

5 3) MOS Caacitor CONCEPTUAL Aswr th qustios i th sacs rovidd: ECE 30L, Exam Fall 05 For th MOS caacitor bad diagram o th lft: a. Is th caacitor i thrmal quilibrium? b. Is th smicoductor i thrmal quilibrium? c. What ty of smicoductor is this? d. Dos ϕ ms 0 for this caacitor?. What olarity V G (ositiv or gativ) is dd to orat th caacitor i dltio mod? f. Sktch oto th bad diagram what would ha if V G ϕ f wr alid, showig all rlvat chags that would tak lac. g. What mod would th caacitor b oratig i with this alid voltag (from art f)? For th MOS caacitor C- V curv o th lft: h. Is th caacitor oratig at low or high f? i. What ty of smicoductor is this? j. Idicat o th curv whr th dltio mod of oratio is takig lac. k. Rdraw th C- V curv for th cas of havig som gativ fixd chargs addd to th oxid. l. Brifly dscrib what would ha to th C- V curv if itrfac tras wr rst? E Fm C M O S z E Fs E Fi V G For th MOS caacitor block charg diagram: m. What ty of smicoductor is this?. What mod is this caacitor oratig i? o. O th diagram, sktch i what would ha as a small ac sigal is alid to th caacitor.. O th diagram, sktch i what it would look lik to hav som ositiv fixd charg rst i th oxid. q. From this diagram, ca you tll whthr or ot V FB 0 V?

6 ECE 30L, Exam Fall 05 4) MOSFETs Cosidr a Si MOSFET with th charactristics show blow. Labl th ty of charactristics that ach lot shows o th lis blow th lots. S S charactristics charactristics Th voltag, V GS is coctd with th ositiv trmial to th gat of th MOSFET ad th voltag, V DS has th ositiv trmial to th drai. Th dvic has V DD V with V T V, t ox m, W µm, k k 0.50 ma/v, ad a load rsistac of 5 Ω. Aswr th qustios or xtract th aramtrs blow ad, wh ossibl, show how ach was xtractd o th lots. a) Subthrshold swig b) Trascoductac c) O- currt d) Is th MOSFET - ty or - ty? ) Mobility f) W/L g) If th gat ovrlas th drai by 0.*L, what will th cut- off frqucy b? ft

7 ECE 30L, Exam Fall 05 5) MOSFETs CONCEPTUAL Aswr th qustios i th sacs rovidd: For th MOSFET schmatic o th lft: a. If this is a - ty MOSFET, labl th sourc, drai, ad substrat rgios with th aroriat doig. b. Sktch i th dltio rgio ad ivrsio layr for th coditio wh th MOSFET is oratig i th liar rgio. c. Will thr b ovrla caacitac i this MOSFET? d. Which will b gratr, C gs or C gd?. O th schmatic, idtify th dimsio L. f. I th bad diagram startd to th right, sktch th MOS caacitor ortio of this MOSFET udr th abov coditios, lablig E Fs, E Fi, E C, E V, V SG, ad ϕ s. E Fm I D k V DD V SD DS For th curvs i th lot to th lft: g. Ca th thrshold voltag b dtrmid from this lot? h. What ty of MOSFET is this? i. Sktch th V DS (sat) li o th lot. j. If th d curv from th to is from V GS V DD, idicat th o- currt o th lot. k. I th mty schmatic giv blow, sktch th MOSFET from this lot oratig at th idicatd oit labld k. O your sktch, labl th sourc, drai, ad substrat rgios with aroriat doig ad iclud th dltio rgio ad ivrsio layr. If alicabl, labl L, ΔL, ad iclud th caacitacs C gd, C gd, C gs, ad C gs.

Solid State Device Fundamentals

Solid State Device Fundamentals 8 Biasd - Juctio Solid Stat Dvic Fudamtals 8. Biasd - Juctio ENS 345 Lctur Cours by Aladr M. Zaitsv aladr.zaitsv@csi.cuy.du Tl: 718 98 81 4N101b Dartmt of Egirig Scic ad Physics Biasig uiolar smicoductor

More information

Chp6. pn Junction Diode: I-V Characteristics I

Chp6. pn Junction Diode: I-V Characteristics I 147 C6. uctio Diod: I-V Caractristics I 6.1. THE IDEAL DIODE EQUATION 6.1.1. Qualitativ Drivatio 148 Figur rfrc: Smicoductor Dvic Fudamtals Robrt F. Pirrt, Addiso-Wsly Publicig Comay 149 Figur 6.1 juctio

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

Narayana IIT Academy

Narayana IIT Academy INDIA Sc: LT-IIT-SPARK Dat: 9--8 6_P Max.Mars: 86 KEY SHEET PHYSIS A 5 D 6 7 A,B 8 B,D 9 A,B A,,D A,B, A,B B, A,B 5 A 6 D 7 8 A HEMISTRY 9 A B D B B 5 A,B,,D 6 A,,D 7 B,,D 8 A,B,,D 9 A,B, A,B, A,B,,D A,B,

More information

EE 560 MOS TRANSISTOR THEORY

EE 560 MOS TRANSISTOR THEORY 1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

University of Toronto. Final Exam

University of Toronto. Final Exam University of Toronto Final Exam Date - Dec 16, 013 Duration:.5 hrs ECE331 Electronic Circuits Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last

More information

(Reference: sections in Silberberg 5 th ed.)

(Reference: sections in Silberberg 5 th ed.) ALE. Atomic Structur Nam HEM K. Marr Tam No. Sctio What is a atom? What is th structur of a atom? Th Modl th structur of a atom (Rfrc: sctios.4 -. i Silbrbrg 5 th d.) Th subatomic articls that chmists

More information

FIELD-EFFECT TRANSISTORS

FIELD-EFFECT TRANSISTORS FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

More information

ESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15

ESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15 ESE 570 MOS TRANSISTOR THEORY Part 1 TwoTerminal MOS Structure 2 GATE Si Oxide interface n n Mass Action Law VB 2 Chemical Periodic Table Donors American Chemical Society (ACS) Acceptors Metalloids 3 Ideal

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model ELEC 3908, Physical Electronics, Lecture 23 The MOSFET Square Law Model Lecture Outline As with the diode and bipolar, have looked at basic structure of the MOSFET and now turn to derivation of a current

More information

Content. MIS Capacitor. Accumulation Depletion Inversion MOS CAPACITOR. A Cantoni Digital Switching

Content. MIS Capacitor. Accumulation Depletion Inversion MOS CAPACITOR. A Cantoni Digital Switching Content MIS Capacitor Accumulation Depletion Inversion MOS CAPACITOR 1 MIS Capacitor Metal Oxide C ox p-si C s Components of a capacitance model for the MIS structure 2 MIS Capacitor- Accumulation ρ( x)

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

Extensive reading materials on reserve, including

Extensive reading materials on reserve, including Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/30/2007 MOSFETs Lecture 4 Reading: Chapter 17, 19 Announcements The next HW set is due on Thursday. Midterm 2 is next week!!!! Threshold and Subthreshold

More information

Microelectronics Part 1: Main CMOS circuits design rules

Microelectronics Part 1: Main CMOS circuits design rules GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

More information

Chapter 2 Infinite Series Page 1 of 11. Chapter 2 : Infinite Series

Chapter 2 Infinite Series Page 1 of 11. Chapter 2 : Infinite Series Chatr Ifiit Sris Pag of Sctio F Itgral Tst Chatr : Ifiit Sris By th d of this sctio you will b abl to valuat imror itgrals tst a sris for covrgc by alyig th itgral tst aly th itgral tst to rov th -sris

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

MONTGOMERY COLLEGE Department of Mathematics Rockville Campus. 6x dx a. b. cos 2x dx ( ) 7. arctan x dx e. cos 2x dx. 2 cos3x dx

MONTGOMERY COLLEGE Department of Mathematics Rockville Campus. 6x dx a. b. cos 2x dx ( ) 7. arctan x dx e. cos 2x dx. 2 cos3x dx MONTGOMERY COLLEGE Dpartmt of Mathmatics Rockvill Campus MATH 8 - REVIEW PROBLEMS. Stat whthr ach of th followig ca b itgratd by partial fractios (PF), itgratio by parts (PI), u-substitutio (U), or o of

More information

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3

ECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3 ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o

More information

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Scaling Issues in Planar FET: Dual Gate FET and FinFETs Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar

More information

1985 AP Calculus BC: Section I

1985 AP Calculus BC: Section I 985 AP Calculus BC: Sctio I 9 Miuts No Calculator Nots: () I this amiatio, l dots th atural logarithm of (that is, logarithm to th bas ). () Ulss othrwis spcifid, th domai of a fuctio f is assumd to b

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon

More information

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION

ECE-343 Test 2: Mar 21, :00-8:00, Closed Book. Name : SOLUTION ECE-343 Test 2: Mar 21, 2012 6:00-8:00, Closed Book Name : SOLUTION 1. (25 pts) (a) Draw a circuit diagram for a differential amplifier designed under the following constraints: Use only BJTs. (You may

More information

Exam 1. It is important that you clearly show your work and mark the final answer clearly, closed book, closed notes, no calculator.

Exam 1. It is important that you clearly show your work and mark the final answer clearly, closed book, closed notes, no calculator. Exam N a m : _ S O L U T I O N P U I D : I n s t r u c t i o n s : It is important that you clarly show your work and mark th final answr clarly, closd book, closd nots, no calculator. T i m : h o u r

More information

CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS

CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS 5.1 The MOS capacitor 5.2 The enhancement-type N-MOS transistor 5.3 I-V characteristics of enhancement mode MOSFETS 5.4 The PMOS transistor and CMOS technology 5.5

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 10, Number 2, 2007, 189 197 MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations S. EFTIMIE 1, ALEX. RUSU

More information

Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5

Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Basic Physics of Semiconductors

Basic Physics of Semiconductors Chater 2 Basic Physics of Semicoductors 2.1 Semicoductor materials ad their roerties 2.2 PN-juctio diodes 2.3 Reverse Breakdow 1 Semicoductor Physics Semicoductor devices serve as heart of microelectroics.

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

ECE 305 Fall Final Exam (Exam 5) Wednesday, December 13, 2017

ECE 305 Fall Final Exam (Exam 5) Wednesday, December 13, 2017 NAME: PUID: ECE 305 Fall 017 Final Exam (Exam 5) Wednesday, December 13, 017 This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the ECE policy,

More information

Microelectronics Main CMOS design rules & basic circuits

Microelectronics Main CMOS design rules & basic circuits GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September

More information

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model

More information

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania 1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF ALIFORNIA, BERELEY ollege of Egieerig Deartmet of Electrical Egieerig ad omuter Scieces Ja M. Rabaey Homework #5 EES 4 SP0) [PROBLEM Elmore Delay 30ts) Due Friday, March 5, 5m, box i 40 ory

More information

ECE594I Notes set 6: Thermal Noise

ECE594I Notes set 6: Thermal Noise C594I ots, M. odwll, copyrightd C594I Nots st 6: Thrmal Nois Mark odwll Uivrsity of Califoria, ata Barbara rodwll@c.ucsb.du 805-893-344, 805-893-36 fax frcs ad Citatios: C594I ots, M. odwll, copyrightd

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions

Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions Investigation of the Thermal Noise of MOS Transistors under Analog and RF Operating Conditions Ralf Brederlow 1, Georg Wenig 2, and Roland Thewes 1 1 Infineon Technologies, Corporate Research, 2 Technical

More information

Basic Physics of Semiconductors

Basic Physics of Semiconductors Chater 2 Basic Physics of Semicoductors 2.1 Semicoductor materials ad their roerties 2.2 PN-juctio diodes 2.3 Reverse Breakdow 1 Semicoductor Physics Semicoductor devices serve as heart of microelectroics.

More information

GATE SOLVED PAPER - EC

GATE SOLVED PAPER - EC 03 ONE MARK Q. In a forward biased pn junction diode, the sequence of events that best describes the mechanism of current flow is (A) injection, and subsequent diffusion and recombination of minority carriers

More information

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution

ECE-342 Test 3: Nov 30, :00-8:00, Closed Book. Name : Solution ECE-342 Test 3: Nov 30, 2010 6:00-8:00, Closed Book Name : Solution All solutions must provide units as appropriate. Unless otherwise stated, assume T = 300 K. 1. (25 pts) Consider the amplifier shown

More information

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150

More information

Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

More information

Characteristics of Active Devices

Characteristics of Active Devices 007/Oct/17 1 haracteristics of Active Devices Review of MOSFET Physics MOS ircuit Applications Review of JT Physics MOS Noise JT Noise MS/RF Technology Roadmap MS MOS 1., 1.0, 0.8µm 0.60, 0.50µm 0.45,

More information

ECE 546 Lecture 11 MOS Amplifiers

ECE 546 Lecture 11 MOS Amplifiers ECE 546 Lecture MOS Amplifiers Spring 208 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine Amplifiers Definitions Used to increase

More information

ECE 340 Lecture 38 : MOS Capacitor I Class Outline:

ECE 340 Lecture 38 : MOS Capacitor I Class Outline: ECE 34 Lctur 38 : MOS Capacitor I Class Outli: Idal MOS Capacitor higs you should ow wh you lav Ky Qustios What ar th diffrt ias rgios i MOS capacitors? What do th lctric fild ad lctrostatic pottial loo

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

Problem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w

Problem 9.20 Threshold bias for an n-channel MOSFET: In the text we used a criterion that the inversion of the MOSFET channel occurs when V s = ;2 F w Prof. Jasprit Singh Fall 2001 EECS 320 Homework 11 The nals for this course are set for Friday December 14, 6:30 8:30 pm and Friday Dec. 21, 10:30 am 12:30 pm. Please choose one of these times and inform

More information

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Overview of Silicon p-n Junctions

Overview of Silicon p-n Junctions Overview of Silico - Juctios r. avid W. Graham West irgiia Uiversity Lae eartmet of omuter Sciece ad Electrical Egieerig 9 avid W. Graham 1 - Juctios (iodes) - Juctios (iodes) Fudametal semicoductor device

More information

Chapter Five. More Dimensions. is simply the set of all ordered n-tuples of real numbers x = ( x 1

Chapter Five. More Dimensions. is simply the set of all ordered n-tuples of real numbers x = ( x 1 Chatr Fiv Mor Dimsios 51 Th Sac R W ar ow rard to mov o to sacs of dimsio gratr tha thr Ths sacs ar a straightforward gralizatio of our Euclida sac of thr dimsios Lt b a ositiv itgr Th -dimsioal Euclida

More information

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. Quantitative MOSFET Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current. V DS _ n source polysilicon gate y = y * 0 x metal interconnect to

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

VLSI Design The MOS Transistor

VLSI Design The MOS Transistor VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at

More information

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012

1/13/12 V DS. I d V GS. C ox ( = f (V GS ,V DS ,V SB = I D. + i d + I ΔV + I ΔV BS V BS. 19 January 2012 /3/ 9 January 0 Study the linear model of MOS transistor around an operating point." MOS in saturation: V GS >V th and V S >V GS -V th " VGS vi - I d = I i d VS I d = µ n ( L V V γ Φ V Φ GS th0 F SB F

More information

Diode in electronic circuits. (+) (-) i D

Diode in electronic circuits. (+) (-) i D iode i electroic circuits Symbolic reresetatio of a iode i circuits ode Cathode () (-) i ideal diode coducts the curret oly i oe directio rrow shows directio of the curret i circuit Positive olarity of

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

Chapter 5 MOSFET Theory for Submicron Technology

Chapter 5 MOSFET Theory for Submicron Technology Chapter 5 MOSFET Theory for Submicron Technology Short channel effects Other small geometry effects Parasitic components Velocity saturation/overshoot Hot carrier effects ** Majority of these notes are

More information

Quiz #3 Practice Problem Set

Quiz #3 Practice Problem Set Name: Studet Number: ELEC 3908 Physical Electroics Quiz #3 Practice Problem Set? Miutes March 11, 2016 - No aids excet a o-rogrammable calculator - ll questios must be aswered - ll questios have equal

More information

EECS 105: FALL 06 FINAL

EECS 105: FALL 06 FINAL University of California College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey TuTh 2-3:30 Wednesday December 13, 12:30-3:30pm EECS 105: FALL 06 FINAL NAME Last

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

MOSFET Capacitance Model

MOSFET Capacitance Model MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

More information

(S&S ) PMOS: holes flow from Source to Drain. from Source to Drain. W.-Y. Choi. Electronic Circuits 2 (09/1)

(S&S ) PMOS: holes flow from Source to Drain. from Source to Drain. W.-Y. Choi. Electronic Circuits 2 (09/1) (S&S 4.1 4.3) NMOS: electrons flow from Source to Drain PMOS: holes flow from Source to Drain In cut-off ( v < V ), i = 0 GS t D NMOS I-V Characteristics In triode, ( v > V but v v v ) GS t DS GS T W 1

More information

Time : 1 hr. Test Paper 08 Date 04/01/15 Batch - R Marks : 120

Time : 1 hr. Test Paper 08 Date 04/01/15 Batch - R Marks : 120 Tim : hr. Tst Papr 8 D 4//5 Bch - R Marks : SINGLE CORRECT CHOICE TYPE [4, ]. If th compl umbr z sisfis th coditio z 3, th th last valu of z is qual to : z (A) 5/3 (B) 8/3 (C) /3 (D) o of ths 5 4. Th itgral,

More information

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Homework 4 Due on March 01, 2018 at 7:00 PM Suggested Readings: a) Lecture notes Important Note:

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Appendix 1: List of symbols

Appendix 1: List of symbols Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

N Channel MOSFET level 3

N Channel MOSFET level 3 N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate

More information

ECE602 Exam 1 April 5, You must show ALL of your work for full credit.

ECE602 Exam 1 April 5, You must show ALL of your work for full credit. ECE62 Exam April 5, 27 Nam: Solution Scor: / This xam is closd-book. You must show ALL of your work for full crdit. Plas rad th qustions carfully. Plas chck your answrs carfully. Calculators may NOT b

More information

Ordinary Differential Equations

Ordinary Differential Equations Basi Nomlatur MAE 0 all 005 Egirig Aalsis Ltur Nots o: Ordiar Diffrtial Equatios Author: Profssor Albrt Y. Tog Tpist: Sakurako Takahashi Cosidr a gral O. D. E. with t as th idpdt variabl, ad th dpdt variabl.

More information

The pn junction: 2 Current vs Voltage (IV) characteristics

The pn junction: 2 Current vs Voltage (IV) characteristics Th pn junction: Currnt vs Voltag (V) charactristics Considr a pn junction in quilibrium with no applid xtrnal voltag: o th V E F E F V p-typ Dpltion rgion n-typ Elctron movmnt across th junction: 1. n

More information

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

More information

LECTURE 13 Filling the bands. Occupancy of Available Energy Levels

LECTURE 13 Filling the bands. Occupancy of Available Energy Levels LUR 3 illig th bads Occupacy o Availabl rgy Lvls W hav dtrmid ad a dsity o stats. W also d a way o dtrmiig i a stat is illd or ot at a giv tmpratur. h distributio o th rgis o a larg umbr o particls ad

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 10 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits Exam No. 2 Thursday, November 5, 2009 7:30 to

More information

Unified Compact Model for Generic Double-Gate

Unified Compact Model for Generic Double-Gate WCM-MSM007 Workshop on Compact Modeling 10th International Conference on Modeling and Simulation of Microsystems Santa Clara, California, USA Unified Compact Model for Generic Double-Gate MOSFETs Xing

More information

ESE 570 MOS TRANSISTOR THEORY Part 2

ESE 570 MOS TRANSISTOR THEORY Part 2 ESE 570 MOS TRANSISTOR THEORY Part 2 GCA (gradual channel approximation) MOS Transistor Model Strong Inversion Operation CMOS = NMOS + PMOS 2 TwoTerminal MOS Capacitor > nmos Transistor VGS

More information