Transistor's self-und mutual heating and its impact on circuit performance

Transcription

1 Transistor's self-und mutual heating and its impact on circuit performance M. Weiß, S. Fregonese, C. Maneux, T. Zimmer 26 th BipAk, 15 November 2013, Frankfurt Oder, Germany

2 Outline 1. Motivation. Research overview 2. Device-level electrothermal investigations 3. Circuit-level electrothermal investigations 4. Conclusion. Future work. 2

3 Research Overview Multi-transistor array Higher device temperature! Thermal coupling effects! 3D temperature distribution in a 3 finger multi-transistor array (Figure taken from Electrothermal HBT modeling, G. Wedel et al., HiCuM Workshop 2012) ΔT x 3

4 Outline 1. Motivation. Research overview 2. Device-level electrothermal investigations 3. Circuit-level electrothermal investigations 4. Conclusion. Future work. 4

5 Thermal Coupling Network P power dissipations (Current) R th thermal resistances ΔT temperature increase (Voltage) Single-pole thermal network 5

6 Thermal Coupling Network P 1, P 2 power dissipations R th_11, R th_22 selfheating thermal resistances c 12, c 21 mutual thermal coupling factors ΔT 1, ΔT 2 temperature increase in the transistors [2] D. J. Walkey et al., Equivalent circuit modeling of static substrate thermal coupling using VCVS representation, IEEE J. Solid-State Circuits,

7 Test Structure Inter Device Coupling Test structure Intra Device Coupling Micrograph E 2 E 4 E 1 C E 3 E 5 7

8 Temperature Measurement T4 is heating Wafer T=300K Distance D between deep trench T 1 T 2 T 3 T 4 T T in 300K, T4 heating T in 300K, T4 heating T in 300K, T4 heating P diss [mw] Intra device coupling in multi-finger transistor T in 300K, T4 heating T in 300K, T4 heating T in 300K, T4 heating D=1.5µm D=5µm D=3µm P diss [mw] Inter device coupling in multi-transistor array 8

9 Coup. Factor [%] Coup. Factor [%] Coupling Factors Wafer T=300K T 1 T 2 T 3 T 4 T C 12 C 21 C 34 C 32 C 23 C 13 C 24 C 31 C 35 C 14 C 25 C P diss [mw] P diss [mw] Intra device coupling in multi-finger transistor 4 2 D=1.5µm Inter device coupling in multitransistor array with distance D=1.5µm C 12 C 21 C 34 C 32 C 23 C 13 C 24 C 31 C 35 C 14 C 25 C 15 9

10 T Lattice [K] Coup. Factor [%] 3D Thermal Simulation solid lines = CF from TCAD symbols = CF from meas. C 12 C 21 C C 23 C 13 C C 31 C 14 C 25 C 15 x C XY P diss [mw] Intra device coupling in multi-finger transistor dtx / dp R Y dt / dp R th _ XY Y Y th _ YY X Sensing Y Heating E1 E2 E3 x E4 E5 Applied power per finger 30mW [7] M. Weiß et al., Characterization of intra device mutual thermal coupling in multi finger SiGe: C HBTs, EDSSC Conference,

11 I C [ma] I C [ma] Model Verification Output characteristics for 5 devices operating parallel Wafer T=300K T 1 T 2 T 3 T 4 T V BE =0.80V V BE =0.85V V BE =0.90V V BE =0.95V V BE =0.80V V BE =0.85V V BE =0.90V V BE =0.95V V CE [V] Intra device coupling in multi-finger transistor V CE [V] Inter device coupling in multi-transistor array, D=1.5µm [8] M. Weiß et al., Mutual thermal coupling in SiGe: C HBTs, SBMicro Conference,

12 Outline 1. Motivation. Research overview 2. Device-level electrothermal investigations 3. Circuit-level electrothermal investigations 4. Conclusion. Future work. 12

13 Specifications 53 CML Inverter Voltage Swing: 200mV Out p In p R L V CC Ring Oscillator: Optimization Simplified CML Inverter R L T 3 T 4 Out n In n Variables Transistor Configuration Emitter Length L E Current Source I 0 Resistance R L gate,min [ps] CBE CBEB CBEBC CBEBC2 CBEBC3 CBEBC4 Propagation Delay 1 t p 2 53 f osc I l E [ m] 13

14 Ring Oscillator: Results Temperature Diode VEE OUT VEE Output Buffer Vk VBUF Va 53 Inverter VPOL VEE VCC VCC VEE Current Mirror Fabricated RO including 53 CML inverter stages and a temperature sensor Wafer map of the gate delay, HBT 0.18x5µm 2, I gate =12.5mA [9] M. Weiß et al., Optimized Ring Oscillator With 1.65-ps, Electron Device Letters,

15 T circ [ C] Ring Oscillator: Circuit temperature L Transistor (T j ) W Wafer T amb =300K Circuit (T circ ) ΔT 2 ΔT Circ Temp Model Circ Temp Meas gate [ps] Meas Sim T27 Sim TModel Sim TMeas I gate [ma] Measured and simulated circuit temperature vs. I gate I gate [ma] τ gate vs. I gate : Measurements (symbols) and HICUM simulation (solid lines) [10] M. Weiß et al., Characterization of mutual heating inside a SiGe RO, BCTM Conference,

16 T 3 [K] gate [ps] T 5 [K] Ring Oscillator: Coupled Simulation VCC V CC 8 R C R C OUTp INn Q3 Q1 Q4 Q2 OUTn INp 7 Vbias up R F I gate 0 Q5 Q6 R F Vbias down 6 C F R E R E C F 60 standard sim. sim. with th. coupling t [ns] 1.6 Meas Sim T27 Sim TMeas standard sim. sim. with th. coupling t [ns] I gate [ma] 16

17 Power amplifier Load Pull test bench Five-finger transistor (INTRA) Five-transistor array (INTER) A five-finger transistor and five transistor array are operated as a PA Each emitter has a drawn emitter area A E =5x0.18µm 2 Matching with load-pull tuners 17

18 P out [dbm], Gain [db], PAE [%] Power amplifier: Single transistor Compact model verification: Comparison simulation vs. power measurements for 1 transistor j0.7 j j0.3 j0.5-3db -2dB -1dB j2.0 j j0.1 j10 j Sim 1xCBEBC Pout Gain PAE P in [dbm] -j0.1 -j0.3 -j0.5 -j0.7 -j0.9 -j2.0 -j4.0 -j50 -j10 Tran Meas: G max Z load = i Tran Sim: G max Z load = i P out, Gain, PAE vs. P in in matched condition Load pull contours for constant power gain 18

19 P out [dbm], Gain [db] P out [dbm], Gain [db] Power amplifier: Transistor array Characteristics of both devices are close at low power dissipation At higher bias (V BE =0.9V, V CE =1.5V) significant performance degradation of the multi-finger transistor due to thermal coupling Good agreement with circuit simulations in both cases PA INTER meas PA INTRA meas PA INTER sim PA INTRA sim P in [dbm] PA INTER meas PA INTRA meas PA INTER sim PA INTRA sim P in [dbm] V BE =0.9V, V CE =1V V BE =0.9V, V CE =1.5V 19

20 Outline 1. Motivation. Research overview 2. Device-level electrothermal investigations 3. Circuit-level electrothermal investigations 4. Conclusion. Future work. 20

21 Conclusion (1/2) Novel test structures to characterize thermal coupling of state of the art trench isolated SiGe HBT technology Thermal coupling factors were extracted from multi-finger transistor (INTRA) and multi-transistor array (INTER) Standard thermal network has been replaced by distributed networks in order to model accurately thermal impedance and thermal coupling between neighboring devices The models were implemented as netlist in Agilent ADS (easy to use for circuit designers) 21

22 Conclusion (2/2) Electrical performance of the multi-finger transistor is degraded due to the significant thermal coupling effect between the emitter stripes Coupled simulation accurately predict thermal effects in multi-finger SiGe HBTs, often used for high speed applications due to lower input resistance and capacitance Model has been already successfully applied for two circuits (PA and of a RO with 218 transistors) Device performance is often limited by thermal effects rather than the electronic limitations circuit designers need accurate models to exploit full potential of a technology 22

23 Future work Thermal stability can be improved, access to the thermal nodes of each finger allows to estimate ballasting resistors The thermal stability in multiple-finger transistors can be increased by adjustment of emitter to emitter distances to make the spatial temperature distribution across the device approximately uniform Thermal coupling capacitances should be considered in a next step Parameter extraction based on isothermal pulsed DC/RF measurements 23

24 Acknowledgement This work is part of the: DOTSEVEN project supported by the European Commission through the Seventh Framework Programme for Research and Technological Development. Acknowledgements to Catrene RF2THz project We want to thank ST microelectronics for helpful discussions and PDK support