Regional Approach Methods for SiGe HBT compact modeling

Size: px
Start display at page:

Download "Regional Approach Methods for SiGe HBT compact modeling"

Transcription

1 Regional Approach Methods for SiGe HBT compact modeling M. Schroter 1),2) and H. Tran 2) 1) ECE Dept., University of California San Diego, La Jolla, CA, USA 2) Chair for Electron Devices and Integr. Circuits, Univ. of Technol. Dresden, Germany 6th HICUM Workshop, Heilbronn, June 12/13, 26 MS 1

2 OUTLINE Introduction Investigated Device Structures Overview on Regional Approach Methods Results and Discussion Conclusions MS 2

3 Introduction Introduction Bipolar transistor main application areas high-frequency/high-speed operation Circuit design constraints cost reduction (mask, re-spins..., yield prediction) some applications are close to the technology limit careful circuit optimization Process development and optimization evaluation of charge and delay components within device structure accurate physics-based modeling of charge storage effects MS 3

4 Introduction Existing methods for analyzing charge storage analytical solutions require strong simplifications of underlying semiconductor equations spatial partitioning into neutral region (NR) and space-charge region (SCR) by definition of abrupt boundaries (Regional Approach = RA) validity of results is limited to particular spatial and bias region device simulation yields detailed information on carrier and charge distributions no limitation of results w.r.t. certain spatial or bias regions however: no abrupt boundaries between spatial regions either desirable: charge storage components from device simulation as reference for analytical modeling this work: evaluation of possible RA options for device simulation MS 4

5 Investigated Device Structures Investigated Device Structures 1D device simulation: unit emitter area A E = 1μm 2 conventional emitter doping (CED) transistor: high-speed BJT, HBT version ad1lv_nge (dashed) ad2lv_ge (solid) with Ge(dotted) 1e L x 1e+2 1e+19 N [cm -3 ] 1e+18 1e+17 Ge(B) mole fraction 1e e x [μm] MS 5

6 Investigated Device Structures Device Structures low-emitter concentration (LEC) transistor: high-speed HBT version N [cm -3 ] mole fraction x [μm] L x MS 6

7 Investigated Device Structures High-frequency performance: transit frequency f T [GHz] symbols: a.c. lines: q.s V C E =.8V LEC CED HBT 4 2 BJT I C [ma] identical results for quasi-static and frequency dependent small-signal calculation partitioning of transit time based on carrier distribution MS 7

8 Overview on Regional Approach Methods Overview on Regional Approach Methods d.c. method(s) determination of NR-SCR boundary is based on static carrier distribution classical criterion for detecting point in SCR: majority carrier density < r * doping conc., with r << 1 works only for sufficiently low-injection does not work in center region of SCR (N but carrier densities remain finite) log(n, p, n) N n p N normalized boundary condition: x r = x N p n r p + n with r <(<) 1 N+p-n p+n NR x j SCR NR x works also for high injection search needs to start from neutral region designated as DCRA and used for comparisons problem: missing link to small-signal operation r x j x MS 8

9 Overview on Regional Approach Methods Small-signal based regional approaches link to small-signal measurements via relation between transit frequency and stored hole charge: 1 dq p = τ 2πf ec = T di C V C'E' differential hole charge from carrier variation: L x dq p = qa E p dx region boundaries detected from quasi-static small-signal carrier distribution next: comparison of 3 methods MS 9

10 Overview on Regional Approach Methods Regional Approach Methods: van den Biesen [6] popular for evaluating device simulation results replaces metallurgical boundaries by electrical boundaries: x m = xdp ( = dn) storage time partitioning: dq p di C V C'E' * = τ e τ ec * * + τ eb + τ b + τ bc + τ c minority carrier storage times, e.g.: τ b * = qa E x mc x me n I C V C'E' dx depletion region "charging times", e.g.: [cm -3 ] dρ 5 x me ad1lv_nge 1E-17*drho x mc V C E =.8V x me ( n p) τ eb = qa E I C V C'E' dx -5-1 no separation of NR and SCR -15 not suitable for compact modeling! x [μm] MS 1

11 Overview on Regional Approach Methods Regional Approach Methods: FRA (1/3) region boundaries from peaks of ( p- n) Note: BC SCR boundaries cannot be detected from CE short distribution! need BE short instead collector related regions are trickier high-current effects => injection zone Ge drop causes barrier => additional peaks [cm -3 ] ρ V C E =.8V dv C E = SCR edges of BC junction: ρ ( x c, x C, c ) = x V B'C' V B'E' = ( max, min) region widths neutral base: w B = min{ x c, x jc } x e BC SCR: w BC = x Cc x c injection width: w i = max{ x c x jc, } ρ [cm -3 ] w E x e x c x C,c dv B E = x [μm] MS 11

12 Overview on Regional Approach Methods Regional Approach Methods: FRA (2/3) separation into BE and BC voltage change: dq p Q p = = V B'E' V C'E' dv B'E' Q p V B'E' V B'C' dv B'E' + Q p V B'C' V B'E' dv B'C' dv B E = dv B C minorities: m = p, p < n minority charge dq m = qa E mdx n, n p w hole charge partitioning: dq p = dq j + dq m depletion charge dq j = dq p dq m = qa E ( n p) dx w( p < n) consistent with q.s. definition of f T MS 12

13 Overview on Regional Approach Methods minority carrier storage time components from accumulated storage time: m τ m ( x) = qa E I C space-charge modulation in BC SCR: ( ρ) C ce = qa E = cross-coupled capacitance L x x mc x Full regional approach (3/3) V B'E' V C'E' V B'C' dξ dx 12 1 τ m (x) [ps] ad1lv_nge vcep8 w i w BE w B w BC profile I C high I C low I peak f T total value: τ f = τ m ( L x ) C ce g mi x je x jc x [μm] depletion capacitances: x me ( ρ) C jei = qa E V B'E' V B'C' dx ( ρ) C jci = qa E L x x mc V B'C' V B'E' dx MS 13

14 Overview on Regional Approach Methods Regional Approach Methods: DTRA [11] proposed for evaluation of device simulation results SCR boundary defined as 5% difference between accumulated carrier storage times x n p τ n ( x) = qa E dξ, τ I p ( x) = qa E C I C V C'E' x V C'E' dξ storage times include depletion charge contributions (C j /g m ) does not allow reliable detection of BC SCR end boundary detection difficult at high injection correction of τ E (2/3)τ E based on non-quasi-static operation ignored here τ(x) [ps] ad1lv_nge vcep8 dp(dashed) τ p I C low τ n I C high I peak f T x [μm] V C E =.8V MS 14

15 Results and Discussion Results and Discussion BJT storage time components (V C E =.8V) ad1lv_nge TE, TBE vce.8 τ [ps] τ B τ BC x τ C τ [ps] τ E o τ BE FRA DTRA DCRA 3 3 τ E 2 1 τ B τ BC τ C (FRA) I C [ma] τ C neutral base: τ B differs significantly; discontinuous for DTRA due to Kirk effect BC SCR: τ BC similar for FRA & DTRA, but too small for DCRA (τ m only) BE SCR: τ BE differs significantly, discontinuous for DCRA (no x e detection) neutral collector: τ C not detected by DCRA and DTRA 2 1 τ BE τ BE τ E I C [ma] MS 15

16 Results and Discussion CED HBT storage time components (V C E =.8V) τ B o τ BE FRA DTRA DCRA 1.5 τ E τ BC τ [ps] 1.5 τ [ps] 1 x τ C 1.5 τ BE τ B τ B.5 τ BC τ C I C [ma] I C [ma] τ E neutral base: τ B more consistent; DTRA does not detect carrier jam properly BC SCR: τ BC similar for FRA & DTRA; difference at low I C due to C jci /g m in DTRA BE SCR: τ BE more consistent; DTRA and FRA similar neutral collector (τ C ): small injection zone is detected by FRA, not by DTRA, DCRA MS 16

17 Results and Discussion LEC HBT storage time components (V C E =.8V) τ [ps] + τ B o τ BE FRA DTRA DCRA τ [ps] τ E τ BC τ B 1 τ BC.5 τ BE I C [ma] I C [ma] τ E neutral base: τ B dominates, detected fairly consistently for all methods BC SCR: τ BC identical for FRA & DTRA, increase due to barrier BE SCR: τ BE similar for DCRA and FRA; DTRA includes C jei /g m (low I C ) neutral collector (τ C ) and emitter (τ E ): negligible due to barriers MS 17

18 Determination of compact model transit time Determination of compact model transit time Reciprocal f T and related storage times vs 1/I C for BJT standard transit time determination method τ f = τ f ( V BC ) + Δτ f ( I T, V ) BC slope is usually assumed to be caused by depletion caps improved method includes curvature (from V BE dependence of C je ) τ [ps] τ f τ mσ 1 2πf T ΣC j g m τ BE in reality: curvature and portion of offset caused by neutral charge in BE SCR /I C [1/mA] extracted C je always includes portion of neutral BE charge MS 18

19 Determination of compact model transit time Full regional approach: capacitances C [ff/μm 2 ] 3 ad1lv_nge CJE(diam), CCE(o), CME(+, axis2), CJC(sq), CMC(x) f T C ce BJT V C E =.8V C me C me [ff/μm 2 ] C jei 2 C jci C mc J C [ma/μm 2 ] BC depletion capacitances cross-coupled BE capacitance L x ρ C jci = qa E x mc V B'C' V B'E' dx ρ C ce = qa E L x x mc V B'E' V B'C' dx MS 19

20 Determination of compact model transit time Full regional approach: HBT capacitances C [ff/μm 2 ] V C E =.8V CED LECHBT f T C jei C me 1 8 C me [ff/μm 2 ] 6 4 C [ff/μm 2 ] V C E =.8V LEC LECHBT f T C jei C me C me [ff/μm 2 ] C jci C mc C ce 5 C jci 2 C ce J C [ma/μm 2 ] J C [ma/μm 2 ] C mc C jei dominates before, C me beyond peak f T stronger C me increase at high current densities due to barrier effect MS 2

21 Conclusions Conclusions several approaches for regional partitioning in Si-based HBTs have been investigated regarding their suitability for device simulation and compact modeling use d.c. carrier distribution based methods are unreliable small-signal quasi-static carrier distribution based methods: van den Biesen s scheme is not useful for compact modeling differential transit time approach (DTRA) is unreliable for BJTs, does not detect boundaries in the collector extended space-charge peak based regional approach (FRA) gives reliable physically reasonable results that can be linked directly to compact model development BE depletion charge always contains a portion of neutral charge MS 21

22 Conclusions Acknowledgments financial support from German Ministry of Research and Technology (DFG project SCHR695/1-2) Atmel Germany, Heilbronn, Germany ST Microelectronics, Crolles, France MS 22

23 Additional slides Additional slides p n+ sgn ( N) G improved (most recently): x SCR = x: r with r = G works for any discrete point (no search direction required) and all regions of operation r (,1) can be easily adjusted to depletion capacitance value MS 23

24 Full regional approach: results Full regional approach: results electron velocity, internal collector resistance internal collector resistance: 1 r Ci = A E carrier velocity: v jc = L x 1 x bcc dx qμ nci n w BC ( τ BC r Ci C jci ) τ BC includes collector charge modul. value close to physical (N C (x)!) v jc [1 7 cm/s], V B E [V] V C E =.8V ad1lv_nge BJT v jc V B E r Ci τ mσ J C [ma/μm 2 ] r Ci [Ωμm 2 ], τ mσ [ps] increasing J C : w BC increases (V c > V lim ) r Ci decreases E jc decreases v jc decreases MS 24

25 Full regional approach: results Full regional approach: results electron velocity, internal collector resistance v jc [1 7 cm/s], V B E [V] CED ad2lv HBT r Ci v jc V B E.1 τ mσ J C [ma/μm 2 ] V C E =.8V r Ci [Ωμm 2 ], τ mσ [ps] v jc [1 7 cm/s], V B E [V] LEC HBT v jc V B E r Ci τ mσ J C [ma/μm 2 ] V C E =.8V r Ci [Ωμm 2 ], τ mσ [ps] increasing J C : w BC decreases (V c < V lim ) r Ci increases E jc decreases v jc decreases MS 25

26 Full regional approach: results Full regional approach: bias dependent widths BJT MS 26

27 Full regional approach: results Full regional approach: bias dependent widths CED transistor MS 27

28 Full regional approach: results Full regional approach: bias dependent widths LEC transistor MS 28

Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation

Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation Charge-storage related parameter calculation for Si and SiGe bipolar transistors from device simulation M. Schroter ),) and H. Tran ) ) ECE Dept., University of California San Diego, La Jolla, CA, USA

More information

Non-standard geometry scaling effects

Non-standard geometry scaling effects Non-standard geometry scaling effects S. Lehmann 1), M. Schröter 1),2), J. Krause 1), A. Pawlak 1) 1) Chair for Electron Devices and Integr. Circuits, Univ. of Technol. Dresden, Germany 2) ECE Dept., University

More information

Accurate transit time determination and. transfer current parameter extraction

Accurate transit time determination and. transfer current parameter extraction Accurate transit time determination and transfer current parameter extraction T. Rosenbaum, A. Pawlak, J. Krause, M. Schröter Chair for Electron Devices and Integrated Circuits (CEDIC) University of Technology

More information

About Modeling the Reverse Early Effect in HICUM Level 0

About Modeling the Reverse Early Effect in HICUM Level 0 About Modeling the Reverse Early Effect in HICUM Level 0 6 th European HICUM Workshop, June 12-13, 2006, Heilbronn Didier CELI, STMicroelectronics 1/21 D. Céli Purpose According to the bipolar models,

More information

Device Physics: The Bipolar Transistor

Device Physics: The Bipolar Transistor Monolithic Amplifier Circuits: Device Physics: The Bipolar Transistor Chapter 4 Jón Tómas Guðmundsson tumi@hi.is 2. Week Fall 2010 1 Introduction In analog design the transistors are not simply switches

More information

Working Group Bipolar (Tr..)

Working Group Bipolar (Tr..) Department of Electrical Engineering and Information Technology Institute of Circuits and Systems Chair for Electron Devices and Integrated Circuits Working Group Bipolar (Tr..) I T parameter extraction

More information

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

More information

ELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 19. BJT Base Resistance and Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 19 BJT Base Resistance and Small Signal Modelling Lecture Outline Lecture 17 derived static (dc) injection model to predict dc currents from terminal voltages This

More information

2 nd International HICUM user s meeting

2 nd International HICUM user s meeting 2 nd International HICUM user s meeting Monterey, September 22 D. Berger, D. Céli, T. Burdeau STMicroelectronics,, France esults HICUM status in ST Implementation of HICUM model equation in an in-house

More information

HICUM / L2. A geometry scalable physics-based compact bipolar. transistor model

HICUM / L2. A geometry scalable physics-based compact bipolar. transistor model HICUM HICUM / L2 A geometry scalable physics-based compact bipolar transistor model M. Schroter, A. Pawlak, A. Mukherjee Documentation of model version 2.32 August, 2013 M. Schroter 16/5/14 1 HICUM List

More information

Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003

Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 16-1 Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model April 8, 2003 Contents: 1. I-V characteristics (cont.) 2. Small-signal

More information

Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31

Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31 Modeling high-speed SiGe-HBTs with HICUM/L2 v2.31 A. Pawlak, M. Schroter, A. Mukherjee, J. Krause Chair for Electron Devices and Integrated Circuits (CEDIC) Technische Universität Dresden, Germany pawlak@iee.et.tu-dresden.de,

More information

Lecture 16 The pn Junction Diode (III)

Lecture 16 The pn Junction Diode (III) Lecture 16 The pn Junction iode (III) Outline I V Characteristics (Review) Small signal equivalent circuit model Carrier charge storage iffusion capacitance Reading Assignment: Howe and Sodini; Chapter

More information

A Novel Method for Transit Time Parameter Extraction. Taking into Account the Coupling Between DC and AC Characteristics

A Novel Method for Transit Time Parameter Extraction. Taking into Account the Coupling Between DC and AC Characteristics A Novel Method for Transit Time Parameter Extraction Taking into Account the Coupling Between DC and AC Characteristics Dominique BEGE and Didier CELI STMicroelectronics, 850, rue jean Monnet F-38926 Cedex

More information

Electronic Devices and Circuits Lecture 5 - p-n Junction Injection and Flow - Outline

Electronic Devices and Circuits Lecture 5 - p-n Junction Injection and Flow - Outline 6.012 - Electronic Devices and Circuits Lecture 5 - p-n Junction Injection and Flow - Outline Review Depletion approimation for an abrupt p-n junction Depletion charge storage and depletion capacitance

More information

Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 2007

Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 2007 6.72J/3.43J - Integrated Microelectronic Devices - Spring 27 Lecture 38-1 Lecture 38 - Bipolar Junction Transistor (cont.) May 9, 27 Contents: 1. Non-ideal effects in BJT in FAR Reading material: del Alamo,

More information

Bipolar junction transistor operation and modeling

Bipolar junction transistor operation and modeling 6.01 - Electronic Devices and Circuits Lecture 8 - Bipolar Junction Transistor Basics - Outline Announcements Handout - Lecture Outline and Summary; Old eam 1's on Stellar First Hour Eam - Oct. 8, 7:30-9:30

More information

Semiconductor Device Simulation

Semiconductor Device Simulation motivation and target applications compact model development under conditions relevant for circuit design development of test structures and measurement methods (fast) predicting device performance and

More information

Investigation of Ge content in the BC transition region with respect to transit frequency

Investigation of Ge content in the BC transition region with respect to transit frequency Investigation of Ge content in the BC transition region with respect to transit frequency P.M. Mans (1),(2), S. Jouan (1), A. Pakfar (1), S. Fregonese (2), F. Brossard (1), A. Perrotin (1), C. Maneux (2),

More information

Lecture 19 - p-n Junction (cont.) October 18, Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics

Lecture 19 - p-n Junction (cont.) October 18, Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode: parasitics, dynamics 6.720J/3.43J - Integrated Microelectronic Devices - Fall 2002 Lecture 19-1 Lecture 19 - p-n Junction (cont.) October 18, 2002 Contents: 1. Ideal p-n junction out of equilibrium (cont.) 2. pn junction diode:

More information

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed)

ECE-342 Test 2 Solutions, Nov 4, :00-8:00pm, Closed Book (one page of notes allowed) ECE-342 Test 2 Solutions, Nov 4, 2008 6:00-8:00pm, Closed Book (one page of notes allowed) Please use the following physical constants in your calculations: Boltzmann s Constant: Electron Charge: Free

More information

Introduction to Power Semiconductor Devices

Introduction to Power Semiconductor Devices ECE442 Power Semiconductor Devices and Integrated Circuits Introduction to Power Semiconductor Devices Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Semiconductor Devices Applications System Ratings

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 1 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.12 Electronic Devices and Circuits Exam No. 1 Wednesday, October 7, 29 7:3 to 9:3

More information

BJT - Mode of Operations

BJT - Mode of Operations JT - Mode of Operations JTs can be modeled by two back-to-back diodes. N+ P N- N+ JTs are operated in four modes. HO #6: LN 251 - JT M Models Page 1 1) Forward active / normal junction forward biased junction

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 5a Bipolar Transistor Dep. Region Neutral Base n(0) b B C n b0 P C0 P e0 P C xn 0 xp 0 x n(w) b W B Adib Abrishamifar EE Department IUST Contents Bipolar Transistor

More information

ELEC 3908, Physical Electronics, Lecture 17. Bipolar Transistor Injection Models

ELEC 3908, Physical Electronics, Lecture 17. Bipolar Transistor Injection Models LC 3908, Physical lectronics, Lecture 17 Bipolar Transistor njection Models Lecture Outline Last lecture looked at qualitative operation of the BJT, now want to develop a quantitative model to predict

More information

Status of HICUM/L2 Model

Status of HICUM/L2 Model Status of HICUM/L2 Model A. Pawlak 1), M. Schröter 1),2), A. Mukherjee 1) 1) CEDIC, University of Technology Dresden, Germany 2) Dept. of Electrical and Computer Engin., University of Calif. at San Diego,

More information

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating

ELEC 3908, Physical Electronics, Lecture 18. The Early Effect, Breakdown and Self-Heating ELEC 3908, Physical Electronics, Lecture 18 The Early Effect, Breakdown and Self-Heating Lecture Outline Previous 2 lectures analyzed fundamental static (dc) carrier transport in the bipolar transistor

More information

Spring Semester 2012 Final Exam

Spring Semester 2012 Final Exam Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters

More information

Lecture 10 - Carrier Flow (cont.) February 28, 2007

Lecture 10 - Carrier Flow (cont.) February 28, 2007 6.720J/3.43J Integrated Microelectronic Devices - Spring 2007 Lecture 10-1 Lecture 10 - Carrier Flow (cont.) February 28, 2007 Contents: 1. Minority-carrier type situations Reading assignment: del Alamo,

More information

Recitation 17: BJT-Basic Operation in FAR

Recitation 17: BJT-Basic Operation in FAR Recitation 17: BJT-Basic Operation in FAR BJT stands for Bipolar Junction Transistor 1. Can be thought of as two p-n junctions back to back, you can have pnp or npn. In analogy to MOSFET small current

More information

HICUM release status and development update L2 and L0

HICUM release status and development update L2 and L0 HICUM release status and development update L2 and L0 M. Schröter, A. Pawlak 17th HICUM Workshop Munich, Germany May 29th, 2017 Contents HICUM/L2 in a nutshell Release of HICUM/L2 version 2.4.0 Strong

More information

CLASS 3&4. BJT currents, parameters and circuit configurations

CLASS 3&4. BJT currents, parameters and circuit configurations CLASS 3&4 BJT currents, parameters and circuit configurations I E =I Ep +I En I C =I Cp +I Cn I B =I BB +I En -I Cn I BB =I Ep -I Cp I E = I B + I C I En = current produced by the electrons injected from

More information

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #1 Time

More information

EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions

EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 pn Junction p-type semiconductor in

More information

TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions

TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions TCAD setup for an advanced SiGe HBT technology applied to the HS, MV and HV transistor versions T. Rosenbaum 1,2,3, D. Céli 1, M. Schröter 2, C. Maneux 3 Bipolar ArbeitsKreis München, Germany, November

More information

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime

Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Lecture 17 The Bipolar Junction Transistor (I) Forward Active Regime Outline The Bipolar Junction Transistor (BJT): structure and basic operation I V characteristics in forward active regime Reading Assignment:

More information

Metal-oxide-semiconductor field effect transistors (2 lectures)

Metal-oxide-semiconductor field effect transistors (2 lectures) Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -

More information

Session 6: Solid State Physics. Diode

Session 6: Solid State Physics. Diode Session 6: Solid State Physics Diode 1 Outline A B C D E F G H I J 2 Definitions / Assumptions Homojunction: the junction is between two regions of the same material Heterojunction: the junction is between

More information

Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration

Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration Breakdown mechanisms in advanced SiGe HBTs: scaling and TCAD calibration T. Rosenbaum 1,2,3, D. Céli 1, M. Schröter 2, C. Maneux 3 Bipolar ArbeitsKreis Unterpremstätten, Austria, November 6, 2015 1 STMicroelectronics,

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 21: Bipolar Junction Transistor Administrative Midterm Th 6:30-8pm in Sibley Auditorium Covering everything

More information

ECE-305: Spring 2018 Final Exam Review

ECE-305: Spring 2018 Final Exam Review C-305: Spring 2018 Final xam Review Pierret, Semiconductor Device Fundamentals (SDF) Chapters 10 and 11 (pp. 371-385, 389-403) Professor Peter Bermel lectrical and Computer ngineering Purdue University,

More information

Lecture 15 - The pn Junction Diode (I) I-V Characteristics. November 1, 2005

Lecture 15 - The pn Junction Diode (I) I-V Characteristics. November 1, 2005 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 15-1 Lecture 15 - The pn Junction Diode (I) I-V Characteristics November 1, 2005 Contents: 1. pn junction under bias 2. I-V characteristics

More information

HICUM Parameter Extraction Methodology for a Single Transistor Geometry

HICUM Parameter Extraction Methodology for a Single Transistor Geometry HICUM Parameter Extraction Methodology for a Single Transistor Geometry D. Berger, D. Céli, M. Schröter 2, M. Malorny 2, T. Zimmer 3, B. Ardouin 3 STMicroelectronics,, France 2 Chair for Electron Devices

More information

Charge-Storage Elements: Base-Charging Capacitance C b

Charge-Storage Elements: Base-Charging Capacitance C b Charge-Storage Elements: Base-Charging Capacitance C b * Minority electrons are stored in the base -- this charge q NB is a function of the base-emitter voltage * base is still neutral... majority carriers

More information

Introduction to Transistors. Semiconductors Diodes Transistors

Introduction to Transistors. Semiconductors Diodes Transistors Introduction to Transistors Semiconductors Diodes Transistors 1 Semiconductors Typical semiconductors, like silicon and germanium, have four valence electrons which form atomic bonds with neighboring atoms

More information

Lecture 17. The Bipolar Junction Transistor (II) Regimes of Operation. Outline

Lecture 17. The Bipolar Junction Transistor (II) Regimes of Operation. Outline Lecture 17 The Bipolar Junction Transistor (II) Regimes of Operation Outline Regimes of operation Large-signal equivalent circuit model Output characteristics Reading Assignment: Howe and Sodini; Chapter

More information

Institute of Solid State Physics. Technische Universität Graz. Exam. Feb 2, 10:00-11:00 P2

Institute of Solid State Physics. Technische Universität Graz. Exam. Feb 2, 10:00-11:00 P2 Technische Universität Graz nstitute of Solid State Physics Exam Feb 2, 10:00-11:00 P2 Exam Four questions, two from the online list. Calculator is ok. No notes. Explain some concept: (tunnel contact,

More information

Lecture 35 - Bipolar Junction Transistor (cont.) November 27, Current-voltage characteristics of ideal BJT (cont.)

Lecture 35 - Bipolar Junction Transistor (cont.) November 27, Current-voltage characteristics of ideal BJT (cont.) 6.720J/3.43J - Integrated Microelectronic Devices - Fall 2002 Lecture 35-1 Lecture 35 - Bipolar Junction Transistor (cont.) November 27, 2002 Contents: 1. Current-voltage characteristics of ideal BJT (cont.)

More information

Lecture 13 - Carrier Flow (cont.), Metal-Semiconductor Junction. October 2, 2002

Lecture 13 - Carrier Flow (cont.), Metal-Semiconductor Junction. October 2, 2002 6.72J/3.43J - Integrated Microelectronic Devices - Fall 22 Lecture 13-1 Contents: Lecture 13 - Carrier Flow (cont.), Metal-Semiconductor Junction October 2, 22 1. Transport in space-charge and high-resistivity

More information

Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003

Lecture 17 - The Bipolar Junction Transistor (I) Forward Active Regime. April 10, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 17-1 Lecture 17 - The Bipolar Junction Transistor (I) Contents: Forward Active Regime April 10, 2003 1. BJT: structure and basic operation

More information

SOLUTIONS: ECE 606 Homework Week 10 Mark Lundstrom. Purdue University. (Revised 3/29/13)

SOLUTIONS: ECE 606 Homework Week 10 Mark Lundstrom. Purdue University. (Revised 3/29/13) ECE- 66 SOLUTIOS: ECE 66 Homework Week 1 Mark Lundstrom (Revised 3/9/13) 1) In a forward- biased P junction under low- injection conditions, the QFL s are aroximately flat from the majority carrier region

More information

Solid State Electronics. Final Examination

Solid State Electronics. Final Examination The University of Toledo EECS:4400/5400/7400 Solid State Electronic Section elssf08fs.fm - 1 Solid State Electronics Final Examination Problems Points 1. 1. 14 3. 14 Total 40 Was the exam fair? yes no

More information

Memories Bipolar Transistors

Memories Bipolar Transistors Technische Universität Graz nstitute of Solid State Physics Memories Bipolar Transistors Technische Universität Graz nstitute of Solid State Physics Exams February 5 March 7 April 18 June 27 Exam Four

More information

Chapter 2. - DC Biasing - BJTs

Chapter 2. - DC Biasing - BJTs Chapter 2. - DC Biasing - BJTs Objectives To Understand : Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

(Refer Slide Time: 03:41)

(Refer Slide Time: 03:41) Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 25 PN Junction (Contd ) This is the 25th lecture of this course

More information

13. Bipolar transistors

13. Bipolar transistors Technische Universität Graz Institute of Solid State Physics 13. Bipolar transistors Jan. 16, 2019 Technische Universität Graz Institute of Solid State Physics bipolar transistors npn transistor collector

More information

Lecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium September 20, 2005

Lecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium September 20, 2005 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 4-1 Contents: Lecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium September 20, 2005

More information

EE 3329 Electronic Devices Syllabus ( Extended Play )

EE 3329 Electronic Devices Syllabus ( Extended Play ) EE 3329 - Electronic Devices Syllabus EE 3329 Electronic Devices Syllabus ( Extended Play ) The University of Texas at El Paso The following concepts can be part of the syllabus for the Electronic Devices

More information

Choice of V t and Gate Doping Type

Choice of V t and Gate Doping Type Choice of V t and Gate Doping Type To make circuit design easier, it is routine to set V t at a small positive value, e.g., 0.4 V, so that, at V g = 0, the transistor does not have an inversion layer and

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

For the following statements, mark ( ) for true statement and (X) for wrong statement and correct it.

For the following statements, mark ( ) for true statement and (X) for wrong statement and correct it. Benha University Faculty of Engineering Shoubra Electrical Engineering Department First Year communications. Answer all the following questions Illustrate your answers with sketches when necessary. The

More information

figure shows a pnp transistor biased to operate in the active mode

figure shows a pnp transistor biased to operate in the active mode Lecture 10b EE-215 Electronic Devices and Circuits Asst Prof Muhammad Anis Chaudhary BJT: Device Structure and Physical Operation The pnp Transistor figure shows a pnp transistor biased to operate in the

More information

Most matter is electrically neutral; its atoms and molecules have the same number of electrons as protons.

Most matter is electrically neutral; its atoms and molecules have the same number of electrons as protons. Magnetism Electricity Magnetism Magnetic fields are produced by the intrinsic magnetic moments of elementary particles associated with a fundamental quantum property, their spin. -> permanent magnets Magnetic

More information

Chapter 2 - DC Biasing - BJTs

Chapter 2 - DC Biasing - BJTs Objectives Chapter 2 - DC Biasing - BJTs To Understand: Concept of Operating point and stability Analyzing Various biasing circuits and their comparison with respect to stability BJT A Review Invented

More information

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information

MENA9510 characterization course: Capacitance-voltage (CV) measurements

MENA9510 characterization course: Capacitance-voltage (CV) measurements MENA9510 characterization course: Capacitance-voltage (CV) measurements 30.10.2017 Halvard Haug Outline Overview of interesting sample structures Ohmic and schottky contacts Why C-V for solar cells? The

More information

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model

Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model Content- MOS Devices and Switching Circuits Review of Band Energy Diagrams MIS & MOS Capacitor MOS TRANSISTORS MOSFET Capacitances MOSFET Static Model A Cantoni 2009-2013 Digital Switching 1 Content- MOS

More information

The Mextram Bipolar Transistor Model

The Mextram Bipolar Transistor Model Date of issue: January 25, 2016 The Mextram Bipolar Transistor Model level 504.12 G. Niu, R. van der Toorn, J.C.J. Paasschens, and W.J. Kloosterman Mextram definition document NXP Semiconductors 2006 Delft

More information

Schottky Rectifiers Zheng Yang (ERF 3017,

Schottky Rectifiers Zheng Yang (ERF 3017, ECE442 Power Semiconductor Devices and Integrated Circuits Schottky Rectifiers Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Schottky Rectifier Structure 2 Metal-Semiconductor Contact The work function

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

CHAPTER 4: P-N P N JUNCTION Part 2. M.N.A. Halif & S.N. Sabki

CHAPTER 4: P-N P N JUNCTION Part 2. M.N.A. Halif & S.N. Sabki CHAPTER 4: P-N P N JUNCTION Part 2 Part 2 Charge Storage & Transient Behavior Junction Breakdown Heterojunction CHARGE STORAGE & TRANSIENT BEHAVIOR Once injected across the junction, the minority carriers

More information

Getting J e (x), J h (x), E(x), and p'(x), knowing n'(x) Solving the diffusion equation for n'(x) (using p-type example)

Getting J e (x), J h (x), E(x), and p'(x), knowing n'(x) Solving the diffusion equation for n'(x) (using p-type example) 6.012 - Electronic Devices and Circuits Lecture 4 - Non-uniform Injection (Flow) Problems - Outline Announcements Handouts - 1. Lecture Outline and Summary; 2. Thermoelectrics Review Thermoelectricity:

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

A Simplified, Analytical, One-Dimensional Model for Saturation Operation of the Bipolar Transistor

A Simplified, Analytical, One-Dimensional Model for Saturation Operation of the Bipolar Transistor 82 A Simplified, Analytical, One-Dimensional Model for Saturation Operation of the Bipolar Transistor G.T. Wright and P.P. Frangos Electronic and Electrical Engineering Department, University of Birmingham,

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

Junction Bipolar Transistor. Characteristics Models Datasheet

Junction Bipolar Transistor. Characteristics Models Datasheet Junction Bipolar Transistor Characteristics Models Datasheet Characteristics (1) The BJT is a threeterminal device, terminals are named emitter, base and collector. Small signals, applied to the base,

More information

Lecture 20 - p-n Junction (cont.) October 21, Non-ideal and second-order effects

Lecture 20 - p-n Junction (cont.) October 21, Non-ideal and second-order effects 6.70J/3.43J - Integrated Microelectronic Devices - Fall 00 Lecture 0-1 Lecture 0 - p-n Junction (cont.) October 1, 00 Contents: 1. Non-ideal and second-order effects Reading assignment: del Alamo, Ch.

More information

ELEC 3908, Physical Electronics, Lecture 13. Diode Small Signal Modeling

ELEC 3908, Physical Electronics, Lecture 13. Diode Small Signal Modeling ELEC 3908, Physical Electronics, Lecture 13 iode Small Signal Modeling Lecture Outline Last few lectures have dealt exclusively with modeling and important effects in static (dc) operation ifferent modeling

More information

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

More information

Semiconductor Physics fall 2012 problems

Semiconductor Physics fall 2012 problems Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each

More information

V BI. H. Föll: kiel.de/matwis/amat/semi_en/kap_2/backbone/r2_2_4.html. different electrochemical potentials (i.e.

V BI. H. Föll:  kiel.de/matwis/amat/semi_en/kap_2/backbone/r2_2_4.html. different electrochemical potentials (i.e. Consider the the band diagram for a homojunction, formed when two bits of the same type of semicondutor (e.g. Si) are doped p and ntype and then brought into contact. Electrons in the two bits have different

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Lecture 29: BJT Design (II)

Lecture 29: BJT Design (II) NCN www.nanohub.org C606: Solid State Devices Lecture 9: JT Design () Muhammad Ashraful Alam alam@purdue.edu Alam C 606 S09 1 Outline 1) Problems of classical transistor ) Poly Si emitter 3) Short base

More information

Forward-Active Terminal Currents

Forward-Active Terminal Currents Forward-Active Terminal Currents Collector current: (electron diffusion current density) x (emitter area) diff J n AE qd n n po A E V E V th ------------------------------ e W (why minus sign? is by def.

More information

Lecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium. February 13, 2003

Lecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium. February 13, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 4-1 Contents: Lecture 4 - PN Junction and MOS Electrostatics (I) Semiconductor Electrostatics in Thermal Equilibrium February 13, 2003

More information

Diodes. anode. cathode. cut-off. Can be approximated by a piecewise-linear-like characteristic. Lecture 9-1

Diodes. anode. cathode. cut-off. Can be approximated by a piecewise-linear-like characteristic. Lecture 9-1 Diodes mplest nonlinear circuit element Basic operation sets the foundation for Bipolar Junction Transistors (BJTs) Also present in Field Effect Transistors (FETs) Ideal diode characteristic anode cathode

More information

Decemb er 20, Final Exam

Decemb er 20, Final Exam Fall 2002 6.720J/3.43J Integrated Microelectronic Devices Prof. J. A. del Alamo Decemb er 20, 2002 - Final Exam Name: General guidelines (please read carefully b efore starting): Make sure to write your

More information

( )! N D ( x) ) and equilibrium

( )! N D ( x) ) and equilibrium ECE 66: SOLUTIONS: ECE 66 Homework Week 8 Mark Lundstrom March 7, 13 1) The doping profile for an n- type silicon wafer ( N D = 1 15 cm - 3 ) with a heavily doped thin layer at the surface (surface concentration,

More information

DC and AC modeling of minority carriers currents in ICs substrate

DC and AC modeling of minority carriers currents in ICs substrate DC and AC modeling of minority carriers currents in ICs substrate Camillo Stefanucci, Pietro Buccella, Maher Kayal and Jean-Michel Sallese Swiss Federal Institute of Technology Lausanne, Switzerland MOS-AK

More information

Modeling and Analysis of Full-Chip Parasitic Substrate Currents

Modeling and Analysis of Full-Chip Parasitic Substrate Currents Modeling and Analysis of Full-Chip Parasitic Substrate Currents R. Gillon, W. Schoenmaker September 11, 2017 Rev. 2.0 1 Outline Objectives Challenges SPX solver Solutions l Compact Modeling (ONSEMI) l

More information

Student Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS

Student Number: CARLETON UNIVERSITY SELECTED FINAL EXAMINATION QUESTIONS Name: CARLETON UNIVERSITY SELECTE FINAL EXAMINATION QUESTIONS URATION: 6 HOURS epartment Name & Course Number: ELEC 3908 Course Instructors: S. P. McGarry Authorized Memoranda: Non-programmable calculators

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at

More information

Yun Shi. Certificate of Approval: Foster Dai Associate Professor Electrical and Computer Engineering

Yun Shi. Certificate of Approval: Foster Dai Associate Professor Electrical and Computer Engineering DESIGN AND OPTIMIZATION OF NANO-SCALED SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTORS Except where reference is made to the work of others, the work described in this dissertation is my own or was

More information

A study of the silicon Bulk-Barrier Diodes designed in planar technology by means of simulation

A study of the silicon Bulk-Barrier Diodes designed in planar technology by means of simulation Journal of Engineering Science and Technology Review 2 (1) (2009) 157-164 Research Article JOURNAL OF Engineering Science and Technology Review www.jestr.org A study of the silicon Bulk-Barrier Diodes

More information

Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009

Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009 HICUM/L0 v1.2: Application to Millimeter Wave Devices Didier CELI, 22 nd Bipolar Arbeitskreis, Würzburg, October 2009 Outline Purpose ariation of reverse Early effect with the evolution of technologies

More information