CMOS Analog Integrated Circuits: Models, Analysis, & Design

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1 CMOS Analog Integrated Ciruits: Models, Analysis, & Design Dr. John Choma, Jr. Professor of Eletrial Engineering University of Southern California Department of Eletrial Engineering-Eletrophysis University Park; Mail Code: 071 os Angeles, California [OFF] [HOME] [FAX] (E-MAI) EE448 MOS Ciruit evel Models Fall 001

2 eture Overview Stati Model Cutoff Region Ohmi (Triode) Region Model Saturation Region Model Subthreshold Model Short Channel Effets In Saturation Channel ength Modulation Substrate/Bulk Phenomena Mobility Degradation Carrier Veloity Saturation Small Signal Model In Saturation Forward Transondutane Bulk Transondutane Capaitanes Sample Ciruit Analysis (Inverter) Gain Bandwidth

3 N Channel MOSFET d d S G D Silion Dioxide T ox X d N Soure N Drain W P Type Substrate (Conentration = N D m -3 ) B V gd G I g I d I b B D V ds I s = I d I g I b I g 0 I b 0, for V bs < 0 V gs I s V bs S V ds I s I d = V gs V gd 3

4 P Channel MOSFET d d S G D Silion Dioxide T ox X d P Soure P Drain W N Type Substrate (Conentration = N D m -3 ) B V dg I d D I s = I d I g I b I g 0 G I g I b B V sd I b 0, for V sb < 0 V sg I s V sb S V sd I s I d = V sg V dg 4

5 Charateristi Curves: Cutoff And Ohmi Regimes Cutoff Regime: I d = 0 Threshold Voltage, Funtion Of Bulk Soure Voltage V hn V gs < V hn Ohmi Regime: I d = K n W V gs V hn and V ds < V gs V hn V ds V gs V hn V ds K n = µ n C ox = µ n ε ox (Hundreds Of µmhos/volt) T ox Comments W/ Is Gate Channel Aspet Ratio, A Designable Parameter V ds = V gs V gd < V gs V hn Implies V gd > V hn Temperature Effets (Holes And Eletrons): µ(t) µ(t o ) T o T 3/ Resistane For Small Drain Soure Voltage: I d V ds 1 = K W R n ds V gs V hn V ds = I d V ds V gs V hn V ds V gs V hn V ds I d V ds 5

6 Charateristi Curves: Saturated Regime Saturation Regime: I d = V dss I dss K n = K n W V gs V hn & V ds V gs V hn V gs V hn V gs V hn Drain Saturation Voltage W V dss Comments Square aw Voltage Controlled Current Soure Drain Current Shows Negative Temperature Coeffiient Beause Of Its Proportionality To Mobility Differential Current Of Two Mathed Devies Is inear With Differential Gate Soure Voltage V DM, Provided Common Mode Gate Soure Voltage Is A Constant V CM Drain Saturation Current I d1 I d = K n W V gs1 V hn V gs V hn I d1 I d = K n W I d1 I d = K n W V gs1 V gs V CM V hn V DM V hn V gs1 V gs 6

7 Simple Differential Pair V DD Inputs R V o R V gs1 = V CM V DM I d1 I d V gs = V CM V DM V DM M1 M V DM V gs1 V gs = V CM V gs1 V gs = V DM V CM Response I d1 I d = K W n V CM V hn V DM V o = R I d1 I d = K n R W V CM V hn V DM Note Differential Output Current And Voltage Are inear With Respet To Differential Input Voltage Without Invoking Small Signal Approximation 6a

8 Charateristi Curves: Subthreshold Regime Subthreshold Regime: V gs < V hn n V T & V ds 3 V T V T = k T q = 6 7 8C 1. < n <.0 I d = K n W nv T ε e ( V gs V hn ) / nv T Comments Bipolar Type I V Ation Indigenous To Subthreshold Regime Subthreshold Operation Corresponds To Gate Channel Interfae Potentials ying Between One And Two Fermi Potentials Useful Only For ow Speed, ow Power Appliations 7

9 Sample Simplified MOS Stati Charateristis Drain Current (miroamperes) volts Ohmi Regime Drain Saturation Current 4 volts Saturation Regime K n W = 80 µmho/volt V hn = 1. volts 3 volts 100 Gate-Soure Voltage = volts Drain-Soure Voltage (volts) 8

10 Cutoff Regime S V gs G V ds SiO D I d Depletion V ds 0 0 < V gs < V hn N Soure Fixed Immobile Charges DEPETION AYER, V > 0 ds DEPETION AYER, V = 0 ds N Drain V bs 0 Zero Current V gs = V ox V y V ox Voltage Aross Oxide P Type Substrate V y Interfae Potential V bs B 9

11 Channel Inversion: Ohmi Regime S G D N Soure P Type Substrate N Drain V gs > V hn V ds = 0 S G D V gs > V hn N Soure N Drain 0 V ds V gs V hn V dss DV ds V gd > V hn ' D P Type Substrate Metal or Polysilion Inversion ayer Silion Dioxide Depletion 10

12 Channel Inversion: Saturation Regime S G D N Soure P Type Substrate N Drain V gs > V hn 0 V ds = V gs V hn V gd V hn S G D V gs > V hn N Soure N Drain 0 V ds > V gs V hn V gd < V hn V dss V ds ' P Type Substrate Metal or Polysilion Inversion ayer Silion Dioxide Depletion 11

13 S Channel ength Modulation G D N Soure N Drain V dss V ds ' D Modified Saturation Regime Current I d V ds > V dss = I dss = K n Channel Modulation Voltage W V gs V hn 1 V ds V dss V λ V λ qn = A V ε ds V dss V j s (Typially Under 0 Volts And As Small As 1/3 Volt For Deep Submiron MOSFETs) V dss = V gs V hn V j = k T q ln N D N A N ib 1

14 Channel ength Modulation Parameters Modified Saturation Regime Current I d V ds > V dss = I dss = K n W V gs V hn 1 V ds V dss V λ V dss = V gs V hn V j = Parameters Average Substrate Impurity Conentration N A e s k T q ln N D N A N ib Dieletri Constant Of Silion (1.05 pf/m) q Eletroni Charge Magnitude V l Channel ength Modulation Voltage V j Built In Substrate Drain/Soure Juntion Potential Note arge Channel ength Redues Channel Modulation Small Substrate Conentration Inreases Channel Modulation V λ = qn A ε s V ds V dss V j 13

15 Substrate/Bulk Phenomena Effet On Threshold Voltage I d V h = V ho V θ V F V T 1 V θ = qn Aε s T = q N A ε ox s (High Hundreds Of µvolts) V F = V T ln N A (Few Tenths Of Volts) Parameters Fermi Potential; Renders Channel Surfae Intrinsi V F N ib Intrinsi Carrier Conentration In Substrate Dieletri Constant Of Silion Dioxide (345 ff/m) εox = K n C ox W N ib V gs V hn 1 ε ox V ds V dss V λ V bs V F V T 1 Note Small Oxide Thikness Redues Threshold Modulation Small Substrate Conentration Redues Threshold Modulation 14

16 Threshold Voltage Modulation Threshold Corretion (volts) 0.7 Oxide Thikness = 1,500 A N ib = m 3 ; N A = (10) 14 m A A 100 A Bulk Soure Voltage, Vbs (volts) 0 15

17 Mobility Degradation Due To To Vertial Field Eletri Field Problems Thin Oxide ayers Condue arge Gate -To- Channel Fields For Even Small -To- Moderate Gate Soure Voltages These Enhaned Fields Impart Inreasing Energies To Carriers, Thereby Causing More Carrier Collisions And Degraded Mobilities Mobility: µ neff 1 µ n V gs V hn V E V E (500)(106 )T ox (ow Hundreds Of Volts) Parameters Effetive Carrier Mobility In Channel µ neff V E Vertial Field Degradation Voltage Parameter Crude One Dimension Approximation To Two Dimensional Problem in MKS Units Yields In Volts T ox V E 16

18 Impat Of Of Mobility Degradation Stati Drain Current K n = µ n C ox K neff = µ neff C ox I d = K n W V gs V hn 1 1 V gs V hn V E V ds V dss V λ Other Effets Redued Bandwidth And Inreased Carrier Transit Time Smaller Current For Given Gate Soure Bias Redued Forward Transondutane 17

19 Mobility Degradation Due To To ateral Field Eletri Field Problems Short Channels Condue arge Drain -To- Soure Fields For Even Small -To- Moderate Drain Soure Voltages These Enhaned Fields Impart Inreasing Energies To Carriers, Thereby Causing More Carrier Collisions And Degraded Mobilities At Very arge Horizontal Fields, Carrier Veloities Ultimately Saturate To A Value Of v sat, Whih Is About 0.1 µm/psec Saturation Ours When Horizontal Field, E h,equals Or Exeeds A Critial Value,, Whih Is About 5 V/µm Mobility And Field µ ne E 1 v sat = µ n E v = µ ne E h µ n = E h E E h V gs V hn E µ n E h E 1 h E v sat E h 18

20 Veloity Mobility Field Relationships Carrier Veloity (µm/pse) 0.1 Normalized Carrier Mobility Carrier Veloity Normalized Mobility ateral Eletri Field (V/µm) a

21 Mobility And ateral Field Mobility And Field µ ne 1 µ n E h E 1 µ n V gs V hn E = 1 µ n V dss E E h V gs V hn = V dss Eletri Field Problems Crude Approximation For Horizontal Field, Free Carriers Exist Only Over Channel Where Voltage With Respet To The Soure Is At Most V dss = V gs V hn Channel ength,, Should Be Effetive Channel ength, ', But This Shrinkage Is Already Aounted For By Channel ength Modulation Voltage Parameter, V λ E Is About 1.75 Volts For = 0.35 µm E h 19

22 Volt Ampere Impat Of Of High ateral Field Stati Drain Current Very High Fields V gs V hn >> E K n = µ n C ox K neff = µ neff C ox I d I d = K n W WC ox v sat (V gs V hn ) 1 1 V gs V hn E V gs V hn 1 V ds V dss V λ V ds V dss V l Comments Drain Current Sales Approximately With W, As Opposed To W/ Drain Current Almost inear W/R To Gate Soure Voltage 0

23 MOS arge Signal Model C old D i d Stati Drain Current C gd C gs Gate-Drain Capaitane Gate-Soure Capaitane C gd r dd DBD r db C db Drain-Bulk Capaitane G C gs I d C db DBS r sb r bb B C sb C old C ols Soure-Bulk Capaitane Drain Overlap Capaitane Soure Overlap Capaitane r ss C sb r dd Drain Ohmi Resistane C ols S r ss r bb Soure Ohmi Resistane Bulk Ohmi Resistane DBD Bulk-Drain Diode r sb Bulk Spreading Resistane DBS Bulk-Soure Diode r db Bulk Spreading Resistane 1

24 Devie Capaitanes In In Saturation D G C old C gd i d r dd I d DBD C db r db C gd C old C old = W d C ox C gs = W C ox 3 A d C jo C db = 1 V bd V j d C gs r ss DBS C sb r sb r bb B C sb = A s W C jo 1 V bs V j C ols C ols = W d C ox C db C sb C gs S arge (Hundreds Of ff) arge (Hundreds Of ff) Moderate (High Tens Of ff) A d A s C jo Drain-Bulk Juntion Area Soure-Bulk Juntion Area Zero Bias Depletion Capaitane Density C gd, C old, C ols Small (Tens Of ff)

25 Approximate (ong Channel) Small Signal Model C old C gd D C db g mf I d V gs Q K n W I dq g mb I d = λ b g mf g mf v ga g mb v ba g o V bs Q G C gs v ga C ols S C sb v ba B λ b = g o I d V θ / V F V T V bsq V ds Q V λ V ds I dq V dss Assumptions All Series Ohmi Resistanes Are Negligible Transistor Operates In Saturation Regime "ong Channel" Approximation Invoked For Stati Drain Current Model To Be Used As A Preursor To Computer Based Studies 3

26 Short Channel Small Signal Model Drain Current: I d Intermediate Parameters: = K n W V gs V hn 1 1 f λ = V ds V dss V λ g mf = K W n V gs V hn E V ds V dss V λ f = V dss E I dq λ b = V θ / V F V T V bsq Forward Transondutane: g mfs = g mf 1 f λ 1 f 1 V dss /V λ 1 f λ f / 1 f Bulk Transondutane: g mbs = λ b g mfs Output Condutane: g o = V λ V ds I dq V dss 4

27 Hypothetial Devie Physial Parameters N A = 5 (10) 14 m 3 N D = 5 (10) 0 m 3 N ib = (10) 10 m 3 ε s ε ox = 1.05 pf/m = 345 ff/m µ n = 400 m / volt-se E = 4 volts / µm Devie Parameters T ox = 50 Angstroms = 0.35 µm V hn = 0.65 volts T = 300 8K W / = 5 Ciruit Parameters V ds = volts V gs = 1. volts V bs = 3 volts 5

28 Peripheral Calulations V F = 80.0 mv V j = mv V u = µv Stati Performane (Fermi Potential) (Juntion Potential) (Body Effet Potential) V hn = 685. mv (Compensated Threshold) V hn = 35. mv V dss = mv (Drain Saturation Voltage) V = mv λ E = 1.4 volts (Channel ength Voltage) (ateral Field Voltage) K n = 76.0 µmho / volt (Transondutane Parameter) f =.18 (Channel ength Parameter) λ f = (ateral Field Parameter) Stati Drain Current I d = 18.9 µa I d = 430. µa (ong Channel Drain Current) (Short Channel Drain Current) Note Short Channel -To- ong Channel Ratio of.35; Ratio Is Generally Between 1.5 And 3.0 6

29 Small Signal Parameters Forward Transondutane g mf = 1.09 mmho g mf = 1.5 mmho (Inorporating Short Channel Effets) Note Short Channel -To- ong Channel Ratio of 1.14; Ratio Is Generally Between 0.5 And.0 Bulk Transondutane λ (10) 3 b = 5.0 g mb = 6.5 µmho (Ignoring Short Channel Effets) (Bulk Parameter) (Inorporating Short Channel Effets) Note Bulk Transondutane Is About 00 Times Smaller Than Forward Transondutane Drain Soure Condutane g o = µmho (Inorporating Short Channel Effets) Corresponds To Shunt Output Resistane Of About 5 KΩ Mandates Condutane Enhanement Strategies When Designing High Performane Transondutors 7

30 V dd Devie Unity Gain Frequeny D C AC Short Ciruit gd C old I bias C big g mf v 1 g mb v g o i out i in i out i in G C gs C ols v 1 S v B i out = i in s g mf s C gd C old C gs C ols C gd C old ω T g mf C gs C ols C gd C old µ n V gs V hn 3 3 d Comments Unity Gain Frequeny Is Good Devie Figure Of Merit; Crude Ciruit Performane Figure Of Merit Result Assumes ω T C gd << g mf 8

31 Common Soure Inverter M V DD R eff R eff MD C V o MD C V os V s V GG V s Shemati Diagram AC Shemati Diagram 9

32 Inverter oad Resistane Calulations r ddl V x M I x v ga g mfl v ga g mbl v ba r ol v ba V x r ssl I x r bbl v ga = v ba = V x r ssl I x V x = r ssl r ddl I x r ol I x g mfl v ga g mbl v ba R eff V x I x = r ssl r ddl r ol 1 1 λ bl g mfl r ol 1 1 λ bl g mfl 30

33 Inverter Gain Calulations R' R out R eff V os V s MD C V os V s v ga g mfd v ga r ddd g mbd v ba r ssd r od R eff v ba r bbd C Ignore For ow Frequenies A v = V os V s = g mfd R eff 1 1 λ bd g mfd r ssd R eff r ddd r ssd r od g mfd R eff g mfd 1 λ bl g mfl A v 1 1 λ bl W d / W l / 31

34 Inverter Bandwidth Calulations r ddd R' V x I x v ga g mfd v ga g mbd v ba r od v ba r ssd r bbd B 3dB = 1 R out C = 1 R / R eff C 1 R eff C R / = V x I x = r ddd r ssd 1 1 λ bl g mfd r ssd r od B 3dB 1 R eff C 1 λ bl g mfl C GBP Av B 3dB = g mfd C 3

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