The Mismatch Behavior P(x,y)

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3 The Mismatch Behavior P(x,y) x y σ 2 ( P) = f A ( WL, ) + f D ( D) f A ( W, L) Small random, transistor size dependent component, true mismatch component f D ( D) Gradient surface, transistor distance dependent component, can be eliminated with layout techniques Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

4 Historical Perspective. Mismatch Models in Strong Inversion σ ( P) = fwl (, ) + S P D 2 σ ( β/β) 2 σ ( VT0 ) 2 σ ( θo ) 2 σ ( θ) 2 σ ( θe ) Pelgrom89 Bastos98 Serrano99 2 σ ( γ) V DS sat θ = θ o θ V GS V e T µc ox l d R µ 1 θ o = θ θ L e = C L 2v ox l d R s Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

5 A Continuous Transistor Model from Weak to Strong Inversion. The ACM Model I DS = I s ( i f ( V P V S ) i r ( V P V D )) V P V SD ( ) = φ t ( 1 + i fr ( ) 2 + ln( 1 + i fr ( ) 1) ) n = 1 V G V TO V P = n γ V G V TO + 2φ F + γ 2φ F + 1 4γ 2 1 2γ 2 I S = I S 'n = µnc' ox ( W L) φ t 2 Continuous for all transistor operation regions Based on a reduced set of physically meaningful parameters { I S, V TO, γ, φ F } Drain/Source symmetric Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

6 Introducing Continuosly Second Order Effects traditionally, I S ( i f i r )( 1 + λ( V D V S )) I DS = θ o [ V P V S ] θe V DSeff, V DSeff = V DS in ohmic region; V DSeff = V P V S 0.5 [ x ] + [x]+ E E in saturation. define smoothed rectification [ ] + 0 if x < E [ x] + = ( x + E) if E < x < E 4E x if x > E redefine V DSeff = [ V P V S ] + [ V P V D ] E 0 E x E 0 E 0.5 x with E = 0,3V DS Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

7 A Continuous Mismatch Model Valid from Weak to Strong Inversion I S ( i f i r )( 1 + λ( V D V S )) I DS = θ o [ V P V S ] θe V DSeff I DS I DS = I S I S + 1 I DS V P 1 I DS V P V I DS V P V T T0 I DS V P n 1 n γ n γ 1 I DS 1 I DS θ I DS θ o θ o I DS θ e e I S , V I T0, γ, θ o, θ e S Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

9 Mismatch Characterization Chip DN DP S G Bus G S DN DP W /L 1 1 DECODER W 1 /L 2. Bus Enable W 6 /L 5 row select column select Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

10 Measuring Curves: 7 Measured Curves V DS = 1,65V Curve 1: I DS ( V GS ), V SB = 0V, V GS [ 03,3, ] Curve 2: I DS ( V GS ), V SB = 1V, V GS [ 03,3, ] V DS = 0,1V Curve 3: I DS ( V GS ), V SB = 0V, V GS [ 03,3, ] Curve 4: I DS ( V GS ), V SB = 1V, V GS [ 0, 3,3] V G = 1,25V S + α Curve 5: I DS ( V S ),α = α 1, V S [ 0, 3,3] Curve 6: I DS ( V S ), α = α 2,V S [ 03,3, ] Curve 7: I DS ( V S ), α = α 3, V S [ 0, 3,3] where: α 1, α 2 and α 3 are values of V G from curve 1 so that we are in weak, moderate and strong inversion respectively. V g V SB log( I ds ) I ds I ds V DS curves 1, 2, 3, 4 V g curves 5, 6, 7 V s Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

12 Computing Statistics x σ I S I S x x x x ( ) σ γ ( ) σ V ( T0 ) x x x x ( ) σ θ o σ θ e ( ) x Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

13 Computing Statistics σ I ( S I S ) 1 ( WL ) 1 ( WL) σ γ ( ) σ V ( T0 ) 1 ( WL) σ θ ( e ) 1 ( WL) σ( θ o ) 1 ( WL) Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

14 Predicting σ I Iof measured curves and errors ( ) ( σ I/I ( ) meas σ I/I ( ) pred ) σ( I/I) meas σ 2 I DS I DS = 2 1 I DS I DS I DS I DS 2 2 σ IS σ I DS VTO VT σ I DS γ γ σ I DS θo θo σ I DS θe θe +correlation 15 σ( I/I) σ( I/I) (σ meas σ ft )/σ meas (σ meas σ ft )/σ meas I mean 10 5 I mean V G V G σ( I/I) σ( I/I) (σ meas σ ft )/σ meas (σ meas σ ft )/σ meas σ( I/I) I mean 10 5 I mean σ( I/I) I 10 1 mean I mean (σ meas σ ft )/σ meas V G V G (σ meas σ ft )/σ meas V G V G Curve 1. V DS = 1,65V V S = 0V Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

15 Correlations θ o θ e γ V T0 I S I S 1 L 1 L 1 L 1 L V T0 1 L 1 L 1 L γ 40µm 20µm 1 L 1 L 10µm 5µm 2µm θ e 0,8µm 1 L Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

17 Nominal Measured Curves Mismatch Measurements W = 0.12μm L = 0.1μm W = 12μm L = 10μm CMOS Transistors 90nm process 25 different sizes 64 devices each size Measured Curves with Mismatch Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN terese@imse-cnm.csic.es

18 Mismatch Measurements Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN

Instituto de Microelectrónica de Sevilla Phone: 34-95-4466666 Av.

19 Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN Extracted Mismatch Parameters Standard NMOS transistors 90nm process

20 Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN Measured vs. Predicted Current Mismatch Standard NMOS transistors 90nm process measured predicted

21 Error in Current Mismatch Prediction Standard NMOS transistors 90nm process Instituto de Microelectrónica de Sevilla Phone: Av. Americo Vespucio s/n Fax: Sevilla, SPAIN

23 Spectre Mismatch Model Implementation T - 26 Our intention is to create a model of a MOS transistor that fits with the results of the model. This model has been implemented in AHDL (Analog Hardware Description Language) and can be used in Simulator Spectre The model implementation is based on a current in parallel with a spectre library transistor that emulates the mismatch behavour. I DS I DS Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

24 T - 27 Spectre Mismatch Model Implementation I DS I DS Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameters I S ACM Model θ o Large signal parameters Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

25 T - 28 Spectre Mismatch Model Implementation I DS I DS Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameter box stores the 5 large signal parameters and the standard deviations and correlations of the 5 mismatch parameters Parameters I S θ o Large signal parameters ACM Model Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

26 T - 29 Spectre Mismatch Model Implementation -parameters Generator box obtains the five mismatch parameters using 5 uncorrelated random numbers and data stored on Parameters box I DS I DS Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameters I S ACM Model θ o Large signal parameters Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

27 T - 30 Spectre Mismatch Model Implementation I DS I DS Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameters I S ACM Model θ o Large signal parameters ACM Model box is used to obtain the large signal current using the 5 large signal Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

28 T - 31 Spectre Mismatch Model Implementation I DS I DS I DS Generator box obtains the current in parallel using the 5 large signal parameters calculated in the ACM Model box and the 5 mismatch parameters obtained in the -parameters Generator box Random Number x 1 parameters I S I DS I DS Generator x 5 Generator θ o Generator Standard deviations and correlations Parameters I S ACM Model θ o Large signal parameters Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

29 T - 33 I DS σ I DS Spectre Mismatch Model Implementation 10 1 I DS σ I DS 10 0 I DS σ I DS V GS I DS σ I DS V GS V GS V GS I DS σ I DS I DS σ I DS V GS 10 0 simulated fitted V GS Comparisson between simulated and fitted data for curve 1 and all transistor sizes Instituto de Microelectrónica de Sevilla Phone: CICA, Av. Reina Mercedes s/n, Fax: Sevilla, SPAIN bernabe@imse.cnm.es

Pelgrom JSSC-89 σ 2 ( P) = A P 2 2 2 ------- + S WL PD size dependent term distance

31 Pelgrom JSSC-89 σ 2 ( P) = A P S WL PD size dependent term distance independent (lot of literature) distance dependent term size independent (little literature)

32 σ 2 ( P) = A P S WL PD By analyzing the mathematical derivation P(x,y) x y

33 Gradient Component (x 2,y 2 ) random planes from die to die (x 1,y 1 ) P( x, y) = Ax + By + C random numbers die average

34 Generate random numbers A and B P( x, y) = Ax + By + C

35 Generate random numbers A and B P( x, y) = Ax + By + C Gradient-induced mismatch P grad_ij = Ax ( i - x j ) + B( y i - y j )

36 Generate random numbers A and B P( x, y) = Ax + By + C Gradient-induced mismatch P grad_ij = Ax ( i - x j ) + B( y i - y j ) Statistics over many planes σ 2 ( P grad _ ij ) = σ 2 ( A)x ( i - x j ) 2 + σ 2 ( B) ( y i - y j ) 2

37 Generate random numbers A and B P( x, y) = Ax + By + C Gradient-induced mismatch P grad_ij = Ax ( i - x j ) + B( y i - y j ) Statistics over many planes σ 2 ( P grad_ij ) = σ 2 ( A)x ( i - x j ) 2 + σ 2 ( B) ( y i - y j ) 2 no preferred directions: σ( A) = σ( B) σ 2 ( P grad_ij ) = σ 2 ( A) [( x i - x j ) 2 + ( y i - y j ) 2 ] = σ 2 ( A)D ij 2

38 Generate random numbers A and B P( x, y) = Ax + By + C Gradient-induced mismatch P grad_ij = Ax ( i - x j ) + B( y i - y j ) Statistics over many planes σ 2 ( P grad_ij ) = σ 2 ( A)x ( i - x j ) 2 + σ 2 ( B) ( y i - y j ) 2 no preferred directions: σ( A) = σ( B) σ 2 ( P grad_ij ) = σ 2 ( A) [( x i - x j ) 2 + ( y i - y j ) 2 ] = σ 2 ( A)D ij 2 σ 2 ( P ij ) = A P S WL PDij S P = σ( A) = σ( B)

39 Mismatch Modelling in a CAD Tool P i = P mean + P global + P rand_i + P grad_i Technology Average Corner (common for whole die) Size-dependent mismatch (2-10 random numbers per transistor) Gradient-induced mismatch (2 random numbers per die) need layout coordinates

memristors in a row. The wires in this image are 50nm about 150 atoms, wide. J.

exploiting new capabilities Models are needed to simulate architectures and circuits Physical

model has the advantage that circuit simulators are available allowing quick design and

41 Motivations: Why? New nano devices are rapidly appearing offering new functionality and memory capabilities 17 memristors in a row. The wires in this image are 50nm about 150 atoms, wide. J. J. Yang, HP Labs NOMFET OG-CNFET Parallely, new circuits and architectures should be devised exploiting new capabilities Models are needed to simulate architectures and circuits Physical modelling is a slow, complex and sophisticated process Fitting new devices to a compact CMOS model has the advantage that circuit simulators are available allowing quick design and simulation of new architectures Hybrid nano-cmos arquitectures can be easily simulated ZnO-MemoryFET Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es

42 EKV Compact Model [Enz et al. 1995] log scale I DS I F I R θ( V P min( V D, V S )) I off linear scale I F I R I s i f ( V P, V S ) I s i r ( V P, V D ) linear scale V P V G V TO n i fr ( ) 1 V P ln V SD ( ) + exp U t 2 linear scale Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es

43 ACM Compact Model [Cunha et al., 1995] I DS I F I R θ( V P min( V D, V S )) I off I F I R I s i f ( V P, V S ) I s i r ( V P, V D ) V P V P V G V TO n i 2 fr ( ) q' is( d) + V SD ( ) φ t q' is( d) 1 2q' is( d) (( ) + ln q' is( d) ) Other compact models could have been used [Iñiguez et al., 1995] Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es

NABAB Nano Devices: OG-CNFET OG-CNFET: Optically Gated Carbon Nanotube FET P-type Carbon nanotubes single/network coated with photosensitive polymers act as memory devices Change in conductance

44 NABAB Nano Devices: OG-CNFET OG-CNFET: Optically Gated Carbon Nanotube FET P-type Carbon nanotubes single/network coated with photosensitive polymers act as memory devices Change in conductance four orders of magnitude upon illumination Response to light robust and reversible Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN

NABAB Nano Devices: NOMFET NOMFET: Nano Particle Organic Memory FET Transistor Three terminal device p + common gate/200nm Si0 2 /gold source-drain electrodes/interelectrode gap 0.

45 NABAB Nano Devices: NOMFET NOMFET: Nano Particle Organic Memory FET Transistor Three terminal device p + common gate/200nm Si0 2 /gold source-drain electrodes/interelectrode gap μm Au nanoparticles deposed on the inter-electrode gap before pentacene deposition NPs are afterwards inmobilized using surface chemistry Pentacene (organic p-type semiconductor) deposited on top Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es

NABAB Nano Devices: ZnO NW memory FETs ZnO nanowires dispersed on a Si0 2 -coated Si substrate 100nm thick Si0 2 Drain/source metal electrodes grown by photolitography Coated with layer of

46 NABAB Nano Devices: ZnO NW memory FETs ZnO nanowires dispersed on a Si0 2 -coated Si substrate 100nm thick Si0 2 Drain/source metal electrodes grown by photolitography Coated with layer of ferroelectric nanoparticles shifts threshold voltage positively or negatively depending on polarization Top gate made easy to change the orientation of polarization completely Long retention times Reversible Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es

47 Fitting OG-CNFET to the EKV model. Experimental Results Different type of channel Different oxide thickness Different size * Device L g =200nm, t ox =2nm, single tube: I S =0.4nA n=1.22 V TO =0.7895V θ=1.7530v -1 I off =8.7pA Device L g =8000nm, t ox =10nm, network of nanotubes: I S =17.0nA n=7.78 V TO =0.5396V θ=2.2085v -1 I off =6.6pA r Device L g =8000nm, t ox =20nm, network of nanotubes: I S =28.6nA n=11.82 V TO =1.1904V θ=1.6013v -1 I off =2.5pA Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es

48 Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN Fitting OG-CNFET to the EKV model. Experimental Results

49 Fitting NOMFET to the EKV model. Experimental Results Same device Different programming conditions. Writing V GS =-50V for 30 seconds Erasing V GS =50V for 30 seconds * Device W=1000μm, L=1μm, t ox =200nm, initial: I S =58.6μA n=177 V TO =-44.95V θ=0v -1 I off =1.7μA r Device W=1000μm, L=1μm, t ox =200nm, after writing: I S =65.4μA n=199 V TO =-48.74V θ=0v -1 I off =0.6μA Device W=1000μm, L=1μm, t ox =200nm, after erasing: I S =6.7μA n=140 V TO =-28.44V θ=0v -1 I off =0.6μA Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es

50 Fitting ZnO Memory FET to the EKV Model. Experimental Results r Device bottom gated ZnO nanowire, L=3μm, t ox =100nm, V GS swept -10V to 15V: I S =0.5521nA n=1.84 V TO = V θ=0.0006v -1 I off =0.0259pA Device bottom gated ZnO nanowire, L=3μm, t ox =100nm, V GS swept 15V to -10V: I S =6.7μA n=10.88 V TO =1.6554V θ=0v -1 I off =0.1926pA Instituto de Microelectrónica de Sevilla Av. Americo Vespucio s/n, Sevilla, SPAIN terese@imse-cnm.csic.es

EECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-

EECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i- EECS40 Spring 010 Lecture 1: Matching Elad Alon Dept. of EECS Offset V i+ V i- To achieve zero offset, comparator devices must be perfectly matched to each other How well-matched can the devices be made?