ASM-HEMT: Compact Modeling of
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1 ASM-HEMT: Compact Modeling of GaN HEMTs for High Frequency and High Power Applications Dr. Yogesh S. Chauhan Associate Professor Nanolab, Department of Electrical Engineering IIT Kanpur Homepage
2 Outline Overview of Compact Modeling GaN HEMT ASM-HEMT Model Overview Model Validation 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 2
3 Joint Development & Collaboration 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 3
4 PDK and Compact Model 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 4
5 Enablers of a silicon chip design 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 5 Source: David HARAME at. al., IBM J. RES. & DEV. MARCH/MAY 2003
6 Goal of a PDK The output of Enablement Technology Innovation Enablement PDK Key to Happy Designers!! Circuit Designers Offer a circuit design environment that enables full exploitation of technology Capture all device physics Model impact of layout choices on device mean and variance Include typical layout effects for simulation from schematic Accurate modeling of layout effects for simulation from layout 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 6
7 Compact Modeling or SPICE Modeling Medium of information exchange Good model should be Accurate: Trustworthy simulations. Simple: Parameter extraction is easy. Balance between accuracy and simplicity depends on end application Excellent Convergence Simulation Time ~µsec Accuracy requirements ~ 1% RMS error after fitting Example: BSIM6, BSIM- CMG 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 7
8 Industry Standard Compact Models Standardization Body Compact Model Coalition CMC Members EDA Vendors, Foundries, IDMs, Fabless, Research Institutions/Consortia CMC is by the industry and for the industry 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 8
9 GaN Properties Device characteristics: High Breakdown Voltage ( ) Low ON Resistance ( ) 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 9 [U. K. Mishra et al., Proc. IEEE, 96 (2), 287 (2008)]
10 GaN HEMT: Advantages Alex Q. Huang pp , IEDM 2016 advantage of fast gate driving capability Reduction in switching loss in hard or soft switched converter Reverse recovery loss reduction 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 10
11 Polarization Polarization! Wurtzite 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 11 [O. Ambacher et al., JAP, 85 (6), 3222 (1999)]
12 GaN Wafers Sapphire (Al 2 O 3 ) Semi-insulating High growth temperatures Relatively cheap Silicon (Si) Low cost Large diameters Acceptable thermal conductivity Processing in standard silicon fabs Low thermal conductivity Lattice mismatch CTE mismatch Lattice mismatch CTE mismatch TEM Image of GaN on Sapphire Dislocations ~10 Silicon Carbide (SiC) High thermal conductivity Low Lattice mismatch Low CTE mismatch Highly costly Smaller Wafers [S. Huang, JJAP, 47 (10), 7998 (2008)] 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 12 [U. K. Mishra et al., Proc. IEEE, 96 (2), (2008)] [S. L. Selvaraj et al., Proc. DRC, 53 (2012)]
13 GaN HEMT Structure Ti/Al/Ti/Au S Pt/Au G AlGaN AlGaN Spacer Layer (UID) Ti/Al/Ti/Au D 2DEG GaN Graded AlGaN to GaN Substrate 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 13
14 AlGaN/GaN Hetero-structure The AlGaN/GaN hetero-structure is used to take advantage of the two dimensional electron gas (2-DEG) AlGaN/GaN materials create piezoelectric and spontaneous polarization effects using an un-doped hetero-interface 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 14
15 2DEG Source 1 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 15 [J. P. Ibbetson et al., APL, 77 (2), 250 (2000)]
16 Design Rules Materials Perspective Thickness of the barrier 2DEG control Al Mole Fraction 2DEG Concentration Nucleation and Buffer Layer Dislocations Substrate Thermal Properties 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 16
17 GaN HEMT Some interesting features of IIInitride system: Wide bandgap High 2-DEG charge density High electron mobility High breakdown voltage Excellent thermal conductivity High power density per mm of gate periphery GaN based HEMTs are able to operate in high frequency, high power as well as high temperature device applications 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 17
18 Field Plates Distribution of Field Plated Structure and 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 18 [H Huang, et al., IEEE TPEL, 29 (5), 2164 (2014)] [W. Saito et al., IEEE TED, 50 (12), 2528 (2003)]
19 Switching applications Small terminal capacitances Less reverse recovery charge Power loss is low [X. Huang, et al., IEEE TPEL, 29 (5), 2453 (2014)] 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 19
20 Modeling GaN! Modeling Strategy Existing Models 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 20 [L. Dunleavy et al., Microwave Magazine 11 (6), 82 (2010)]
21 Modeling Continued Angelov model Angelov Model Deficiencies Emperical model with ~ 90 parameters Fails to capture non-linear behaviour and harmonic accuracy in power circuits Challenging to use for multiple device dimensions 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 21 [I. Angelov et al., IEEE T-MTT, 44 (10), 1664 (1996)] [I. Angelov et al., IEEE T-MTT, 40 (12), 2258 (1992)]
22 Status of Compact Model GaN HEMT Compact Model GaN-HEMT Table-Based Empirical Physics Based Threshold- Voltage Based Surface- Potential Based Advanced SPICE Model for GaN HEMT device CMC candidate models for industry standardization (Two models are in final phase) ASM-HEMT model: Our model MIT Unified VS GaNFET (MVSG) model: MIT, Prof. D. Antoniadis 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 22
23 Advantages of SP-Based Model Better Model Scalability Device Insight Better Statistical Behavior Accurate Charges and Capacitances Better Temperature Scalability Less number of parameters Easier parameter extraction Uses a single expression for all regions Inherent Model Symmetry 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 23
24 ASM-HEMT Model Overview Analytical Solution of Schrӧdiger s & Poisson s 2-DEG Charge Fermi-level (Ef), Surface-potential (SP) SP-Based I d I g & ChargeModel Real Device effects included Accurate I-V and C-V Physical parameters DIBL, Rs, VS,... Noise Model, Trapping Effects Model, Self-Heating DC, AC, Transient Harmonic Simulations, Noise etc. 11/08/
25 ASM-HEMT Model Overview Core Model Analytical Solution of Schrӧdiger s & Poisson s 2-DEG Charge Fermi-level (Ef), Surface-potential (SP) SP-Based I d, I g & Charge Model 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 25
26 Surface-Potential Calculation Assumptions: Quasi-constant electric field in the potential well (triangular well approximation) Only the contribution of the first two sub-bands are important Quasi-Fermi-potential and SP Basic device equations are transcendental in nature We divide variation of E f with V g into regions to develop fully analytical expression Regional models are combined in one analytical expression No fitting parameters introduced, accuracy (order of nano-volts) 11/08/2017 S. Khandelwal, TED, VOL. 59, NO. 10, OCTOBER 2012 Yogesh S. Chauhan, IIT Kanpur 26
27 ASM-HEMT Model Overview CLM Mobility Degradation Temperature Dependence Bias Dependent Series Resistance Self-Heating Core Drain Current Model Complete Drain Current Model DIBL Velocity Saturation Sub-threshold Slope 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 27
28 Drain-Current Model and Intrinsic Charges We apply the drift-diffusion framework for carrier transport An analytical and continuous expression for the core drain-current is developed including the velocity-field relation and mobility degradation Core Drain Current Model: Ward-Dutton Partitioning for S/D charges Capacitances are calculated as derivatives of the terminal charges: C ij =-dq i /dv j (i j), C ii =dq i /dv i (i=j) Charge conservation ds Velocity-Field relation and mobility-degradation: L d s m 2 d s sat eff v sat 11/08/2017 is the CLM parameter Yogesh S. Chauhan, IIT Kanpur 28
29 Temperature Dependence 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 29
30 Model Parameter Extraction Set L, W, NF, Tbar Device Dimensions Obtain LAMBDA, Improve VSAT, ETA from IDVD Obtain VOFF, NF, CDSCD, ETA from log-idvg, LINEAR And Saturation Temperature Parameters Obtain U0, UA, UB and RDS from IDVG-LIN Capacitance Modeling Obtain VSAT, Improve ETA From LINEAR IDVG Model Implemented in Verilog-A Simulations performed in: ADS, Spectre, HSPICE 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 30
31 List of Main Parameters Physical Constants Simulation Conditions Device dimensions Physically-Linked Parameters Parameters U0 UA UB VOFF VSAT RTH DIBL LAMBDA VOFFT UTE RS RD.. Physical Meaning Low field Mobility Mobility degradation parameter Mobility degradation parameter Cut-off Voltage of Device Saturation Velocity Thermal Resistance DIBL effect parameter Channel length modulation Temperature dependence of Voff Mobility dependence of mu0 Source Side Resistance Drain Side Resistance.. 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 31
32 Importance of R d/s Model Aggressive lateral scaling of source-drain access regions improve the RF performance of GaN HEMT but at the cost of breakdown voltage (BV) Too short L gd increases electric field which is responsible for lowering of BV Scaling of L gd also affects the f max due to increasing C gd and g ds of device As a trade-off, ashortl gs and optimized L gd is required to achieve high f T,f max and BV altogether In GaN HEMT, gate-to-drain/source access region works as nonlinear resistance (R d/s )whichlimits maximum drain current Accurate model of R d/s is of great importance to predict the I d and g m for high power as well as high frequency GaN HEMTs 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 32
33 Nonlinear source/drain access region resistance model Fig. 1: Nonlinear variation of source/ drain access resistances with Ids extracted from TCAD simulation and comparison with model. 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 33
34 R d/s Model Validation with Measurement Effect of high access region resistance at high V g Fig. 2: I d V g and trans conductance for the Toshiba power HEMT. Different slopes above V off in g m V g : self heating governs the first slope while velocity saturation in access region affects second slope. Fig. 3: (a) Ids Vds, (b) g ds and (c) reverse Ids Vds fitting with experimental data. The non linear R s/d model shows correct behavior for the higher Vg curves in the Id Vd plot; the S P based model can accurately capture the reverse output characteristics. 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 34
35 Modeling of Temperature dependence The temperature dependence of R d/s model is extremely important as it increases significantly with increasing temperature Temperature dependence of 2-DEG charge density in the drain or source side access region: Temperature dependence of Saturation Velocity: Temperature dependence of electron Mobility: 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 35
36 Temperature Model Validation 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 36
37 Temperature Model Validation Id Vg at three different temperatures 300, 365 and 425 K RDS variation VSAT variation Mobility variation 11/08/2017 VOFF variation Yogesh S. Chauhan, IIT Kanpur 37
38 Temperature Model Validation Id-Vd at two different temperatures 300 and 573K RDS Temperature dependences VSAT variation Mobility variation VOFF variation 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 38
39 Model Validation IEMN France data Lg = µm, W=100 µm Lg = 0.35 μm 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 39
40 Modeling of Field-Plates in HEMTs Affects capacitance and breakdown behavior. 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 40
41 Field-Plate Capacitance Modeling 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 41
42 Cross Coupling Capacitance Both FPs Only GFP Appearance of fringing electric field between the vertical wall of the GFP and the 2-DEG SFP causes the cross-coupling effect giving rise to the second plateau Significant number of fringing field lines reach the GFP through the insulator stack in the absence of SFP causing more fringing capacitance Both FPs In the presence of the SFP, most of them end up at the SFP leading to a reduced fringing capacitance component in C gd 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 42
43 Substrate Capacitance Vgs = 7 V Vds = 20 V (a) Field lines originating from the 2-DEG reach the substrate electrode leading to the existence of C SUBD (b) whereas without substrate node, field lines from the drain side of the 2-DEG terminate at the 2-DEG on the source side through the GaN buffer 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 43
44 Current Collapse Stephen Sque - ESSDERC tutorial Sept /08/2017 Yogesh S. Chauhan, IIT Kanpur 44
45 Current Collapse [S. DasGupta et al., Appl. Phys. Lett. 101 (24), (2012)] Stephen Sque - ESSDERC tutorial Sept /08/2017 Yogesh S. Chauhan, IIT Kanpur 45
46 Issues-Virtual-gate effect [R. Vetury et al., Trans. Elec. Dev. 48 (3), 560 (2001)] Stephen Sque - ESSDERC tutorial Sept [T. Mizutani 11/08/2017 et al., TED 50, 2015 (2003)] Yogesh S. Chauhan, IIT Kanpur 46
47 Issues-Buffer trapping [E. Kohn et al., Trans. Microw. Theory Tech. 51 (2), 634 (2003)] Stephen Sque - ESSDERC tutorial Sept /08/2017 Yogesh S. Chauhan, IIT Kanpur 47
48 Pulsed IV Measurements Vgq, Vdq 0, 0 8, 0 Vgq, Vdq 8, 0 8, 20 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 48
49 Trap Model and Pulsed IV Scheme The trapping effects are modeled with the help of two R-C sub-circuits. The generated trap voltages V trap1 and V trap2 are fed back into the model which update parameters like the cut-off voltage, subthreshold slope, source and drain-resistances to capture the effects of traps. 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 49
50 Modeling of Trapping effect Traps in GaN HEMTs play huge role in determining the performance of the device, especially in high frequency operations 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 50
51 Switching Collapse Setup Signal generator at gate terminal switches device from high negative stress voltage (Vgsq) to some value higher than Voff. Variable resistor is used to make device working in linear region of operation. Waveform (i) is the input at the gate, which is switching the device from ON to OFF-state and vice versa. Waveform (ii) is the constant input applied at drain terminal via a variable resistor. Waveform (iii) is showing the output drain current with time. The drain current is kept fixed at 0.3A with the help of variable resistor. Waveform (iv) is the value of Vds which is equal to VDD when device is in OFF-state and becomes Von when device is in ON-state. Waveform (iv) illustrates the fact that, as the device is turning ON, capacitor assumed for the trapstates start to discharge and due to reduction in depletion of 2-DEG, Von of the device recovers with 11/08/2017 time. Yogesh S. Chauhan, IIT Kanpur 51
52 Switching Collapse Model Modeling of trapping effect by using RC network with different time constant. This RC network is contributing to drain-access region resistance as Rtrap (as a function of Vtrap) to capture the trapping effect on device ON-resistance (Ron) Model-Hardware correlation for pulsed I-V, Von data for 1, 5 and 10 khz input applied at gate terminal for various Vds. Von is the value of Vds at which the value of drain current is 0.3A. As VDD is increasing, Ron of the device increases which results in switching collapse. Measured data is from Toshiba for CMC standardization. 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 52
53 Toshiba DC I-V Results for High Power HEMT 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 53
54 Room Temperature I V Id (A) (m/s) / [E+0] Gds' (A/V2) (m/s) / [LOG] 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 54
55 Reverse room temperature 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 55
56 Room Temperature I V g m (ma/v 2 ) Id (A) g m (ma/v) 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 56
57 Log (Id) Vds (Vd>0) T=25 Log (Id) Vds (Vd<0) T=25 Id (A) Log (Id) Vgs T=25 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 57
58 I 20 deg C Id (A) 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 58
59 Rev T=150 C Vg from 12 to 3 0.5V step id (m/s) [LOG] / Lin Scale Log Scale 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 59
60 Rev T= 20 C Vg from 12 to 3 0.5V step Lin Scale Log Scale gds' (m/s) [E-3] / 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 60
61 I 20 deg C g m Id (ma) g m / / 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 61
62 I 20 deg C Log Scale Id (A) 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 62
63 I 100 deg C Id (ma) Id (ma) Id (ma) 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 63
64 Temperature Scaling Vd = 0.1, 0.5, 1 and 10V Id (ma) 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 64
65 DC I-V Results of Multifinger RF HEMT Lg = 125 nm, Wg = μm, Lsg = 200 nm, Ldg = 1.7 μm 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 65
66 DC Parameter Extraction Flow S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics based Multi bias RF Large Signal GaN HEMT Modeling and Parameter Extraction Flow", IEEE Journal of the Electron Devices Society, Sept /08/2017 Yogesh S. Chauhan, IIT Kanpur 66
67 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 67
68 12 RF Measurements S-Parameters Easy for high frequencies (hard to do open/short for Z/Y) Calculate other quantities Cascadable Transformation Compatibility with simulation tools VNA Architecture 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 68 [Advanced Design System, Design Guide]
69 13 De-embedding De-embedding : Negating effects of unwanted portion Real DUT SP= Measured SP Fixture Characteristic De-embedding is a mathematical process that removes the effects of unwanted embedded portions of the structure in the measured data by subtracting their contribution. 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 69 [De-embedding Techniques in Advanced Design System, Agilent Manual]
70 Device Layout and Manifolds 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 70
71 Equivalent Circuit Model at RF 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 71
72 Small Signal Modeling C gs C gd g m g ds 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 72 S. A. Ahsan,..,Y. S. Chauhan, IEEE Journal of the Electron Devices Society, Sept
73 Impact of Gate Resistance Large resistors R gs and R gd Capture the differential gate resistance for current flowing through the gate-source and gate-drain Schottky diodes. Their inclusion significantly impacts the overall gate resistance (R g ) at low frequencies as shown in Fig. R sub and C sub Capture the substrate loss at the output port. Total R g 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 73
74 S-Parameters Frequency: GHz 2 different drainbias conditions, with 10 different gate biases (Id = ma/mm) Lines Model Symbols Measured Data 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 74
75 Y-Parameters The peaks and dips and their bias dependence is a manifestation of the interaction between the intrinsic capacitances and the extrinsic inductances. The values of bus-inductances can be fine-tuned to fit the peaks/dips in measured and modeled extrinsic-level Y- parameters. 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 75
76 RF Parameter Extraction Flow 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 76
77 16 Power Amplifier Design Goals 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 77
78 17 Load Pull Technique Helps us: Determine Optimum load impedance for maximum Pout and PAE performance Matching networks Understand tradeoffs! 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 78 [M. S. Hashmi et. al, IEEE Instrum. Meas. Mag., 16 (2), Feb., (2013)]
79 Load-Pull Schematic & Overlays 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 79 S. A. Ahsan, et. al, IEEE Trans. Microwave Theory Tech, 2017.
80 Load Pull Contours 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 80
81 Harmonic Balance Power Sweeps 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 81 S. A. Ahsan, et. al, IEEE Trans. Microwave Theory Tech, 2017.
82 Model Quality 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 82
83 Toshiba device Id and derivatives ID ID = GX Smooth and continuous Id and its derivatives ID = GX ID =GX Full device (simulation) 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 83
84 Toshiba device Intrinsic device (simulation) Intrinsic device passes Gummel Symmetry Test 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 84
85 Characterization and Parameter Extraction for RFMD RF 3931 Device (Devices received from ISRO) 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 85
86 Summary Physics-based fully analytical model for the GaN HEMTs Excellent agreement with the measured data at different temperatures for different channel length devices Model is implemented in the Verilog - A code Tested on Agilent ADS, Synopsys HSPICE and Cadence s Spectre simulators In final phase of industry standardization at CMC 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 86
87 My Group and Nanolab Current members 30 Postdoc 5 Ph.D. 17 Three PhD graduated Postdocs in UC Berkeley and U. Bordeaux France Books 1 1 Journal Conference Funding in last 5 years: > Rs. 8.5 Crore Device Characterization Lab Pulsed IV/RF PNA X 43.5GHz High Power IV 11/08/2017 Yogesh S. Chauhan, IIT Kanpur 87
88 GaN-HEMT Journal Publications 1. S. A. Ahsan, A. Pampori, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "A New Small-signal Parameter Extraction Technique for large gate-periphery GaN HEMTs", in IEEE Microwave and Wireless Components Letters, Vol. 27, Issue 10, Oct S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics-based Multi-bias RF Large-Signal GaN HEMT Modeling and Parameter Extraction Flow", in IEEE Journal of the Electron Devices Society, Vol. 5, Issue 5, Sept S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Pole-Zero Approach to Analyze and Model the Kink in Gain-Frequency Plot of GaN HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 27, Issue 3, Mar S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Cross-Coupling and Substrate Capacitance in GaN HEMTs for Power-Electronic Applications", IEEE Transactions on Electron Devices (Special Issue), Vol. 64, Issue 3, Mar A. Dasgupta and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise in HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 26, Issue 6, June S. A. Ahsan, S. Ghosh, A. Dasgupta, K. Sharma, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling in Dual Field Plate Power GaN HEMT for Accurate Switching Behaviour", IEEE Transactions on Electron Devices, Vol. 63, Issue 2, Feb A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Surface potential based Modeling of Thermal Noise for HEMT circuit simulation", IEEE Microwave and Wireless Components Letters, Vol. 25, Issue 6, June S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2, Feb A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Compact Modeling of Flicker Noise in HEMTs", IEEE Journal of Electron Devices Society, Vol. 2, Issue 6, Nov S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance and T. A. Fjeldly, "A Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design", IEEE Transactions on Electron Devices, Vol. 60, Issue 10, Oct S. Khandelwal, Y. S. Chauhan, and T. A. Fjeldly, "Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices", IEEE Transactions on Electron Devices, Vol 59, Issue 8, Oct /08/2017 Yogesh S. Chauhan, IIT Kanpur 88
89 GaN-HEMT Conference Publications 1. S. Khandelwal, S. Ghosh, S. A. Ahsan and Y. S. Chauhan, "Dependence of GaN HEMT AM/AM and AM/PM Non-Linearity on AlGaN Barrier Layer Thickness", IEEE Asia Pacific Microwave Conference (APMC), Kuala Lumpur, Malaysia, Nov S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Surface-potential-based Gate-periphery-scalable Small-signal Model for GaN HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), Miami, USA, Oct S. Ghosh, S. A. Ahsan, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "GaN HEMT Modeling for Power and RF Applications using ASM-HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec S. Ghosh, A. Dasgupta, A. K. Dutta, S. Khandelwal, and Y. S. Chauhan, "Physics based Modeling of Gate Current including Fowler-Nordheim Tunneling in GaN HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Statistical Simulation for GaN HEMT Large Signal RF performance using a Physics-based Model", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, N. Defrance, and Y. S. Chauhan, "Modeling DC, RF and Noise behavior of GaN HEMTs using ASM-HEMT Compact Model", IEEE International Microwave and RF Conference (IMaRC), Delhi, India, Dec S. A. Ahsan, S. Ghosh, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Advanced SPICE Model for Gallium Nitride High Electron Mobility Transistors", International Conference of Young Researchers on Advanced Materials (ICYRAM), Bangalore, India, Dec S. Ghosh, S. A. Ahsan, S. Khandelwal and Y. S. Chauhan, "Modeling of Source/Drain Access Resistances and their Temperature Dependence in GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Modeling of Kink-Effect in RF Behaviour of GaN HEMTs using ASM-HEMT Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug R. Nune, A. Anurag, S. Anand and Y. S. Chauhan, "Comparative Analysis of Power Density in Si MOSFET and GaN HEMT based Flyback Converters", IEEE International Conference on Compatibility and Power Electronics, Bydgoszcz, Poland, June S. Agnihotri, S. Ghosh, A. Dasgupta, A. Ahsan, S. Khandewal, and Y. S. Chauhan, "Modeling of Trapping Effects in GaN HEMTs", IEEE India Conference (INDICON), New Delhi, India, Dec S. Ghosh, S. Agnihotri, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Trapping Effects in RF GaN HEMTs under Pulsed Conditions", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec S. Agnihotri, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Impact of Gate Field Plate on DC, C-V, and Transient Characteristics of Gallium Nitride HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec K. Sharma, S. Ghosh, A. Dasgupta, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Capacitance Analysis of Field Plated GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec S. A. Ahsan, S. Ghosh, J. Bandarupalli, S. Khandelwal, and Y. S. Chauhan, "Physics based large signal modeling for RF performance of GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec S. Khandelwal, S. Ghosh, Y. S. Chauhan, B. Iniguez, T. A. Fjeldly and C. Hu, "Surface-Potential-Based RF Large Signal Model for Gallium Nitride HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), New Orleans, USA, Oct S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. 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