Solution Manual for Modern Digital Electronics

Transcription

1 Solution Manual for Modern Digital Electronics Third Edition R P Jain

2 HPTER. (a) nalog. The output of a pressure gauge is proportional to the pressure being measured and can assume any value in the given range. (b) Digital. n electric pulse is produced for every person entering the exhibition using a photoelectric device. These pulses are counted using a digital circuit. (c) nalog. The reading of the thermometer is proportional to the temperature being measured and can assume any value in the given range. (d) Digital. Inputs are given with the help of switches, which are converted into digital signals and corresponding to the switch in the ON or OFF position. These signals are processed using digital circuits and the results are displayed using digital display devices. (e) nalog. It receives modulated signals which are analog in nature. These signals are processed by analog circuits and the output is again in the analog form. (f) Digital. It has only two possible positions (states), ON and OFF. (g) Digital. n electric pulse is produced for every vote cast by pressing of switch of a candidate. The pulses thus produced for each candidate are counted separately and also the total number of votes polled are counted..2 (a) (i) S S 2 ulb (ii) S S 2 ulb OFF OFF OFF OFF OFF OFF OFF ON OFF OFF ON ON ON OFF OFF ON OFF ON ON ON ON ON ON ON (iii) S ulb (iv) S S 2 ulb (b) OFF ON OFF OFF OFF ON OFF OFF ON ON ON OFF ON ON ON OFF (i) S S 2 ulb (ii) S S 2 ulb (iii) S ulb (iv) S S 2 ulb (c) (i) ND (ii) OR (iii) NOT (iv) EX-OR

3 .3 Input t(ms) Input t(ms) ND OR NND NOR EX-OR.4 Inputs Outputs of (a) (b) (c) (d) The operations performed are (a) NOR (b) NND (c) ND (d) OR 2

4 .5 For Fig..6 (a) Y (b) Y (c) Y For Fig..8 (a) Y (b) + Y (c) Y.6 (a) NND, NOR (b) ND (c) NND (d) OR.7 (a) Inputs Output Y (b) EX OR (c) Y 3

5 (d) Y = + \ Y = + = Y = Y = = Y Y 2 where, Y = and Y 2 = Y Y Y 2.8 For simplicity, we shall consider 2-input gates, but the results are equally valid for any number of inputs. In the positive logic system, the higher of the two voltages is designated as and the lower voltage as. On the other hand in the negative logic system, the lower of the two voltage is designated as and the higher voltage as. Therefore, if s and s are interchanged, the logic system will change from positive to negative and vice-versa. (a) In the truth table of positive logic ND gate replace all zeros by ones and all ones by zeros. The resulting truth table is same as that of the OR gate. Similarly, if all ones and zeros are interchanged in the truth table of the OR gate, the resulting truth table will be same as that of the ND gate. (b) Repeat part (a) for NND and NOR gates..9 (a) + + = ( + ) + = ( + ) + = + = + = ( + ) ( + ) = + (b) + + = ( + ) + = + = ( + ) ( + ) = + (c) = + + ( + ) = + + = + ( + ) = + ( + ) ( + ) 4

6 = + + = ( + ) +. (a) = ( + ) ( + ) + = ( + ) + = (b) (c) LHS RHS. (a) The realization of LHS requires, two inverters, two 2-input ND gates, and one 3-input OR gate, whereas the realization of RHS requires only one two input OR gate. (i) (ii) 5

7 (b) The realization of LHS requires two inverters, three 2-input ND gates and one 3-input OR gate, whereas the realization of RHS requires only one inverter and one 2-input OR gate. (i) (ii) (c) The realization of LHS requires three inverters, four 3-input ND gates and one 4-input OR gate, whereas the realization of RHS requires only three 2-input ND gates and one 3-input OR gate. (i) (ii).2 (a) + D = + D = D 6

8 (b) ( + ) ( + D) = ( + ) ( + D).3 (a) = ( + ) + ( + D) (i) The left hand side of (a) can be realized by using two 2-input ND gates followed by one 2-input OR gate, while the right hand side is realizable by two 2-input NND gates followed by another 2-input NND gate. Hence an ND-OR configuration is equivalent to a NND- NND configuration. (ii) The left hand side of (b) is realizable by two 2-input OR gates followed by a 2-input ND gate, while the right hand side is realizable by two 2-input NOR gates followed by another 2-input NOR gate. Hence an OR-ND configuration is equivalent to a NOR-NOR configuration. Y Y D D (b) (i) (ii) Y Y D D (i) (ii).4 (a) Since = Therefore, the ND operation is commutative. If ( ) = ( ), then the ND operation is associative. This can be proved by making truth table as given below: ( ) ( ) 7

9 Since the last two columns of the truth table are identical, which proves that the ND operation is associative. (b) Since, + = +, therefore, OR operation is commutative. The associative property requires + ( + ) = ( + ) + which can be proved by making the truth table in a way similar to the truthtable of (a) above (c) Since, Å = Å, which means the EX-OR operation is commutative. The associative property requires ( Å ) Å = Å ( Å ) This can be proved by making truth table.5 (a) Since = =, therefore, the NND operation is commutative. To verify whether the NND operation is associative or not, we prepare the truth table as given below. From the Table we observe that the last two columns are not identical, which means ( ) ( ) This shows that the NND operation is not associative. ( ) ( ) (b) Since, + = +, which means the NOR operation is commutative. y making a truth table similar to the truth table of (a) above we can verify that ( + ) + + ( + ) Therefore, the NOR operation is not associative..6 Two possible realizations are given on page 9:.7 (i) If only one of the variables is and all others are zero, then ( Å ) Å Å Å... = Å Å Å... = Å = (ii) If only two of the variables are and all others are zero, then (since EX- OR operation is commutative and associative) ( Å ) Å Å Å Å... = Å Å Å Å... = (iii) Similarly, if only three of the variables are, then ( Å ) Å Å Å Å... = Å Å Å Å Å... = 8

10 Å Å Å D D or Å Å D Fig..7 Y Å Å Å D Y Å Å Å D In the same way we can try higher number of ones. It is obvious from the above discussion that Z =, if an odd number of variables are and Z = if an even number of variables are..8 Since a logical variable can assume one of the two values ( or ) the number of possible combinations is 2 N. Take an N-bit binary number b N b N 2... b 2 b b and write all combinations from... to... in normal binary ascending order..9 (a) 742 is a quad 2-input NOR gate. This means there are four identical 2-input NOR gates. Each gate requires three pins, two for inputs and one for output. Therefore, the four gates requires 3 4 = 2 pins. Two pins are required for the power supply (V and GND). Hence it is a 4-pin I. (b) 744 is a hex inverter. The number of pins = = 4. (c) 748 is a quad 2-input ND gate. The number of pins = = 4. (d) 74 is a triple 3-input NND gate. The number of pins = = 4. (e) 74 is a triple 3-input ND gate. The number of pins = = 4. (f) 742 is a dual 4-input NND gate. The number of pins = = 2. Since 2-pin I package is not used, therefore, it is packaged as 4-pin I. Two pins are left free (N). (g) 7427 is a triple 3-input NOR gate. The number of pins = = 4. (h) 7432 is a quad 2-input OR gate. The number of pins = = 4. 9

11 (i) 7486 is a quad EX-OR gate. The number of pins = = 4..2 (a) (i) 748 and 7432 (ii) 74 (b) (i) 7432 and 748 (ii) Logic ircuit.4v = 2V = Logic ircuit.75v =.55V =.22 Inputs Output ND OR NND NOR Y Y 2 Y 3 Y 4.23 Yes. (a) Y or Y (b) Y or Logic Y (c) Y or Logic Y (d) Y or Logic Y Logic

12 .24 Yes. ND by connecting one of the inputs to logic OR by connecting one of the inputs to logic NND by connecting one of the inputs to logic NOR by connecting one of the inputs to logic..25 (a) ctive-high (b) ctive-low (c) ctive-high (d) ctive-low.26 (a) ctive-low (b) ctive-high (c) ctive-low (d) ctive-high.27 (a) Y (b) Y = = ( ) () Y Y = + + = ( + ) + () (c) Y Y = = ( ) + (d) = ( ) = Y

13 .28 (a) Å = + Å = + (b) = + = Å = + Å = + = + Å = + = + (c) Å ( Å ) = Å Å = Å = 2

14 HPTER 2 2. (a) = = = (57) (b) = = = (4) (c) = = = (254) (d) = = () (e). = = = (3.875) (f). = = (.625) (g). = = (.875) 2.2 (a) Quotient Remainder Thus (37) = () 2 Similarly, (b) (255) = () 2 (c) (5) = () 2 3

15 (d) Integer part: (26) = () 2 Fractional part: Therefore, (26.25) = (.) 2 (e) Integer part: () = () 2 Fractional part: Thus (.75) = (.) 2 (f) Thus, (.) 2 = (.) 2 The process may be terminated at the required number of significant bits. 2.3 (a) arry + Final carry (b) arry. +.. Final carry 2.4 (a) + (2 s complement) Since the MS of the sum is, which means the result is negative and it is in 2 s complement form. 2 s complement of = = () Therefore, the result is. 4

16 (b) Þ + (2 s complement) = + 9 Ignore (c). Þ.. +. (2 s complement). = Ignore 2.5 (a) Quotient Remainder Therefore, (375) = (567) 8 = () 2 (b) Quotient Remainder Therefore, (249) = (37) 8 = () 2 (c) Integer part: (27) = (33) 8 = () 2 Fractional part: Thus (.25) = (.) 8 = (.) 2 Therefore, (27.25) = (33.) 8 = (.) (a). = (334.52) 8 (334.52) 8 = = ( ) (b). = (23.25) 8 = ( ) (c) = (263) 8 = (79) 5

17 2.7 (a) Quotient Remainder Therefore, (375) = (77) 6 (or 77H) = ( ) 2 (b) Quotient Remainder F 9 Therefore, (249) = (F9) 6 (or F9H) = ( ) 2 (c) Integer part: Quotient Remainder Thus (27) = H Fractional part: \ (.25) =.2H \ (27.25) = (.2) 6 =.2H = (.) (a). = (D.8) 6 (D.8) 6 = = ( ) (b). = (53.54) 6 = ( ) (c) = (3) 6 = (79) 2.9 For each decimal digit write its natural D code (a) 46 = (D) (b) =. (D) (c) 2.35 =. (D) 2. For each decimal digit write its 4-bit Excess-3 code. (a) 46 = (Excess-3) (b) =. (Excess-3) (c) 2.35 =. (Excess-3) 6

18 2. Starting from 4-bit Gray code given in Table 2.8 formulate 5-bit Gray code as given below in Table. Table Table 2 Decimal G 4 G 3 G 2 G G Decimal G 5 G 4 G 3 G 2 G G No. No. 2 2 : : : 3 : : : : : : : : : : : Similarly, form 6-bit Gray ode as given in Table 2. From Table 2, we obtain (46) = (Gray ode) 2.2 Writing the 6-bit code for each character (See Table 2.9), we obtain 2.3 (a) Write the 7-bit SII code for each character (See Table 2.) R.P. JIN = (b) Write the 8-bit EDI code for each character (See Table 2.9) R.P. JIN = (c) Write the 6-bit internal code for each character (See Table 2.9) R.P. JIN = 2.4 (a) ount the number of ones for every character from SII table and attach a or as the MS for odd or even number of ones respectively. For example, the SII code for R is, which has three ones. Therefore, a is to be attached as MS and the resulting 8-bit code with even parity will be Similarly, the code for l is which has four ones. Therefore, a is to be attached as MS and the resulting 8-bit code with even parity will be. 7

19 In a similar way parity bit can be attached to every character. (b) Repeat part (a) for EDI code. 2.5 (a) ttach or as MS to make the number of ones odd. For example, 8-bit SII code for R with odd parity is (b) Repeat part (a) for EDI code. 2.6 (a) Since, 2 5 = 32 and 2 6 = 64, therefore, the minimum number of bits required to encode 56 elements of information is 6. (b) 2 7 < 3 < 2 8 Therefore, 8 bits are required to encode 3 elements of information. 2.7 In the 8 bit SII code with the parity bit, if binary to hexadecimal conversion is used, the resulting format will be hexadecimal. For example, R = = D2 H and l = = 2EH for even parity and R = = 52H and l = = EH for odd parity. 2.8 onsider the following examples: (i) 7 Þ 3 + ( s complement) 4 End-round arry (E) = 4 (ii) 3 Þ 7 + ( s complement) 4 = 4 in s complement form From the above examples the rules of subtraction can be summarized as: (a) dd ones complement of the subtrahend to the minuend. (b) If a carry is produced, add end-around carry (E) (c) If the MS of the sum is, the result is positive (d) If the MS of the sum is, the result is negative and it is in one s complement format bits bits. 2.2 Let us consider the D code for 9 and find out its Hamming code for error correction. Hamming ode Decimal Position digit p p 2 n p 3 n 2 n 3 n 4 9 D : : : : : : : : : : odd parity for : : : : : : :,3,5,7 requires p = : : odd parity for 2,3,6,7 : : : : : : : requires p 2 = : odd parity for 4,5,6,7 : : : : : : : requires p 3 = 8

20 Therefore, Hamming code for decimal digit 9 is. Similarly, Hamming code is determined for each D digit and the complete sequence is given below. Hamming code Decimal Position digit p p 2 n p 3 n 2 n 3 n

21 HPTER 3 3. (a) The number of covalent bonds breaking away increases with temperature, which decreases the resistivity of the semiconductor material, whereas in a metal an increase in the temperature results in a greater thermal motion of the ions, and hence decreases the mean free path of the free electrons. This results in a decrease in the mobility and hence resistivity increases with temperature. (b) ll the covalent bonds are intact at K and hence there are no free charge carriers, whereas at room temperature some of the covalent bonds break away resulting in small conductivity. 3.2 (a) Using the V-I relation of the diode, we obtain I» I exp (V /hv T ) (3.) and I 2 = 2I» I exp (V 2 /hv T ) (3.2) From Eqs. (3.) and (3.2), 2 = exp (V 2 V /hv T ) or V 2 V = hv T n 2 = mv» 36 mv (b) Since, V = 7 mv Therefore, V 2 = = 736 mv Percentage change = % 7 = 5.4% 3.3 From the V I relation of the diode, we obtain I» I exp (7/hV T ) and I 2» I exp (75/hV T ) \ I 2 /I = exp (5/2 26) = 2.66 or I 2 = = m (b) Percent change = % 2 = 6.6% 3.4 I 2 I = = e {(V 2 V )/2 26} or V 2 V = 52 n = 9.73 mv 3.5 (a) The circuit will be under steady-state at t = 2ms, i.e., dq dt = 2

22 I V R = = m Since, Q t = I \ Q = 6 3 = 9 (b) The diode will turn off when excess minority charge has been removed. VR I R = 5 = R The differential equation is dq dt 5. m Q + = 5. τ 3 Solving this with initial condition Q() = 9 (part (a)), we obtain Q = e t Set Q = for cut-off \ t =.99 ms (c) The various waveforms are given below. The recovery time constant t R = R O = 3 2 =. ms V i V = V -V 2 = -5V t V d.7v -5V t R t I d m -.5 m t R t Excess Minority harge Q t.99 ms 2 t

23 3.6 (a) Since the E- junction is forward-biased, therefore, the transistor is conducting (i.e., I is flowing). It may either be operating in the active region or in the saturation region. Let us assume that the transistor is operating in the saturation region. Then the base and collector voltages will be V E, sat (=.8 V) and V E, sat (=. V) respectively. Therefore, the collector current I and the base current I are given by V I = V R = = 333. m 3 E, sat. V and I = V R 5 8 = = 2 µ 2 E, sat. h FE I = 2 = 2. m Since I >h FE I, therefore the transistor cannot be in saturation. Hence it is conducting in the active region. with V = 6V, let us again assume that the transistor is operating in the saturation region. Therefore, 6 I =. 2 m 3 The current I remains same as in part (a). Therefore, now I < h FE I which means the transistor is certainly operating in the saturation region. (b) The value of R required for the transistor to be in saturation is given by V V R E,sat h FE I or R. kw 2. ³ 4.7 kw \ The value of R c just sufficient for saturation will be 4.7 kw. If the value of R used is more than 4.7kW, the transistor will continue to be operating in the saturation region. (c) The value of R required to drive the transistor into saturation is given by V VE,sat I hfe R or R 5. 8 kw kw 22

24 The value of R just sufficient to drive the transistor into saturation will be kw. If a smaller value of R than the value calculated above is used, the transistor will be driven deeper into saturation. 3.7 (a) For the transistor to be in the cut-off region, the voltage V V E, cut in.5 V (b) For active region operation V E V R V V E, sat E, sat R h FE R V or, V < R V h FE E, sat + V E, sat 5. < < 3.25 V Therefore, the range of V for active region is.5 V < V < 3.25 V (c) The range of V for saturation region is V ³ 3.25 V 3.8 For the transistor to be in saturation V V R E,sat V V R E,sat h FE or, h FE (min) = R R V V V V E, sat E, sat = = ssume the transistor to be in saturation. Writing KVL equations for the collector and base circuits, R I + V E, sat + R E (I + I ) = V and R I + V E, sat + R E (I + I ) = V Substituting the values, we obtain, 53 I + 5 I =

25 and 5 I + I = 4.2 Solving these equations, I =.96 m and I = 6.24 m Since I comes out to be negative, hence the transistor is not in saturation. ssuming V E =.7 V in the active region, KVL for the base circuit will be [R + ( + h FE ) R E ] I = 5.7 or, I = m \ I = h FE I = m and I E» m 3. The equivalent circuit at the input of a transistor consists of input resistance R i in parallel with the input capacitance i as shown in Fig. given below: + V i R R i i Equivalent circuit at the transistor input When fast changes occur in V i, the voltages at change with the time constant i (R R i ) If a capacitor is connected across R, the voltage at will change as soon as V i changes because of the capacitive voltage divider. This helps in improving the switching speed of transistor circuit. 3. (a) For the load transistors 5V I,sat = = 2.5 m 2kW 25. m I,sat = = 25. µ \ The minimum value of V i required for the load transistors to be in saturation is V i(min) = =.5 V 24

26 (b) ssuming the load transistors to be in saturation the equivalent circuit at their input will be as shown in Fig. (a), which reduces to the circuit shown in Fig. (b). Now, the voltage V i = V O can be determined using the principle of superposition and is given by 5 2 V i = V O = = 3.8 V kw V i kw.8 V V i 5 kw.8 V.8 V (a) (b) (c) The base current I = I 2 = m =.3 m 3.2(a) When both the transistors are cut-off, there is no current drawn from the supplies, and the voltage at Y is 5 V. (b) When both the transistors are in saturation, the voltage at Y is V. (c) ssume T to be cut-off and T 2 to be in saturation. Since T 2 is in saturation, the voltage at Y will be V. The currents I and I 2 will be same æ V = ö ç è R ø and I 2 = I + I 2. Similarly, if T is in saturation and T 2 is cut-off then I = I + I 2 (d) V V 2 Y V V 5V V 5V V 5V V V 5V 5V V It performs NOR operation. 3.3 (a) ssume the transistor to be in saturation. Therefore, I = 5 5 = =. 8 5m, I =. 42 m h FE I = 5.42 = 6.3 m Since I < h FE I, therefore, the transistor is definitely in saturation. 25

27 (b) When S is closed, I = (5.7/4) =.75 m assuming the transistor to be in saturation. Therefore, I = I + I Since = = 6.75 m I < h FE I Therefore, the transistor continues to remain in saturation. (c) When both S and S 2 are closed, if we again assume the transistor to be in saturation, I = I + I + I 2 Now = = 7.5 I <h FE I Which means the transistor no longer remains in saturation. Therefore, it is conducting in the active region. 3.4 The base current required for each transistor to be in saturation is 25m. Therefore, total base current will be 25 m. If this current flows through R of driver, the voltage at its collector will be V O = = Which shows that it is not possible to have a base current of 25 m for each of the load transistor. Hence, the load transistors will not remain in saturation. 3.5 Let T be cut-off. Therefore, the circuit will be as shown below: V V R R T T 2 Now, the total resistance in the collector circuit of T 2 is R R = R /2 which means its collector current increases. This requires the base current to be doubled for the transistor to remain in saturation. Therefore, the transistor will be operating in the active region. 3.6 The effective resistance = R R = R 2 26

28 R Therefore, the time constant = O (a) Since V GS =, therefore, the V DS V S I D characteristic will be same as the characteristic for V GS = in Fig. 3.4(b). (b) Transistor T 2 acts as load for T, the v-i characteristic of the load is that of part (a). Since the current I D is same in both T and T 2, therefore, for a given value of I D, the voltage. V DS = V DD V DS2 Take various values of I D and for each I D determine V DS2 from the curve of (a). alculate V DS and locate a point corresponding to V DS, I D on the characteristic of Fig Thus, we get a load curve as shown below. From this we see that when V i =, V O = 5V and V i = 5V, V O» V Therefore, the circuit functions as an inverter. I D, m Load curve V GS = 5 V 4 V 3 V 2 V V 5 V DS, V 27

29 HPTER 4 4. When the output of the driver gate is high, the load gates are in saturation and T and T 2 are cut-off. Therefore, V O =.4V. The current drawn from the supply, I V = V R O = = m 64 when the output of the driver is low, T and/or T 2 are in saturation and V O =.2V. The current drawn from the supply I 2 = = m 64 I verage current = I = av = m + I = 2 verage Power drawn from the supply = V I av = mw = 6.48 mw 4.2 (a) & (b) h FE = h FE = 2 N V O Noise Margin V O Noise Margin D D <.4 Load gate transistors not in saturation < < The voltage V O and noise margin D are given in Table. (c) Fan out and noise margin increases with increase in h FE. (d) For h FE =, if N > 7, the load gate transistors come out of saturation. The value of noise margin decreases with increased N. 4.3 (a) Let us consider all the possible cases: ase I = = = D =. Therefore, all the transistors T, T, T, and T D are cut-off, hence Y = Y = Y 2 = orresponding to this, each gate will be able to drive 5 gates. Therefore, the fan-out of this combination will be. lternatively, we can consider 28

30 equivalent collector resistance R = R R = R / 2, which means the base current of load transistors can flow through R and give same output voltage corresponding to logic as the output voltage of each gate individually while driving 5 load gates. ase II t least one of the inputs of each gate P and Q are HIGH. This will drive the corresponding transistors into saturation and consequently Y = Y = Y 2 will be LOW and hence the load transistors will be cut-off. Therefore, there is no problem of fan-out. ase III t least one of the inputs to gate P is HIGH and = D =. The transistor whose input is HIGH will be driven to saturation forcing the output voltage to LOW. onsequently, Y = Y = Y 2 will be LOW and this situation is similar to that of ase II. ase IV = = and at least one of the inputs to gate Q is LOW. This will lead to a situation similar to that of ase III. Therefore, the fan-out is. (b) Without load gates, the propagation delay time-constant R = 2 2 = R O O which is same as the propagation delay time-constant of a single gate. With load gates, the propagation delay time-constant for a single driver (without wired-logic) is æ R ö ç R + O + Ni è N ø ( ) where, N is the number of load gates. R is the resistance in the base circuit of a load gate. i is the input capacitance of a load gate. With wire-nding, the timeconstant will be æ R R ö ç + + è 2 O N ø ( 2 N ) When the output is high, the current drawn from the supply is I H = m (see Prob. 4.) Similarly, for low output I L = m \ I av = 9.56 m Power drawn from the supply = mw = mw 4.4 (a) This circuit has active pull-up (consisting of T 2 and W resistor) instead of passive pull-up R used in normal RTL gates. The state of transistor T 2 i 29

31 will always be opposite to that of T 3, i.e., if T 3 is cut-off, T 2 is in saturation (since T is cut-off) and vice-versa. Therefore, when the input V i is HIGH, T 3 will be in saturation, while T 2 is cut-off and V O = V E,sat» V. When V i is LOW, T 2 is in saturation and T 3 is cut-off. The output voltage V O will be HIGH. (b) If it is driving N load gates, the output circuit corresponding to HIGH state will be as shown in Fig. Prob. 4.4(a). V (3.6 V) 64 W W 45 W T 2 I I O P 45 W/N V E, sat».8 V Equivalent input circuit of load gates Fig. Prob. 4.4(a) V V sat V I O = + 45/ N E, E, sat = + 45/N = / N Writing KVL for the closed path P, we obtain V 9 I V E, sat 45 N I O V E, sat = é 45 æ 2.6 öù or I = ê ç ú è + 45/ êë N Nøúû For T 2 to be in saturation h FE.I ³ I O 3 é 45 æ 2.6 öù 2.6 \ ê2-9 ç ³ 45/ ú êë N è + Nøúû + 45/ N From the above equation, we obtain N ³ 2.5. Therefore, N ³ 3 since N is an integer. 3

32 Since, I = I 2 =... = I N. Therefore, I 26. O = = + 45/ N N I The values of I for various values of N are given in Table Table N I (m) The base current required for saturation for a normal RTL is about 3 m, which means N can be taken as 7, which is very large. (c) The relevant portion of the circuit is shown in Fig. Prob. 4.4(b). Here T 3 and T 2 are in saturation, whereas T 2 and T 3 are cut-off. Neglecting the base currents I E2 = I 3 = = 32 m V = 3.6 V W W T 2 T 2 I E2 T 3 I 3 = = T 3 Fig. Prob. 4.4(b) 4.5 (a) When all the inputs are HIGH the voltage at the point P will be V p = =.5 volts I = = 7. m 5 and I =.7.6 =.54 m This will increase the fan-out to 7, but the noise margin D will be reduced from.8 V to.2 V. 3

33 (b) In this case V P = = 2.9 V \ I =.42 m, and I =.26 m This will reduce the fan-out to 6, but the noise margin D will be increased to.4 V. 4.6 For a fan-out of, = h FE.4 or h FE» The Fig. Prob. 4.7 shows the relevant portion of the circuit. The worst condition corresponds to the situation when the output transistor of one of the driving gates is in saturation and all others are cut-off. orresponding to this the output voltage at Y is V E,sat».2 V, which means the input diodes of all the load gates driven from this combination are conducting. ssuming all the other inputs of load gates to be HIGH. I L =.82 m ssuming T to be in saturation, the collector current of T is given by, N I L + MI where, N is the fan-out with the wire-nded connection. This collector current must be same as the collector current of the single gate driving N gates which is given by NI L + I \ NI L + I = N I L + MI V (5 V) V (5 V) I R Y Y I L R T P V R I Y 2 I L V R T 2 P 2 V V R I I L R Y M T M P N M Gates wire-nded Fig. Prob. 4.7 N Load gates 32

34 or N = N (M ) I /I L = N (M ) = N 2.66 (M ) 4.8 When all the inputs are HIGH, the input diodes are non-conducting. If we assume that the transistor T is in saturation, then V P = V E, sat + V D + V E, sat = = 2.3 V The voltage at the collector of T = V E, sat + V D + V E, sat = =.7 V Since the voltage at P is higher than the voltage at the collector of T, I cannot exist, therefore, the assumption that T is in saturation is inconsistent. Hence T is in active region. In fact when T is conducting, the voltage drop across R 2 will reverse-bias the - junction of T and therefore T will definitely be operating in active region. 4.9 If any input is LOW, the corresponding input diode conducts and therefore, V P =.9 V, which keeps T, D 2, and T 2 cut-off. Hence Y =. If all the inputs are HIGH, the input diodes will be nonconducting. T will be in active region and T 2 in saturation region. Hence Y =. This shows that the circuit operates as a NND gate. (a) When all the inputs are HIGH, V P = V E + V D + V E3, sat = = 2.2 V Here, V E has been assumed to be.7 V in active region. Therefore, lso V V P = R I + R 2 I I = ( + h FE ) I I = = µ. and I =.543 m, I 2 = V E2, sat =.6 m, 5 I 2 = I I 2 = =.383 m V V V Standard load = R + R D E,sat 2 5 = =. 93 m V \ I 2 = N I + L V R E, sat =. 93 N

35 For T 2 to be in saturation, I 2 h FE I 2 or,.93 N or, N < 36 Therefore, the fan-out of this gate is 35 which is much higher than the fanout of the DTL gate of Fig (b) Noise margins D = =.7 V D = V() + (V P V Dg ) = 5 + (2.2.6) = 3.4 V (c) When the output is LOW, the power P () = (I + I ) V = ( ) 5 = mw When the output is HIGH, the power P () = I V cc =.93 5 = mw P( ) + P( ) The average power P av = = = mw 2 4. (a) When at least one of the inputs is LOW, V P = V () + V D = =.9 V orresponding to this T and T 2 will be nonconducting. When all the inputs are HIGH, T will be conducting in active region, Zener will be in the breakdown region and T 2 in saturation. Therefore, V P = V E, active + V Z + V E, sat = = 8.4 V The level noise margin = D = V g + V Z + V g V P = = 7 V The level noise margin = D = [V () (V P V Dg )] = [5 (8.4.6)] = 7.2 V (b) When all the inputs are HIGH, V P = 8.4 V. Writing KVL from V to V P, V V P = R ( + h FE ) I + R 2 I 34

36 V VP or, I = R ( + h ) + R FE = 3( 4) + 2 =.489 m The current through Zener diode, I = = 2.4 m \ I 2 = I I 2 = =.844 m The current through R 4. 8 = = m 5 The load current I L =.95 m \ I 2 = N or, N 76 (c) P() = (I + I ) V = ( ) 5 = mw P() = I V =.94 5 = 4. mw \ P av = mw 4. I L =.94 m, I =.9867 m N = N (M ) I /I L = N.3 (M ) 4.2 The noise margins depend upon temperature because the voltage across a conducting diode and V E are temperature dependent. The input diode and the base-emitter junction of T are in polarity opposition, therefore, the temperature sensitivities of these two junctions cancel. Therefore, the temperature sensitivity of the circuit depends on the temperature sensitivities of D 2 and the base-emitter junction of T 2. In HTL, D 2 is replaced by the Zener diode. Since the temperature sensitivity of a Zener diode is positive whereas for a forwardbiased diode it is negative, therefore, the temperature sensitivities of Z and the base-emitter junction of T 2 cancel (their magnitudes are of the same order). Hence the temperature sensitivity of the HTL gate is significantly better than that of the DTL gate. 4.3 (a) When the output is LOW. ase-collector junction of T is forward-biased T 2 and T 3 are in saturation. Therefore, V = = 2.3 V urrent through R = =. 675 m 4 V 2 = = V 5 urrent through R 2 = = m 4.

37 Since, T 4 and D are cut-off, therefore, I 4 = Therefore, I () = = m (b) t least one of the inputs is LOW. \ V = =.9 T 2, T 3 and T 4 are cut-off \ I = urrent through R = =.25 m (c) The total current will be sum of current through R (as given in (b) part above) and given in Eqs. 4. and 4. = = m 4.4 The current I remains same and it does not affect the fan-out of the gate G. 4.5 (a) If R 4 =, the change in output from logic to logic will be faster. Since T 3 does not turn off (because of storage time) as quickly as T 4 turns on, therefore, both T 3 and T 4 will be conducting simultaneously for some time which will cause almost short circuiting of the V supply. (b) When the output is in LOW state, V 4 = V which makes V E4 =.8 V if the diode D is not present. This means T 4 will be in saturation and its collector current would be V V sat V I 4 = E 4, E3, sat (c) 5 = = 46 m which is very large and will increase significantly the power dissipation. Moreover, it is simply a wastage of power. (i) When output is in LOW state, the shorting of output to ground will not have any effect. (ii) When output is in HIGH state, the relevant portion of the circuit with output shorted to ground is shown in Fig. Prob The base current and the collector current of T 4 will become V V 4,sat V I 4 = R E D = = 25. m 4. 36

38 V V 4,sat V and I 4 = R \ I s = I 4 + I 4 E D 5 = = 4 m 4 = = 43.5 m This large current will continuously be drawn from the supply as long as at least one of the inputs is LOW. This will damage the transistor T 4 and the diode D. V =5V R 2 =.4 kw R 4 = kw I 4 T 4 2 I 4 D E 2 3 E 3 I s Fig. Prob Let the output transistor T 3 of one gate is in saturation, while that of the other gate is cut-off. The voltage at Y will be LOW, which will make the transistor T 4 of the gate whose T 3 is cut-off to conduct through T 3 of the other gate which is in saturation. The corresponding current drawn from the power supply will be I 4 + I 4 = 4.4 m. This continuous current will damage these transistors. When both the outputs are HIGH or LOW, the currents drawn from the supply will be same as the currents without this connection. 4.7 The circuit is shown in Fig. Prob V VOH ( ) 3 R (max) = = kw IOH + 8 IIH = 4.56 kw V R VOL 5. 4 (min) = = = 44. kw I + 8 I OL Therefore,.44kW < R < 4.56 kw 4.8 The relevant portion of the circuit is given in Fig. Prob (i) When the output Y =, V (5 I OH + 6 I IH ) R ³ V OH IL 37

39 which gives V V R (max) = 5I + 6I OH OH IH ( ) 3 = kw = 74. kw V = +5 V R I IH I OH Output circuit of open-collector gate Fig. Prob. 4.7 Load gates V = 5 V R I IH I OL I OH I OH I OH I OH I OH Fig. Prob Y I IL I IH I IL I IH I IL I IH I IL I IH I IL I IH I IL

40 (ii) When the output Y =, it is assumed that only one of the driving gates has its output transistor in saturation while the output transistors of all the other gates are cut-off. V V R OL I OL + NI IL which gives R (min) = V I OL + V NI OL IL 5. 4 = 72. kw Therefore, R should be between.72 kw and.74 kw. value of R = kw is reasonable. 4.9 Let us assume a supply voltage V = + 5V and corresponding V OH = 2.4 V ( ) 3 \ R (max) = 28. kw and R (min) =. 59 kw Therefore,.59kW < R <.28 kw 4.2 (a) No (b) No (c) No (d) Yes 747 V = +5 V V = + V V, 3 Lamp Fig. Prob is an open-collector non-inverting buffer with V OH = 3V (maximum), which means a lamp load along with the necessary supply voltage may be connected as shown in Fig. Prob Let us take LS devices driving other devices. (i) LS driving standard devices I OH (LS) = 4 m I OL (LS) = 8 m (74 series) I IH (Standard) = 4 m I IL (Standard) =.6 m 39

41 Here, I OH (LS) = I IH (Standard) and I OL (LS) = 5 I IL (Standard) This means, when the output is LOW, the fan-out is 5, whereas it is when the output is HIGH. Therefore, the fan-out is 5 (ii) LS driving LS I IH (LS) = 2 m I IL (LS) =. m Which gives a fan-out of 2 when the output is HIGH and 8 when it is LOW. Therefore, the fan-out is 2. Similarly, the complete table can be verified ase I Let T 2 be cut-off. Then the output circuit will appear as shown in Fig. Prob. 4.22(a), whose equivalent circuit is shown in Fig. Prob. 4.22(b). P P 4 R 2 R 2 h FE I T 4 4 V n Y V n I E 4 Y R E4 R E4 Q Q (a) Fig. Prob From the equivalent circuit, we obtain (b) (a) V YQ = RE4 ( + hfe ) R + ( + h ) R 2 FE E4 V n. 5 ( ) =. 3 + ( )(. 5) V n =.998 V n (b) V YP = (V n V YQ ) =.2 V n Therefore, if the terminal P is grounded, the noise voltage present in the output is negligibly small. ase II Let T 2 be conducting and T be cut-off. (a) The noise voltage at the collector of T 2 = the noise voltage at the base of T 4. = 8. Vn =. 797 Vn Since T 4 is operating as an emitter-follower, therefore, V YQ =.797 V n (b) V YP = (V n.797 V n ) =.23 Vn 4

42 This again shows that the noise voltage is very small between Y and P and hence the terminal P is grounded (a) The 5.2 V supply will appear across R E4 or R E3 and no damage is caused to the supply and the circuit. (b) The 5.2 V supply voltage will appear across the output transistor T 4 or T 3. lso 5.2 V supply gets applied to their bases through R 2 and R respectively. Therefore, the output transistor will burn out In a TTL gate, when the output changes from V() to V(), a current spike of 4.4 m is produced, whereas in the case of EL the change in current is negligibly small when the output changes from LOW to HIGH and vice-versa Let = = =, D =, and E = Therefore, Y = and Y 2 =. orresponding to this T 4 of G is acting as an emitter follower while that of G 2 is acting as a diode. The relevant portions of the circuits are shown in Fig. Prob In this when Y and Y 2 are connected together, the voltage at the output terminal will be equal to.75 V (i.e., the voltage across T 4 acting as a diode). onsequently T 4 goes to cut-off. Similarly, when Y = and Y 2 = identical situation will prevail making the output. When Y and Y 2 both are same, the output will be equal to Y = Y 2. This confirms that OR operation is performed when the outputs are connected in wired logic. Similarly, it can be proved for all the other cases. V = V = R 2 R 2 (-.85 V) T 4 R E4 (-.55 V) (-.75 V) Y Y 2 T 4 R E4-5.2 V Fig. Prob V 4.26 The output logic levels of EL, input/output logic levels of MH25 I, and the input logic levels of TTL are shown in Fig. Prob V V OH 2V V IH.9V.7V V OH EL V OL (a) Output logic level voltages of EL.5V V OL.3V.48V 4 V IH V IL MH25 Translator (b) Input/output logic level voltages of Translator Fig. Prob V IL TTL (c) Input logic level voltages of TTL

43 From the logic levels, we observe, V IH (Translator) < V OH (EL) V IL (Translator) > V OL (EL) which shows that the input of MH25 I is EL compatible. Similarly, V IH (TTL) < V OH (Translator) V IL (TTL) > V OL (Translator) which shows that the output of the translator is compatible with TTL The output Y of EL NOR gate is Y = + The output of the Translator circuit is Y and the output of TTL Inverter will be Y = Y. EL Y MH25 Translator Fig. Prob Y TTL Y The complete circuit is shown in the above figure (a) onsider the NMOS inverters shown in Fig If the output accidently gets shorted, large current from V DD will continuously flow through the load transistor T 2 which may damage the load transistor. (b) onsider the MOS inverter of Fig When T is ON, the output voltage is LOW (» V). Now if the output gets shorted to ground, it does not cause any problem. On the other hand when V i is LOW, T is cut-off, and if the output gets shorted to ground, whole of V will appear across T 2 which is conducting. This will cause a relatively very high current to flow through T 2 which may damage it, since T 2 is not meant to carry such large currents. The normal current through T and T 2 is extremely small being the OFF current of either T or T Its operation is given below Inputs State of Output T T 2 T 3 T 4 Y OFF OFF ON ON V V ON OFF OFF ON V OFF ON ON OFF V V ON ON OFF OFF 42

44 4.3 The fan-out is given below. TTL/MOS 74H 74HT 74 74T 54/ H/74H L/74L S/74S 54LS/74LS S/74S LS/74LS /74 54H/74H 54L/ 54S/ 54LS/ 54S/ 54LS/ 74L 74S 74LS 74S 74LS (a) 74H/74HT (b) 74 /74 T When output is HIGH, it can drive a total of up to 2 gates. When output is LOW, it can drive 2 74S gates requiring m of current. The remaining 4 m of current can drive 4 74LS gates. Therefore, maximum possible number of LS gates which can be driven is The output logic levels of MOS and the input logic levels of MH24 TTL-to-EL translator are given in Fig. Prob V OH 3.76V V IH 2V V OL.37V MOS (a) V IL.8V MH24 translator (b) Fig. Prob From these logic levels, we observe, V IH (Translator) < V OH (MOS) V IL (Translator) > V OL (MOS) which shows that the input of the translator is compatible with MOS. Since the output of the translator is compatible with EL, therefore, MOS-to-EL interfacing is possible using TTL-to-EL translator The output logic levels of MH25 translator and the input logic levels of MOS (74HT & 74 T) are shown in Fig. Prob

45 V OH 2.5V V IH 2V V OL.5V V IL.8V MH25 Translator (a) Fig. Prob MOS (74HT & 74T) (b) From these logic levels, we observe, V IH (MOS) < V OH (Translator) V IL (MOS) > V OL (Translator) Therefore, the output of the translator is compatible with these MOS devices. Since the input of the translator is compatible with EL, therefore, EL-to- MOS interfacing is possible. For MOS 74 H, and 74 series V IL =.35V V IH = 3.85V and for MOS 74 series V IL =.5V V IH = 3.5V For these MOS Is, V IL (MOS) > V OL Translator but V IH (MOS) < V OH (Translator) Therefore, a resistance R and V are required to be connected to pull up the voltage at P corresponding to V OH (Translator) R P V MH25 Translator (c) MOS Fig. Prob

46 HPTER 5 5. Let S and S 2 be the two switches. The circuit diagram of the system is shown in Fig. Prob. 5.(a): L S S 2 Supply Fig. Prob. 5.(a) (a) The truth table is given below: (b) The logic equation is S S 2 L ulb ON = OFF = L = S S 2 + S S 2 (c) The ND-OR realization is given in Fig. Prob. 5.(b): S S 2 L Fig. Prob. 5.(b) (d) Replace each of the ND gates and the OR gate in the above figure by NND gates. The resulting circuit will be NND-NND realization. 5.2 (a) Inputs Output D f 45 (ontd.)

47 (ontd.) Inputs Output D f (b) The K-map is given in Fig. Prob The simplified expression is f = + D D (a) D D Fig. Prob. 5.2 (b) f 5.3 (a) f = ( D ) ( D) ( D) ( D ) ( D ) ( D) ( D) ( D) ( D ) f 2 = ( D) ( D) ( D ) ( D ) ( D) ( D) ( D ) ( D ) ( D ) (b) The K-maps for f and f 2 are given in Fig. Prob. 5.3(a) and (b) respectively. The minimized expressions are: D D (a) Fig. Prob. 5.3 (b) 46

48 f = ( + + D) ( + + ) ( + + D) ( + + D ) ( + + ) f 2 = ( + ) ( + ) ( + + D ) ( + D ) (c) The OR-ND realizations are shown in Fig. Prob. 5.3(c) and (d) for f and f 2 respectively. D 5.4 (d) Replace all the ND and OR gates in figures () and () by NOR gates to obtain realizations using only NOR gates. (a) D D (c) f Fig. Prob. 5.3 D D (d) f 2 D D f D Fig. Prob. 5.4(a) 47

49 (b) D f D D (c) Realization for (a) requires /2 743 a total of three chips. Realization for (b) requires a total of only two chips. 5.5 (a) Fig. Prob. 5.4(b) 74 D Y (b) / Y D 7427 Fig. Prob

50 5.6 (c) Realization of (a) requires only one chip whereas (b) requires two chips. 3/4 742 D D f 5.7 (a) Fig. Prob. 5.6 D Fig. Prob. 5.7(a) (b) f = å m (2, 3, 6, 7, 8, 9,,, 2, 3, 4, 5) (c) f = + f Fig. Prob. 5.7(b) 5.8 (a) Figure Prob. 5.8 (i) below gives the K-map. Using offset adjacencies shown in the K-map, the expression for f can be written as f = ( D) ( ) + ( D) ( ) = ( ) ( D) D ( ) D D( Å ) Fig. Prob. 5.8(i) 49 D ( ) D ( Å )

51 f D Fig. Prob. 5.8(ii) Logic Its realization using EX-OR gates is given in Fig. Prob. 5.8(ii). This realization requires only one 7486 I chip. (b) Its K-map is given in Fig. Prob. 5.8(iii) The minimized expression is f 2 = + D + D The realization using NND gates is given in Fig. Pro. 5.8(iv). This requires one 74 chip and one gate of 74 chip. D D f 2 D (iii) (iv) Fig. Prob Truth table of D-to-Excess-3 code converter is given below. D Excess-3 D E 3 E 2 E E Here only ten out of sixteen combinations are used and the other six are taken as don t-care conditions. The K-maps for the outputs E, E, E 2 and E 3 are given in Fig. Prob The minimized expressions are: E = 5

52 D D E E (a) (b) D D E 2 E 3 (c) Fig. Prob. 5.9 (d) E = + E 2 = + + E 3 = D + + The circuit can be drawn using NND gates. 5. Truth table of Excess-3-to-D converter can be prepared using the truthtable of Prob The K-maps can then be prepared and minimized. The minimized expressions are given below. = E = E E + E E = E 2 E + E 2 E E + E 3 E E D = E 3 E 2 + E 3 E E The circuit can now be drawn using NND gates. 5. (a) The K-map is shown in Fig. Prob. 5.(a). The minimized expression is f = D = + D (b) The K-map is shown in Fig. Prob. 5.(b). The minimized expression is f2 = ( + + D)( + + D)( + ) (c) The K-map is shown in Fig. Prob. 5.(c). The minimized expression is f3 = ( D)( + + D)( + + )( + + D) The circuits for f, f 2, and f 3 can be drawn using NOR gates. 5

53 D D (a) D (b) (c) Fig. Prob The K-map for f is shown in Fig. Prob. 5.2 and the minimized expression is f = E + E + D + + DE This can be realized using NND gates. Similarly, the minimized expression for f 2 is f2 = E + D + DE + DE + E + DE + E which can be realized using NND gates. = = D E DE DE E D E Fig. Prob (a) Its K-map is given in Fig. Prob. 53(a). 52

54 (a) D The minimized expression is D Fig. Prob. 5.3(a) Y = D + D + D D Y D (b) The K-map is given in Fig. 5.8 of the book and Y = D + D (c) Realization of part (a) requires 2 I chips (74) whereas for part (b) one I chip (74) only is required. D D Fig. Prob. 5.3(b) Fig. Prob. 5.3(c) 5.4 (a) Figure Prob. 5.4(a) and (b) show the K-maps of f for NND and NOR realizations respectively. The minimized expressions are f = + D + D + D (SOP) and f = ( + + )( + D)( + D)( + D ) (POS) ircuits using NND and NOR gates can be designed using the above expressions. (b) Similar to part (a), the minimized expressions are obtained which are given below. f 2 = D + + (SOP) 53 Y

55 and f 2 = ( + )( + D)( + )( + ) (POS) These equations can be used to design circuits with NND and NOR gates. D D (a) 5.5 Its K-map and circuit realization are given in Fig. Prob (a) ( Å D) D ( D) D Fig. Prob. 5.4 (b) f (b) D ( Å D) ( Å ) D f 2 54

56 (c) D (ÅD) D f 3 ( Å D) Fig. Prob Its truth table is given in Table Prob Table Prob bit word Odd parity bit Even parity bit D P O P E The K-map for P o is given in Fig. Prob. 5.6(a), from which P o is obtained as P o = ( D) + ( Å D) + ( Å D) + ( D) = ( Å ) ( + D) Its realization using EX-OR and EX-NOR gates is given in Fig. Prob. 5.6(b). D (a) D Fig. Prob (b) P o

57 5.7 From the truthtable given in Prob. 5.6, K-map is prepared and the circuit is designed. These are given in Fig. Prob P E = D D (a) D Fig. Prob (a) The K-map using s is given in Fig. Prob. 5.8(a). The minimized expression for f is (b) f = DE + DF + EF + DEF The circuit for f can be realized using NND gates. Similarly, we can minimize using s which will lead to a circuit realizable by NOR gates. (b) The K-map using s is given in Fig. Prob. 5.8(b). The minimized expression for f 2 is f 2 = ( D + E + F ) ( + + D + E + F) ( E + F ) ( + + D + E + F) ( E + F) ( E + F) ( E + F) ( D ) ( + + D + E) ( + + D + E) ( + + D + F ) ( D) The circuit for f 2 can be realized using NOR gates. Similarly, we can minimize the function using s which will lead to a circuit realizable by NND gates. 5.9 Let the augend, addend, and the carry inputs to the full-adder be n, n, and n respectively and S n, and n be the sum and carry outputs respectively. (a) n and n are applied at the two inputs of first half-adder H. Its outputs are S (Sum) and (arry). Its truth table is given in Table Prob Table Prob. 5.9(a) n n S P E 56

58 D EF D EF DEF D EF EF D EF DE DF Fig. Prob. 5.8(a) D D EF EF EF D EF D Fig. Prob. 5.8(b) 57

59 n n n H S H 2 2 S 2 = S n n Fig. Prob 5.9(a) Truth table of the full-adder using input variables S,, and n is given below: Table Prob. 5.9(b) S n n S n K-maps for n and S n are shown below: S n n S K-map for n K-map for S n n = + S n S n = S n - + S n = + 2 = S Å n S n and n are generated using H 2 and an OR gate as shown in the block diagram. 58

60 (b) n EX OR() S EX OR(2) n S 2 = S n 2 n ND Fig. Prob. 5.9(b) ND-2 OR n 5.2 Propagation delay time for S n = t pd [EX-OR()] + t pd [EX OR(2)] = = 4 ns. Propagation dealy time for n = t pd [EX-OR() + t pd (ND-2) + t pd (OR) = = 4 ns. Since the propagation delay time (t pd ) of ND is less than the t pd of EX-OR(), therefore, it is not counted. 5.2 f(,,, D) = pm(2, 7, 8, 9,, 2) = Sm (,, 3, 4, 5, 6,, 3, 4, 5) Table (a) Grouping of minterms according to number of s. Group Minterm Variables heck for inclusion D in groups of 2 ü ü 4 ü 3 ü 2 5 ü 6 ü ü 3 3 ü 4 ü 4 5 ü Table (b) Grouping of two minterms Group Minterms Variables heck for inclusion D in groups of 4, ü, 4 ü, 3, 5 ü (ontd.) 59

61 (ontd.) Group Minterms Variables heck for inclusion D in group of 4 4,5 ü 4, 6 3, 2 5,3 6, 4, 5 3 3, 5 4, 5 Table (c) Grouping of 4 minterms Group Minterms Variables D,, 4, 5, 4,, 5 Table (d) PI table PI Decimal Minterms terms numbers ü,, 4, 5 Ä D ü, 3 D ü 4, 6 D ü 3, D ü 5,3 D ü 6, 4 D ü, 5 D 3, 5 4, 5 ü ü ü ü ü ü ü From the PI table, we see that the column for minterms contains only one, therefore, is an essential prime-implicant. ll the other columns contain 2 or more Xs. Therefore, starting from the prime-implicant D, we see the minterms that are covered by each prime-implicant and find the minimum number of prime-implicants that will cover all the minterms. Depending upon the prime-implicants selected above, the minimized function is f(,,, D) = + D + D + D + D + D + D There can be other options also. 6

62 5.22 f (,,, D) = Sm (, 3, 5, 8, 9,, 5) + d(2, 3) Table (a) Grouping of minterms/don t care terms according to number of s. Group Minterm/ Variables heck for inclusion don t care term D in group of 2 ü 2* ü 8 ü 3 ü 2 5 ü 9 ü ü 3 3* ü 4 5 ü Table (b) Grouping of 2 minterms/don t care terms Group Minterms/ Variables heck for inclusion don t care terms D in group of 4, 3 ü, 5 ü, 9 ü 2*, 3 8, 9 3, ü 5, 3* ü 2 9, ü 9, 3* ü 3, 5 ü 3, 5 ü Table (c) Grouping of 4 minterms/don t care terms Group Minterms/ Variables don t care terms D, 3, 9,, 5, 9, 3*, 9, 3,, 9, 5, 3* 9,, 3*, 5 2 9, 3*,, 5 There are a total of 5 prime-implicants D, D, and D from Table (c) and and from Table (b). 6

63 Table (d) PI Table PI Decimal Minterms/don t care terms terms numbers 2* * 5 D, 3, 9, D, 5, 9, 3* ü Ä D 9,, 3*, 5 ü Ä 2*, 3 8, 9 ü Ä ü ü ü The essential prime- implicants are: D, D, and. Except the minterm 3 all the other minterms have heen covered by the essential prime-implicatns. Therefore, D is to be included in the minimized expression. The minimized function is f (,,, D) = D + D + D f (,,, D, E) = Sm (8, 9,,, 3, 5, 6, 8, 2, 24, 25, 26, 27, 3, 3) Table (a) Grouping of minterms according to number of s Group Minterm Variables heck for inclusion D E in group of 2 8 ü 6 ü 9 ü 2 ü 8 ü 24 ü ü 3 ü ü 26 ü 5 ü 4 27 ü 3 ü 5 3 ü Table (b) Grouping of 2 minterms Group Minterms Variables heck for inclusion D E in group of 4 8, 9 ü 8, ü (ontd.) 62