# Department of Electrical Engineering and Computer Sciences University of California, Berkeley. Final Exam Solutions

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1 Electrical Engineering 42/00 Summer 202 Instructor: Tony Dear Department of Electrical Engineering and omputer Sciences University of alifornia, Berkeley Final Exam Solutions. Diodes Have apacitance?!?! Frustrated at how inaccurate all our linear diode models have been, ohn decides to cook up another one. The Zener diode below has a linear ON characteristic and a breakdown voltage V B like any other, but it is modeled as a capacitor D when it is reverse-biased, or OFF. i D (A) Reverse-Bias (OFF) i D v D = 0 D BD OFF 2 ON v D (V) (a) (3 points) Let s first analyze the diode in its forward-bias (ON) mode. What is its linear circuit equivalent in this region of operation? Label the directions of v D and i D. i D 0.5 Ω V v D (b) (3 points) ohn attaches this diode to a circuit as shown below. Ω 5u(t) A i D v D (t) 3 Ω Evidently, the Zener diode is now reverse-biased. On the plot below, draw in the load line immediately after the current source turns on, i.e., t = 0. Be sure to label slopes and intercepts; your plot need not be to scale. i D (A) /3 v D (V)

2 Ω 5u(t) A i D v D (t) 3 Ω (c) (3 points) Suppose the capacitance of the diode is D = µf (0 6 F). What is the time constant τ associated with it? The time constant is given by τ = R D, where R is the Thévenin resistance as seen by the diode/capacitor. Since the current source becomes an open, the Ω resistor has no effect, and we simply have τ = R D = (3 Ω)( µf) = 3 µs (d) (6 points) Sketch the voltage v D (t) across the diode as a function of time. Label key values on the v D axis. Remember that a charging capacitor reaches about 63% of its final value after one time constant τ. Don t forget to account for the diode s breakdown region! The capacitor naturally wants to exponentially charge up to the steady-state value, which is 5 V (obtained if you treat the capacitor as an open circuit). However, this voltage abruptly ends at 0 V, the breakdown voltage of the diode. v D (t) 0 5 τ 2τ 3τ t 0 5 2

3 2. Moar Diode Madness William is having so much fun with diodes that he has constructed the following nightmare. Fortunately, you remember that you can always break the problem up into pieces that you can analyze separately. kω kω v in (t) v (t) 3 V v o (t) v L (t) R L For this entire problem, we can make the following assumptions: We are in A steady-state, such that we can ignore all transient effects. The capacitances are large, such that discharging effects are negligible. The op amp is ideal. All diodes are ideal with a turn-on voltage of 0 V. Finally, the input signal is v in (t) = 5 sin(t) V. (a) (5 points) Sketch the voltage v (t). Be sure to label peak values. This part of the circuit simply clamps the positive peak of the waveform to 3 V. v (t) 3 t 7 3

4 kω v in (t) kω v (t) 3 V v o (t) v L (t) R L (b) (5 points) Find an expression for v o (t) in terms of v (t) and v in (t). Using L at the inverting input of the op amp along with SP (v = v ), we obtain v v in kω v v o kω = 0 v o (t) = 2v (t) v in (t) (c) (5 points) We re almost there! Given what you found above, sketch the voltage v L (t). Be sure to label peak or constant values. Remember that we don t care about transient effects! Notice that the output side of the op amp is simply a peak detector with the diode facing backwards. Assuming negligible discharge, v L (t) will keep constant at the minimum value of v o (t). According to our expression above, the minimum value is v L (t) = v o,min = 2v,min v in,min = 2( 7) ( 5) = 9 V v L (t) t 9 4

5 3. FFFFFFFFUUUUUUUUUUU erry is trying to design an amplifier for the hundredth time. This time, he has turned to MOSFETs, specifically the common-source configuration. He has pulled up the following NMOS specs and designed the circuit as follows. 20 V =.0 A/V 2 V to = 2 V R D = kω v o (t) v in (t) V G kω R S = 500 Ω (a) (0 points) Recall that the transconductance of the transistor is given by g m = 2(V GS V to ) = 2 I DS () Given that Tony has demanded g m = 20 ms (0.02 S), find the necessary bias V G that should be applied at the gate to achieve this. g m =.02 = 2 I DS = 2.0I DS I DS =.0 A V S = I DS R S = (.0 A)(500 Ω) = 5 V g m =.02 = 2(V GS V to ) = 2(.0)(V G 5 2) V G = 8 V 5

6 20 V =.0 A/V 2 V to = 2 V R D = kω v o (t) v in (t) V G kω R S = 500 Ω (b) (2 points) Draw the equivalent small-signal model of the circuit and show that the gain is given by A v = v o = g mr D = 20 2 (2) v in g m R S Be sure to label all components and values. The SS model of this circuit is shown below. G D v out v in kω v gs g m v gs R D S R S Now we proceed to find the small-signal gain of this amplifier. v s = g m v gs R S = g m R S (v in v s ) v s = g mr S v in g m R S ( v o = g m v gs R D = g m R D (v in v s ) = g m R D v in g ) ( mr S v in = g m R D g m R S v o = g mr D = 20 v in g m R S 2 g m R S ) v in 6

7 (c) (8 points) Tony now insists that the gain be a function of the signal frequency. erry cleverly adds in a source capacitor as follows. 20 V =.0 A/V 2 V to = 2 V R D = kω v o (t) v in (t) V G kω S R S = 500 Ω The gain of the amplifier now becomes a complex transfer function, given by ( ) H(ω) = V o = g mr D = g mr D jωr S S V in g m Z S g m R S jω R S S 2 jωr S S jωr g S S /0 mr S (3) Sketch the magnitude Bode plot for the transfer function. Be sure to label any cutoff frequencies and asymptotic magnitude values, as well as slopes. You may leave your plot labels in terms of R S S for convenience. (Hint: 20 log 0 (2) = 6) H(ω) db 26 6 R S S 0 R S S ω 7

8 4. Introducing... the NYAN gate! Dennis has finally perfected the NYAN gate and is ready to add it to the current repertoire of logic gates. Its logic gate symbol is shown below: A B N Unlike most other logic gates, the NYAN gate takes in exactly three inputs. The truth table showing all its possible input/output combinations is as follows: A B N (a) (2 points) Is the NYAN gate commutative? Briefly justify why or why not. No, it is not. Observe that the order of inputs into the gate actually matters. For example, NYAN(0, 0, ) NYAN(0,, 0). (b) (6 points) Write the SOP Boolean expression for the output N in terms of the inputs A, B, and. Simplify it into a sum of two terms only. N = A B AB AB AB = A (B B) AB( ) = A AB 8

9 (c) (8 points) Implement your simplified expression from above with a logic gate circuit. learly indicate the inputs A, B, and, as well as the output N. For full credit, use no more than 4 logic gates. The first term can be rewritten as a NOR using De Morgan s law: A = A Then the logic gate circuit can be implemented as follows: B A N (d) (4 points) Now help Dennis implement the NYAN gate using MOS digital logic. He already has the pull-down network in; your job is to fill in the pull-up network above it. For full credit, use no more than 4 transistors (you may use inverted inputs). V DD A A B Pull-Down Network N GND 9

10 5. The Final ountdown The hours that you have left in EE42/00 are numbered, and you can t wait to finish this exam and GTFO to party away your Friday night and what s left of summer. But before you do so, you must help finish our timer circuit below to perform the final countdown. Q Q Recall that the behavior of the flip flop is as follows: Q n 0 Q n Q n 0 0 Q n Q n (a) (4 points) The output of this circuit is given by Q = (Q ) 2. Draw the state transition diagram for the given circuit above

11 Q Q (b) (4 points) The first feature we want to add is the ability to pause the timer. Suppose we add in a new input P ; when P =, the timer keeps its current state and ignores the clock (Q should not reset to 0). Then when P = 0, the timer continues as usual. Given the original two flip flops below, make all the necessary connections to implement this new feature, using logic gates if necessary. Q P Q

12 Q Q (c) (4 points) Suppose the next feature we want to add is an LED (light-emitting diode) such that it lights up whenever our timer lands on the state Q = 0 2. The LED lights up when the signal line feeding into it is high (or ). Make all the necessary connections to implement this new feature, using logic gates if necessary. Q Q 2

13 Q Q (d) (8 points) You may have noticed that our timer doesn t have a very wide range, since it only has two bits of output. The last extension we want to do is to modify the timer so that it counts down from Q = 7. Make all the necessary connections to implement this new feature, using logic gates if necessary. (Notice that we have drawn in a third flip flop for you.) Q Q 2 Q Q 2 3

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Electrical Engineering 42/00 Summer 202 Instructor: Tony Dear Department of Electrical Engineering and Computer Sciences University of California, Berkeley Final Exam: Friday, August 0, 202 Last Name:

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