Lecture 14. Ozgur Aktas. March 20, 2006


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1 Lecture 14 Ozgur Aktas March 20, 2006
2 What we have learnt up to now? Basic semiconductor equations Drawing band diagrams for pn junctions, and npn/pnp transistors RTL/DTL/TTL/ATTL/STTL analysis Analysis for states of each transistor Transfer characteristics Power dissipation Definitions that relate to delay Input/output currents, voltages The problems/solutions of charge removal from base ECL basics L14
3 Todays overview Announcements Output impedance of Darlington pullup circuit Finish ECL L14
4 Announcements Exam on April 13th HW2 due this Friday (March 24th) Tutorial session on April 10 evening L14
5 Output impedance of Darlington pullup circuit The circuit is drawn as follows: +5V R C R CP Assuming the output current is small the transistors Q P and Q P 2 will be active. Then, ignoring R bb, the equivalent model will be: +5V Q P R C R CP Q P2 β I B(QP) R EP V out I B(QP) V BEA β I B(QP2) I B(QP2) V BEA R EP V out L14 1
6 Output impedance of Darlington pullup circuit +5V r out = V o I o R C I B(QP) β V BEA I B(QP) R CP β I B(QP2) I o = (β + 1)I B(QP 2) ( I o = (β + 1) (β + 1)I B(QP ) V ) o R EP Ignoring the term with R EP R EP I B(QP2) V BEA V out I o = (β + 1) 2 V o 2 V BEA R C V o I o = R C (β + 1) 2 L14 2
7 ECL gates The basic circuit forming the basis of ECL gates is the emitter coupled current switch R CI out R CR Q I Q R The operation of the current switch is based on changing the transistor through which the current flows. This change is fast, since the emitter current of an active npn transistor depens exponentially on the baseemitter voltage. For each 60mV change in the baseemitter bias, the emitter current of an active npn changes by exp( V BE kt q ) L14 1
8 ECL gates The basic circuit forming the basis of ECL gates is the emitter coupled current switch Band diagrams of EB junctions of Q I and Q R. Emitter Base < R CI R CR out Q I Q R = > L14 2
9 ECL gates Emitter coupled current switch Assume V IH V IL = 100mV V in < V ref 0.05 :: Q I is OFF, Q R is ACT V in > V ref :: Q I is ACT, Q R is OFF R CI R CR out Q I Q R In order to guarantee ACT operation, the resistor, input voltage range, and power supply voltages must be selected APPROPRIATELY. Emitter Base < ECL standart :: = 0V, V EE = 5.2V, V ref = 1.175V = So: V in < V ref 0.05 :: V CQI = > V in > V ref :: V CQI = R CC L14 3
10 ECL gates emitter coupled current switch Basic ECL gate R CI R CR out Q I Q R R CI R CR Q INV Q NINV Q I Q R (V INV ) (V NINV ) L14 4
11 ECL gates Basic ECL gate R CI R CR Q INV Q NINV Q I Q R (V INV ) (V NINV ) The emitter followers ( Q INV R o and Q NINV R o ) provide extremely low output impedance. Thereby increasing the capacity to feed high number of fanout gates. L14 5
12 ECL gates Output impedance of emitter follower Emitter follower and model The output resistance consists of R bb as seen from the output in parallel with R o. Q ef R bb β I B I B L14 6
13 ECL gates Output impedance of emitter follower Model of emitter follower Derivation HERE R bb β I B I B L14 7
14 ECL inverter transfer characteristic: NINV R CI R CR Q INV (V INV ) Q I Q R Assume V IH V IL = 100mV Q NINV (V NINV ) Consider node NINV with V IN =logic0 V IN < V ref 0.05 (LOW voltage) Now: Q I :: OFF, Q R ::ACT = V ref V BEA ( V EE ) R E I RCR = α I RCR = α V ref V BEA ( V EE ) R E V BQNINV = 0 R CR I RCR The node (NINV) is now at logic 0 value, which is: V OL = V BQNINV V BEA = 0 R CR I RCR V BEA V OL = V BQNINV V BEA = 0 R CR α V ref V BEA ( V EE ) R E V BEA The resistor values and V EE is selected so that V OL 2 V BEA L14 8
15 ECL inverter transfer characteristic: NINV Q INV R CI R CR 270 Ω 300 Ω Q NINV (V INV ) 2000 Ω 1240 Ω (V NINV ) 2000 Ω Use V BEA = 0.75V for ECL NINV with V IN =logic0 (LOW) V OL = R CR α V ref V BEA ( V EE ) V BEA R E ( 5.2) V OL = = 1.526V 1240 Note that this is for NINV output. L14 9a
16 ECL inverter transfer characteristic: NINV Q INV R CI R CR 270 Ω 300 Ω Q NINV (V INV ) 2000 Ω 1240 Ω (V NINV ) 2000 Ω Use V BEA = 0.75V for ECL NINV with V IN =logic1 (HIGH) V IN > V ref (LOW voltage) Then, node NINV will be at logic1 (HIGH) V OH = 0 V BEA = 0.75V Note that this is for NINV output. L14 9b
17 ECL inverter transfer characteristic: NINV Q INV R CI R CR 270 Ω 300 Ω Q NINV (V INV ) 2000 Ω 1240 Ω (V NINV ) 2000 Ω Use V BEA = 0.75V for ECL For (V ref 0.05) < V IN < (V ref ) the logic state is indeterminate. Q I is switching from OFF to ACT. Q R is switching from ACT to OFF. Assume V o (NINV) changes linearly as V IN changes from V ref 0.05 to V ref L14 9c
18 ECL inverter transfer characteristic: NINV outputs ECL characteristics NON inverting output L14 10
19 ECL inverter transfer characteristic: INV NINV with V IN = logic0 (LOW) V IN < V ref 0.05 (LOW voltage) Now: Q I :: OFF, Q R ::ACT Node INV (V out ) is at logic1 (HIGH) V OH = V BEA = 0.75V Note that this is for INV output. Q INV (V INV ) 2000 Ω R CI R CR 270 Ω 300 Ω Q I Q R 1240 Ω Q NINV (V NINV ) 2000 Ω For (V ref 0.05) < V IN < (V ref ) the logic state is indeterminate. Q I is switching from OFF to ACT. Q R is switching from ACT to OFF. When V IN > (V ref ) Q I is ACT. Assume V o (INV) changes linearly as V IN changes from V ref 0.05 to V ref L14 11
20 ECL inverter characteristic: NINV & INV outputs ECL characteristics NON inverting output inverting output L14 12
21 ECL inverter transfer characteristic: INV Consider node INV with V IN =logic1 V IN > V ref (HIGH) Q INV R CI R CR Q NINV Now: Q I :: ACT, Q R ::OFF (V INV ) Q I Q R (V NINV ) = V IN V BEA ( V EE ) R E I RCI = α I RCI = α V IN V BEA ( V EE ) R E V BQNINV = 0 R CI I RCI The node (INV) is now at logic 0 value, which is: V OL(INV ) = V BQNINV V BEA = 0 R CI I RCI V BEA V OL(INV ) = 0 R CI α V IN V BEA ( V EE ) R E V BEA L14 13
22 ECL inverter transfer characteristic: INV Q INV R CI R CR 270 Ω 300 Ω Q NINV The resistor value R CI selected to be smaller than R CR so that V o = V OL for V IN = V OH V OUT V Q I Q OUT R (V INV ) (V NINV ) 2000 Ω 2000 Ω I 1240 Ω RE Use V BEA = 0.75V for ECL INV with V IN > (V ref )=logic1(HIGH) V OL = 0 R CI α V IN V BEA ( V EE ) V BEA R E V OL = V IN 0.75 ( 5.2) V OL = V IN 1.7 Note that this is for NINV output. L14 14
23 ECL inverter characteristic: NINV & INV ECL characteristics outputs L14 15
24 ECL inverter transfer characteristic: INV R CI R CR Q INV 270 Ω 300 Ω Q NINV V OUT V Q I Q OUT R (V INV ) (V NINV ) 2000 Ω 2000 Ω 1240 Ω As V IN increases further, Q I will saturate when V CE(QI ) = V CES Assume V BCS = 0.7V Assume V CES = 0.05V V C(QI ) = 0 R CI α V IN V BEA ( V EE ) R E V E(QI ) = V IN V BEA Rather than try to remember Eq. 6.23, just use V CE(QI ) = V CES for condition of saturation. When saturation of Q I happens V o = V IN + V BCS V BEA L14 16
25 ECL inverter transfer characteristic: INV Q INV R CI R CR 270 Ω 300 Ω Q NINV As V IN increases further, Q I will saturate when V CE(QI ) = V CES (V INV ) 2000 Ω 1240 Ω (V NINV ) 2000 Ω Assume V BCS = 0.7V Assume V CES = 0.05V V C(QI ) = V IN V E(QI ) = V IN 0.75 Solving for V CE(QI ) = 0.05 V INsat = 0.21V = V IN 0.95 L14 17
26 ECL inverter characteristic: NINV & INV outputs ECL characteristics L14 18
27 ECL inverter characteristic: NINV & INV V IN LOGIC V o (INV) V o (NINV) V IN < LOGIC V IN > LOGIC1 LOW V IN > 0.21 INVALID SAT L14 19
28 ECL inverter characteristic: MotorolaSPECs Typical and AVERAGE characteristics L14 20
29 ECL inverter characteristic: MotorolaSPECs NML= V OL(max) V IL(max) = = 0.175V NMH= V OH(min) V IH(min) = = 0.175V (note that the definitions are somewhat different than the ones used in the book) L14 21
30 ECL inverter power dissipation ECL power dissipation dominated by DC dissipation. This is an approximation and will not hold at higher frequencies. Still, we will only consider DC dissipation of ECL gates. P L is the DC dissipation when NONINVERTING output is LOW. P H is the DC dissipation when NONINVERTING output is HIGH. P L = ( V EE ) I EE = V EE I EE = V EE ( + I 1 + I 2 ) Q INV R CI R CR 270 Ω 300 Ω Q NINV Q I Q R (V INV ) (V NINV ) 2000 Ω 1240 Ω I 1 I Ω I EE L14 1
31 ECL inverter power dissipation Q INV R CI R CR 270 Ω 300 Ω Q NINV Q I Q R (V INV ) (V NINV ) 2000 Ω 1240 Ω I 1 I Ω I EE P L = ( V EE ) I EE = V EE I EE = V EE ( + I 1 + I 2 ) = V ref V BEA + V EE R E I 1 = V OH + V EE R E I 2 = V OL + V EE R E L14 2
32 ECL inverter power dissipation Q INV R CI R CR 270 Ω 300 Ω Q NINV Q I Q R (V INV ) (V NINV ) 2000 Ω 1240 Ω I 1 I Ω I EE P H = ( V EE ) I EE = V EE I EE = V EE ( + I 1 + I 2 ) = V OH V BEA + V EE R E I 1 = V OL + V EE R E I 2 = V OH + V EE R E L14 2
33 ECL inverter power dissipation Q INV R CI R CR 270 Ω 300 Ω Q NINV Q I Q R (V INV ) (V NINV ) 2000 Ω 1240 Ω I 1 I Ω I EE P DC = P L + P H 2 L14 3
34 ECL inverter power dissipation Q INV R CI R CR 270 Ω 300 Ω Q NINV Q I Q R (V INV ) (V NINV ) 2000 Ω 1240 Ω I 1 I Ω This specific circuits power dissipation to be asked in next quiz. I EE L14 4
35 ECL logic design R CI R CR Q INV Q NINV 1 Q I1 Q R (V INV ) (V NINV ) 3 Q I3 2 Q I2 Using ORNOR and inverterbuffer gates is much easier in ECL. Also: If we connect output of 2 ECL gates, the outputs are logically OR ed. The reason why ORNOR is to be preferred will be asked in next quiz. ECL implementation of a given logic function to be asked in the next quiz. L14 1
36 ECL temperature dependence The main source of temperature dependence comes from V BEA and V D. V BE T 2mV/ C V D (diode builtin potential) also shows a similar change. L14 1
37 ECL temperature dependence Considering the basic ECL inverter/buffer: Output high level is given as: V OH = V BEA So: Output low level is given as: V OH T = 2mV/ C V OL = R CI α V IN V BEA ( V EE ) R E V BEA So: V OL T = R CI R E ( VOH T V ) BEA T V BEA T 1mV/ C L14 2
38 ECL temperature dependence With increasing temperature, the NMH decreases and NML increases. The overall effect is a decrease in the noise margin It would be better to compansate so that the NM decreases slower. L14 3
39 ECL family: ECL I R CI R CR Q INV Q NINV Q I Q R (V INV ) (V NINV ) Decouples grounds for switch and emitter followers. L14 1
40 ECL family: ECL I/III/10k R CI R CR Q INV Q NINV Q I Q R (V INV ) (V NINV ) Has temperature compensated reference. L14 2
41 ECL family: ECL I/III/10k, temperature compensation δ represents the change in junction voltage. L14 3
42 ECL family: ECL I/III/10k, temperature compensation V R = 2δR 1 R1 + R2 δ 0.77δ V outlow = V R R C R E + δ R C R E delta V outhigh = δ V out (AV ERAGE) = V outlow + V outhigh δ Since average change in output levels is equal to change in V R, V R stays at midpoint of logic transition range. Hence, the NML and NMH changes equally. But NML and NMH still does change. L14 4
43 ECL family: ECL 100k R=500 R R R D1 Q INV Q I Q R Q NINV (V INV ) (V NINV ) D2 V ref2 =3.2V R E =300 Has constant current source (reducing dependence on V EE ) Diodes and R reduce temperature coefficients of V OL and V OH. Also has better temperature compansated reference voltage supply. L14 5
44 ECL family: Level sensitive active pulldown R CI Definitely makes a nice HWquix/exam question. R CR Vo Active pulldown decreases L tlh. V REG = V OL V BEA. Q I Q R V REG V ref2 L14 6
45 Omission Note: Not responsible from sections and 6.11 L14 1
46 Next Lecture Hour: Will finish ECL. Finish reading ECL in preparation of quiz. Will start MOS. Make a quick reading of MOS chapter for quiz. L14 1
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