Moore s Law Technology Scaling and CMOS

Transcription

1 Design Challenges in Digital High Performance Circuits Outline Manoj achdev Dept. of Electrical and Computer Engineering University of Waterloo Waterloo, Ontario, Canada Power truggle ummary Moore s Law Technology caling and CMO ource Intel Corp. Doubling of transistors on an IC every two years Ever since ICs were invented, transistor is scaled To pack more transistors in a given area Allow higher operational speed Constant voltage scaling Followed till. µm Constant field scaling All device dimensions, V DD, V T are scaled by a factor ( > )

2 Parameter caling Benefits Relation CV CF caling in Practice W, L, t ox / / V DD, V T / Area WL / 2 / 2 C ox C L C ox.wl / / K n, k p C ox.w/l I av t ox K n, p V 2 / J av I av /Area 3 t p (intrinsic) C L. V/I av / 2 / P av C L.V 2 /t p / 2 PDP C L.V 2 / / 3 Gate delay is reduced by 3% Frequency is increased by 43% Die area is reduced by 5% Power is reduced by 5% (for a given function) Energy per transition is reduced by 65%. Borkar, Design Challenges of Technology caling, IEEE Micro, July-Aug 99 Frequency caling Trend Outline Power truggle ummary ource Intel Corp. 2

3 Processor Power Trend Processor Power Projections Const. voltage scaling Const. field scaling. Borkar, Design Challenges of Technology caling, IEEE Micro, July-Aug 99 ource Intel Corp. Power Components 25 Leakage Pwr 2 Active Pwr 75 5 Power Density um. um.3 um. um Leakage power exponentially with scaling T j also with scaling under nominal and BI conditions ource Intel Corp. 25 Normalized Tj increase of. CMO chip T j at Normal Oper. Cond CMO technology generation, um T j is increased by ~.45x/generation emenov et.al., Burn-in Temperature Projections for Deep ub-micron Technologies, ITC3 3

4 Normalized temperature increase of CMO chip T j at Burn-in Conditions T = 25 C UHP, Ioff = 3 na/um LP, Ioff =.6 na/um CMO technology generation, um On-Die Temperature Variation Temp ( o C) R. Krishnamurthy, Intel JC 3 Cache Execution core 2 o C AGU emenov et.al., Burn-in Temperature Projections for Deep ub-micron Technologies, ITC3 Thermal gradient causes on-die timing variations ub-3nm Transistor caling Trends Normalized I ON /I OFF (n-mo transistor)... Typical corner, C, nominal V CC Berkeley Predictive Tech. Models High V TH I ON /I OFF ratio degradation: ~26x Low V TH Technology generation (nm) V TH scaled for high performance, I ON (V DD -V TH ) α I OFF /µm 3-5x/generation: result I ON /I OFF degradation.2..4 Normalized threshold voltage Transistor Leakage Current Model Threshold voltage impact V G = when transistor OFF + V G V TH γv B ηv D V D = nv v I T. e T OFF Ae Body bias impact DIBL impact when V D =V DD I OFF drain-source leakage: weak inversion and DIBL components modeled worst case leakage at C considered 4

5 Outline Power truggle ummary Leakage Control Techniques Reducing supply voltage (V CC ): Reduce V CC by 3%; V G =V 3% lower V D lower DIBL Non-minimum channel length transistor: G V G =V D I OFF B L e increase V TH weak inversion exponentially Extent of leakage reduction limited by V TH roll-off V TH L e V TH /V TH 7nm V TH vs. L e plot V TH roll-off regime L e /L e Leakage Control Techniques tack effect: V N = I OFF R OFF kt/q [K. Roy, TCAD 99] 3nm-7nm: V N 5-95mV Result -ve gate-source, body bias, reduced V D (DIBL) for N Reverse Body Bias: Results in stronger reverse bias of drain-bulk, source-bulk junction Reduces sub-threshold current Limited by optimum RBB voltage IOFF/um (na/um).e+2.e+.e+.e-.e-2.e-3.e-4 Region of interest G N N2 V N Reverse Bias Voltage [V B/V CC] D B I OFF R OFF Min. I OFF at RBB 3% V CC Leakage Control Techniques: I ON -I OFF Tradeoffs Normalized I OFF x 7nm, C, typical corner ref. pt. (no leakage ctrl.) -2% non-min. L e RBB.9..7 Normalized I ON V CC scaling stack effect Max. I ON degradation RBB, non-min. L e steepest gradient in I ON -I OFF plane Target Leakage reduction in high performance circuits tack effect, V CC scaling: reduce V G, degrade I ON.6.5 5

6 Leakage Control Techniques: caling Trends Normalized I OFF / I ON C, typical corner 3nm nm 7nm upply scaling non-min. Le tack effect RBB Effectiveness of all techniques degrading with scaling Normalized I OFF / I ON (F.O.M) for 3nm 7nm: RBB: 2 7.5; non-min. L e : 3. 2.; upply scaling:..; tack effect: Outline Power truggle ummary x2 x32 bits x2 Read Ports Bank x GBL 2: D<63:32> LBL Register File Organization x x Write Port LBL3 Bank7 x LBL2 LBL3 x R<255:>, W<255:> :256 AD :256 x2 Read Ports x Write Port x32 bits Bank x x Bank7 x x LBL LBL3 LBL2 LBL3 GBL 2: x2 D<3:> array selected, 255 deselected arrays leak Leakage power increases: depth of RF, scaling RF read path [Chatterjee et. al. VLI ymp. 3] 256 entry 64 bit 2R-W ported register file ingle-cycle throughput execution core loop Read operation performance critical Register File, WL Driver Energy Break-up RF total energy Dec % GBL 9% LBL 7% Read/Write elect Drivers 35% Bitcells 37% Clk 4% nm, typical corner, C WL driver energy break-up nm 7nm 3nm 22% 5% 3% witching Energy Leakage Energy RF total energy: WL drv.+ bitcells (72%); leakage dominated WL drv. energy 7nm breakup: 3% leakage, 7% switching 6

7 Low Power Word Line Driver Design Apply lkg. ctrl WL drv. section driver switches 255 drivers leak upply scaling non-min. L e stack effect RBB R D LBL R7 D7 OUT LBL, GBL 6% leakage 75% switching energy GBL GBL3 GBL4 GBL7 2: Goal use low power WL drivers, quantify delay penalty D RF Energy-Delay Tradeoffs with WL Drivers Normalized energy, delay plots RBB -7% +4% V CC scaling -25% -34% -33% -35% non. min-l e +2% +3% +3% Reference (baseline RF) -% -3% stack -3% Leakage Energy Total Energy Read Delay 7nm, 2R-W ported, 256 entry X 64 bit RF: Leakage energy: 3%~35% Read delay: 4%~2% RBB, non-min. L e : improved energy-delay tradeoffs Implementation Issues upply scaling: dual V CC for delay minimization, extra V CC generation and routing Non-min. L e : precise channel length control, gate area, capacitance and switching energy tack effect: gate area and switching energy, I ON degradation RBB: limited by optimal RBB voltage, generation routing of body bias voltage, triple well process ummary Leakage is increasing with technology scaling how stopper in further integration, performance everal techniques to reduce the leakage RBB is the most effective Future work: ub nm I GATE significant component of total leakage Modeling impact of techniques on I GATE 7