University of Central Florida. IEEE Electron Devices Colloqium Feb nd 2008

Transcription

1 University of Central Florida IEEE Electron Devices Colloqium Feb nd 2008 Steven H. Voldman, IEEE Fellow Latchup in Semiconductor Technology

2 It s Here!

3 Outline Latchup Basics CMOS Latchup Characterization Latchup Testing Latchup Computer Aided Design Concepts

4 CMOS Latch-up CMOS Concern increasing with Technology scaling and Integration - P+/N+ Scaling - STI Scaling - Substrate Concentration Scaling - Mixed Signal (RF, Analog, Digital) - System-on-Chip Integration - Non-native Power Supply Voltages

5 What is the fundamental problems today? Testing Characterization Design Integration CAD Methods for Verification and Checking

6 What is the CAD chip layout challenges? Identifying parasitic PNPNs Identifying guard ring Evaluate sensitivity of latchup concern Design optimization Co-synthesis

7 Latchup How Does it Happen? p + p + n + n + N-Well P- Substrate

8 Latchup Network PNP R well NPN R sub

9 Latchup I-V Characteristic I Holding point V on Negative Resistance Regime Trigger point V

10 External Latchup - Substrate Injection p + n + p + n + N-Well P- Substrate Voldman 2004

11 Alpha Particle Induced Latchup n + p + n + p + N-Well P- Substrate Voldman 2005

12 Single Event Upset Induced Latchup n + p + n + p + N-Well P- Substrate Voldman 2005

13 Lateral Bipolar Models Lindmayer-Schneider Model Introduces lateral and vertical components Dutton/Whittier Step Junction Introduces Vertical Step Junction N-/N++ or P-/P++ D.B. Estreich Model - Lateral Electric field Model influences lateral and vertical transport

14 Lateral and Vertical Transistor W B W E X J I D I V I L P- Epi N-Well P- Epi / P ++ Substrate Voldman 2004

15 Lateral and Vertical Transistor W B W E X J I D I V I L N-Well P-Well P- Substrate

16 Model: Lindmayer and Schneider Lindmayer and Schneider representation assumes that vertical current does not contribute to the bipolar current gain β = I C I B = α l I L ( 1 α ) l I L + I D + I V

17 Lateral and Vertical Transistor with STI X STI W E X J W B I D I V I L P-Well N-Well P- Substrate

18 Lateral Transistor: Non-field Assisted Early 1990 s: p' ( x) = p θ exp( x/ ) exp( / ) no Lp WB Lp sinh cosh ( x Lp) ( x Lp) sinh p no sinhwb ( x Lp) ( ) Lp ( V V ) 1 θ = exp T

19 E-Field Assist Transport Lateral E field 2 d p' dx2 ( x) E dp' ( x) ( x) V T dx S1x p' = Ae + 1 L 2 p S2x Be p '( x) = 0 S = 1,2 E 2V T ± E 2 + 2V T 1 L 2 p S 1,2 = λ ± λ 1 2

20 Lateral Electric Field Carrier Distribution ( λ1w B ) θ exp( λ2w B ) 2sinh( λ W ) ( ) exp p' x = p + no θ exp 1 2 x 2 B ( λ1w B ) θ exp( λ2w B ) 2sinh( λ ) (( λ + λ ) ) + exp + + p no exp W B (( λ λ ) x) S 1,2 = λ ± λ 1 2 S = 1,2 E 2V T ± E 2 + 2V T 1 L 2 p

21 Electric field Assisted α l Lateral Current Gain with E-field Assist ( λ ) λ2expwb α = l λ sinh + 1 B ( W λ ) λ cosh( W λ ) B 2

22 H-L and L-H Step Junctions Early latchup models pre-1980 did not address the influence of the p- / p+ substrate on the transport of the vertical transistor. Models developed by Gunn, Low, Dutton and Whittier addressed the step junction influence on the carrier transport in a p- / n- / n+ diode structure. D.B. Estreich included this effect into the CMOS latchup bipolar models.

23 Model: β with L-H Factor Lateral Bipolar Model with L-H Vertical Correction (Estreich) α I l L β = pnp + ( 1 α ) l I L F V I V ξ = Dp sub Dp epi LD epi LD sub F V = ND epi ND sub sinh γ + ξ coshγ coshγ + ξ sinh γ γ = W epi LD epi

24 Triple Bipolar Model Issues Lateral and Vertical Components Buried Layer Extension Vertical Bipolar Transistor Step Junctions Separation of Currents

25 Triple Well X STI W E X J W B W B W E I I V D N-Well I L I L I V P-Well N- Buried Layer P- Substrate

26 LATCHUP LATCHUP CRITERIA

27 Beta-Product Latchup Criterion βnβp I DD I DD I RSX + I RSXβn β I n + 1 RNW βn I RSX = ( Vbe) ( ) n R sx I RNW = ( Vbe) p ( ) R nw

28 Beta Product Space β pnp β pnp β npn = 1 Latchup SAFE β npn

29 Differential Latchup Criterion General Tetrode Condition Alpha Sum Form α * * fns + α fps 1 α * fns = αfns 1+ ren Rs α * fps = αfps r 1+ ep Rw

30 SAFE Region α* fps 1.0 α* fps + α* fns = 1 α fps SAFE Region Troutman 1984 α fns 1.0 α* fns

31 R nw R sx Resistance Space log (R well ) 100 kω 10 kω Holding Voltage 1 kω 100 Ω 10 Ω 10 Ω 100 Ω 1 kω 10 kω 100 kω log (R sub )

32 LATCHUP CHARACTERIZATION

33 Latchup Test Structures: PNPN 1.0 um 1.0 um 1um 1 um 1 um 1 um N+ P+ W N+ P+ 25 um N-Well Troutman 1982

34 Dual Well Latchup Structures n + p + n + p + N-Well P-Well P- Substrate

35 Merged Triple Well Latchup Structures n + p + n + p + N-Well P Epi N Layer

36 Merged Triple Well Latchup Structures n + p + n + p + N-Well P- Substrate N Layer

37 Merged Triple Well Vertical NPN n + p + n + p + N-Well P-Well N Layer N Layer P- Substrate

38 Latchup Test Structures: Triple Well 1um 1.0 um 1 um 1 um 1.0 um 1 um Isolated Epi 25 um N+ P+ W N+ P+ N-Well Voldman 2003

39 Latchup Structures Deep Trench n + p + n + p + DT N-Well DT Watson, Voldman IRPS 2004

40 Latchup Structures Trench Isolation n + p + n + p + TI N-Well TI P - Substrate Voldman IRPS 2005

41 LATCHUP SIMULATION

42 Latchup Simulation Structure

43 Latchup Equivalent Circuit Model Morris IRPS 2003

44 Simulation: PNP Overshoot Negative Resistance Regime Morris IRPS 2003

45 Simulation: Latchup State Morris IRPS 2003

46 Simulation: N+/P+ Study Morris IRPS 2003

47 Simulation: STI Scaling Morris IRPS 2003

48 LATCHUP LATCHUP PRODUCT TESTING

49 Transient Latchup Standard ESD Association Standard Practice for Protection of Electrostatic Discharge Susceptible Items: Transient Latchup Testing Component Level Supply Transient Simulation Transient Latchup Test determines the response to different waveforms using a TLU Amplifier

50 TLU Test Set up ESDA DSP5.4 - TLU

51 TLU Pulse Waveform Pulse Voltage (% of Max.) 0 10 Initial DC Level Max. Pulse Amplitude 50 Pulse Width Fall-Time Rise-Time Time ESDA DSP5.4 - TLU

52 TLU Latchup Test: V Undershoot -80 ma Surge Current ESDA DSP5.4 TLU TR

53 TLU Pulse Width Dependence No Latchup 75 us Latchup 62 us ESDA DSP5.4 TLU TR

54 Overshoot Latchup Sensitivity Product sensitive to overshoot and undershoot phenomena ESDA DSP5.4 TLU TR

55 Smart Power and HVCMOS CMOS Concern increasing with Integration - Smart Power integration of V applications with low voltage CMOS 0-5V - Integration Issues between DMOS, CMOS, and Bipolar Transistors

56 Smart Power and HVCMOS CMOS Concern increasing with Integration - Smart Power integration of V applications with low voltage CMOS 0-5V - Integration Issues between DMOS, CMOS, and Bipolar Transistors

57 Lateral and Vertical Issues Lateral and vertical transistors form in CMOS technology Dual Well - Lateral npn and pnp BJT Triple Well - Introduces vertical npn BJT

58 LATCHUP CIRCUIT SOLUTIONS

59 Circuit Solutions Power Supply Current Limit Power Supply Voltage Limit Multiple Power Supply Sequencing Circuitry Anti-Overshoot Circuit Anti-Undershoot Circuit Active Guard Rings Compensating Active Guard Rings S.Voldman 2007

60 LATCHUP MULTIPLE POWER SUPPLY SEQUENCING NETWORKS

61 Current Control Network

62 Power Supply Sequencing System

63 Sequence Independent Network

64 LATCHUP ACTIVE GUARD RINGS

65 Guard Rings - LDMOS to CMOS LDMOS n + p + N-well Guard Ring CMOS

66 Passive Guard Rings V SS V DD LDMOS n + p + N-well Guard Ring CMOS

67 Active Guard Rings V SS LDMOS n + p + N-well Guard Ring p + CMOS E(x)

68 Active Guard Rings

69 Active Compensation Guard Rings

70 Latchup Design System Latchup CAD methods are focused on the semiconductor device of PNPN and how the process affects it Latchup CAD layout/rules in the following areas: - PNPN Extraction - Inter-domain Latchup Interactions - Guard Ring Automation and Design - Internal Latchup Rules - External Latchup Rules

71 Latchup Computer Aided Design Layout Extraction Techniques

72 Latchup CAD Design Issues Identify PNPNs Identification of Guard Rings Improvement of Guard Rings Inter-domain parasitic problems Injection phenomena Satisfying ground rules

73 CAD Extraction of PNPNs Extraction of PNPN Sorting of PNPNs and Rules Integration with Circuit Schematics

74 Tong Li Latchup CAD Method Methodology useful for Latchup: Device Extraction - A method to extract actual devices. Stress Annotation - A method to determine the electrical potentials and classify the level of important stress conditions. Bipolar Junction Transistor Extraction - Extraction of parasitic bipolar transistors, and means to determine the critical transistors.

75 Extraction of Parasitic Bipolars T. Li UIUC

76 CAD Extraction Methodology (Zhan-Feng-Wu-Chen-Guan-Wang Method) Model Graphs (MG) formed for all devices Model Graphs formed for Parasitic PNPN Elements

77 Extraction Models P+/NW {} {NW} {P/NW} N+/SX {} {NW} P-Channel {Poly} MOSFET N-Channel MOSFET {P/NW} {N+} {Poly} {P/NW} {N+} PNPN {N+} {} {NW} {P/NW} R.Y. Zhan, A. Wang

78 CAD Guard Rings Checking of Guard Ring Rules Verification of Guard Ring Rules Post-Processing Generation of Guard Rings Guard Ring Parameterized Cells (PCell)

79 Guard Ring Resistance

80 Intra- and Inter-Domain Latchup and Design Rule Development

81 Inter-Circuit Latchup V SS N+ Junction in Diode ESD cell I/O cell ESD cell PMOS Driver Y. Huh EOS/ESD 2003

82 Inter-Circuit Latchup PMOS cap in 1.2V N-well Hot spot PMOS driver in 3.3V N-well Y. Huh EOS/ESD 2003

83 External Latchup Design Rules and Automation

84 Internal and External Latchup Internal Latchup - Injection phenomenon within the pnpn structure External Latchup Injection phenomenon outside of the pnpn strucure Internal latchup driven by process and design spacings External latchup driven by both external stimuli, and internal latchup parameters (e.g. process and spacings)

85 External Latchup: Domino Effect Mechler IRPS 2004

86 Latchup Network Holes PNP R well NPN Electrons R sub Voldman IRPS 2005

87 Cable Discharge Event (CDE) Induced External Latchup Weger IRPS 2003

88 ESD-Induced Latchup Weger IRPS 2003

89 Latchup Characterization CCD package pin current 5x flip-chip power supply board Stellari ITSFA 2003

90 Photo-emission Studies Stellari ITSFA 2003

91 Photon Emissions ESD NWSX contacts latchup I/O circuitry I/O circuitry ESD F. Stellari ISTFA 2003

92 Transfer Resistance p + p + n + n + N-Well NPN P- Substrate Transfer Resistance I sub R ij Troutman 1985

93 CAD Placement Optimization of Latchup contacts with chip optimization using Cost functional algorithms Optimization of well and contact spacing based on injector-to-circuit spacing

94 Latchup Ground Rules Injector Injector To PNPN N+ Contact P+/NW N+/NW N+ P+ N+ P+ N-Well P+ Contact

95 External Latchup SAFE Region Injected Current Latchup Region SAFE Region Injector-to-Collector Space Vashenko / Concannon

96 External Latchup Design Rules Implementation of ELUP Rules Spacing between well contacts (um) Des Man ASICs Distance from edge of injector shape (um) Brennan EOS/ESD 2004

97 ASIC Array I/O Brennan EOS/ESD 2004

98 Injector Dummy Design Levels INJECTO R I/O Brennan EOS/ESD 2004

99 Latchup Ground Rules - Orientation N+ Contact P+/NW N+/NW N+ P+ N+ P+ N-Well P+ Contact Injector To PNPN Injector

100 Latchup Ground Rules - Orientation Injector To PNPN Injector

101 CAD Global Placement Global placement based on PNPN density and circuit Latchup sub-function boundary evaluation methodology

102 Global Floor planning

103 CMOS Latch-up CMOS Concern increasing with technology scaling and Integration Solutions include - Test and Characterization - Circuit solutions - Design Synthesis and Integration - CAD tools for verification and checking - Circuit methodologies