Novel Comprehensive Analytical Probabilistic Models of The Random Variations in MOSFET s High Frequency Performances

Size: px
Start display at page:

Download "Novel Comprehensive Analytical Probabilistic Models of The Random Variations in MOSFET s High Frequency Performances"

Transcription

1 WSEAS RANSAIONS on IRUIS SYSEMS Novel omprehensive Analytical Probabilistic Models of he Rom Variations in MOSFE s Hih Frequency Performances RAWID BANHUIN Department of omputer Enineerin Siam University 35 Petchakasem Rd., Phasicharoen, Bankok HAILAND rawid_b@yahoo.com Abstract: In this research, the probabilistic models of the rom variations in MOSFE s hih frequency performance defined in terms of variations in ate capacitance transition frequency, have been proposed. Both rom dopant fluctuation process variation effects which are the major causes of the MOSFE s hih frequency characteristic variations have been taken into account. he short channel MOSFE has been focused. he proposed models which take the form of the comprehensive analytical expressions have been derived by usin the alphapower law which is more comprehensive than the conventional square law. he up to dated physical level fluctuation model has been adopted as the basis instead of the classical one. So, the model of ate capacitance variation has been refined. hese probabilistic models have been verified based on the IBM 90nm RF MOS technoloy by usin the Montearlo SPIE simulations the Kolmoorov Smirnof oodness of fit tests. hey are very accurate since they can fit the Montearlo SPIE based data distributions with 99% confidence. Hence, the proposed models have been found to be the potential mathematical tool for the statistical/variability aware analysis /desin of various MOSFE based hih frequency applications. KeyWor: Gate capacitance, Hih frequency, MOSFE, Short channel, Statistical desin, ransition frequency, Variability aware desin. 1 Introduction Recently, the subthreshold (weak inversion reion MOSFE has been adopted in many hih frequency circuits, system applications such as active inductor, active transformer, hih frequency filter, optical front en, clock/data recovery circuits Bluetooth devices. Of course, the performances of these hih frequency equipments are mainly determined by the hih frequency performances of their intrinsic MOSFE which can be determined by two major MOSFE s parameter entitled ate capacitance, transition frequency f. Obviously, imperfection in MOSFE s properties for example rom dopant fluctuation, line ede rouhness ate lenth rom fluctuation cause the rom variations in MOSFE s physical parameters such as threshold voltae which are crucial in the statistical/variability aware desin of MOSFE based applications. his is because the MOSFE s circuit level parameters such as drain current, I d transconductance, m are romly fluctuated due to the cited rom variations at the physical level. By this motivation, there are many previous researches on the modelin of such variations in the circuit level parameters for example, [1. he resultin models take the form of the comprehensive analytical expressions which have been found to be the convenient mathematical tools for the statistical/variability aware analysis/desin of various MOSFE based applications. However, these researches did not mention anythin about the variations in f even thouh they also exist. Furthermore, such f reatly determine the hih frequency performances of the MOSFE as mentined above. So, it can be seen that these previous models lack of some important information for hih frequency applications. Fortunately, there are previous studies in the characteristics of rom variations in both f for example [57 etc. he results of these previous studies are the raphical plots numerical measurement of such variations. Unfortunately, such results are not eneric since they are obtained from a certain technoloical basis. Furthermore, none of any related comprehensive analytical expressions that display the variation characteristics of both f has been derived. However, it has been pointed out in [7 that rom dopant fluctuation process variation effects such as line ede rouhness ate lenth rom fluctuation are the major causes of rom EISSN: 66X 69 Issue 3, Volume 1, March 013

2 WSEAS RANSAIONS on IRUIS SYSEMS variations in hih ftrequency characteristics of MOSFE includin f. In [8, simple formulas on f the relationship between the variance of that of f have been iven. Unfortunately, these formulas are incomprehensive since they do not display the physical level variation causes their relationships with the resultin variations in f. Accordin to the importance of both f alon with their possibility to be romly fluctuated as mentioned above, the comprehensive analytical modelin of their variations similarly to the modelin of the other parameters proposed in the previous researches such as [1, must be urently performed. Fortunately, the cited comprehensive analytical model of rom variation in has been proposed in [9. However, this model has been derived based on the classical model of variation [10 which is bein replaced by the state of the art ones such as that proposed in [11, so, a refinement is necessary. Furthermore, the similar modelin on f which is as important as that of has not been performed yet. Hence, due to the above motivation, the probabilistic models of rom variations in MOSFE hih frequency performance defined in terms of variations in f have been proposed in this research. Both rom dopant fluctuation process variation effects which are the major causes of the rom viriations in the MOSFE s hih frequency characteristics as stated in [7, have been taken into account. he short channel MOSFE has been focused since it reins the universe of the MOS technoloy nowadays. he proposed models which take the form of the comprehensive analytical expressions have been derived by usin the alphapower law [1 which is more comprehensive than the conventional square law. his alphapower law has also been previously adopted in [1, [ [9. he up to dated physical level fluctuation model proposed in [11 has been adopted as the basis instead of the classical one proposed in [10 which has been adopted in [9 as aforementioned. So, the model of variation in has been refined. he proposed models have been verified by usin the Montearlo SPIE simulations based on the IBM 90nm RF MOS process technoloy the KolmoorovSmirnof oodness of fit tests. he verifications have been performed based on both NMOS PMOS technoloies. hese models are very accurate since they can fit the Montearlo SPIE based data distributions with 99% confidence. Hence, the proposed models have been found to be the potential mathematical tool for the statistical/variability aware analysis/desin of various MOSFE based hih frequency applications. he Proposed Model In this section, the proposed models will be discussed. Before procee further, it is worthy to ive some foundation on the alphapower law of MOSFE s characteristic. Accordin to [1, [, [9 [1, this law which is more comprehensive than the classical square law stated that I d can be iven by I µ W L α d (1 λv ( Vs Vt (1 where µ,, V t, α λ denote the carrier mobility, the ate ide capacitance of the transistor, practical thresold voltae which is affected by rom dopant fluctuation process variation, velocity saturation index [1 channel lenth modulation parameter respectively. With such I d, the alphapower law based m is µ α 1 m α (1 λv ( Vs Vt ( W L At this point, the derivation of the proposed model can be started. Firstly, the analytical expression of has been derived. Similarly to [9 accordin to [13, can be iven by dq (3 dvs where Q denotes the ate chare [13. As in [9, accordin to [1, Q can be iven by Q d Vst ( Vs c t dvc QB,max 0 µ W L ( I where Q B,max denotes the maximum bulk chare [1. By usin (1 (, alphapower law based Q is [9 Q WL ( Vs Vt 3 1 λv 3 α Q B,max (5 So, can be iven by usin (3 (5 as follows [9 WL (3 α ( Vs 3 1 λv t α (6 EISSN: 66X 70 Issue 3, Volume 1, March 013

3 WSEAS RANSAIONS on IRUIS SYSEMS Hence, the alphapower law based f can be iven by usin ( (6 as f 3 αµ 8π (1 λv ( V (3 α L s 3 α 3 t (7 By takin both rom dopant fluctuation which is assumed that it ives the number of dopant atoms that obeys the Poisson distribution [15, process variation effects into account, the variations in MOSFE s properties existed. hese fluctuations include the rom variations in both f [7. Such variations are denoted by f respectively. Of course, both f become romly varied due to these variations which can be defined as follows (8, Nom (9 f f f, Nom So, it can be seen that these variations can be defined in terms of the different between their actual romly varied values their correspondin nominal counterparts denoted by,nom f,nom respectively. hese nominal values which can be ideally obtained by nelectin all imperfections of the MOSFE are obviously deterministic. With (6 (9, Δf can be iven as follows α α WL [( Vs Vt ( Vs VH ( (1 λv (3 α f 3 αµ 8π [( V s (1 λv α 3 t ( V s (3 α L H 3 α 3 (11 where V H denotes the nominal threshold voltae. By usin the state of the art model of physical level variation proposed in [11 the principle of rom variable transformation with (10 (11 as mappin functions, the probability density functions of Δf can be derived with the emphasis on the short channel MOSFE. hese probability density functions are α 1 H 3 3ε (1 λv( Vs ( δ π qw L N W ( α(3 α INV sub α 7ε (1 λv ( Vs H δ exp 3 8qINVNsubW WL ( α (3 α (1 f 8 3πε W L (3 α ( δf [3 µ q (1 λv ( V N sub W exp{ [9µ INV (1 λv α 3 α 7 q INVNsubW 96π ε WL (3 α δf ( V s s ( α H ( α H } α 3 α (13 where δ, δf, q, ε, N sub, INV, W, W L denote any sampled value of, that of f, electron chare, ate ide permittivity, channel impurity concentration, electrical ate dielectric thickness, channel width, letion width channel lenth respectively [11. Hence, it can be stated that the proposed model which probabilistically describes the rom dopant fluctuation process variation effects induced rom variation in the similar variation in f can be iven by (1 (13 which many physical parameters have been incorporated. At this point, the probabilistic models of rom variations in MOSFE s hih frequency performance which can be defined in terms of variations in f have been derived in the form of the probability density functions which are the comprehensive analytical expressions includin many physical level parameters. ompared to the previous studies such as those in [57 which presents the study results of variation in in terms of raphical plots numerical measurements obtained from a certain technoloical basis, the proposed model is a more analytic, comprehensive eneric result as it is an analytical expression in term of many physical variables without any reference to a certain technoloy node but to the eneral MOS technoloy. hese models are more comprehensive than that proposed in [8 as they contain several physical level parameters so, the physical causes of such hih frequency performance variation have been revealed. his clarifies the exploration of the cited hih frequency performance variation. hese models are also as comprehensive as those in [ [3 but they emphasize on the hih frequency operation. Finally, the proposed models are more complete up to dated than that proposed in [9 which mention nothin on the variation in f, also relies on the outdated physical level fluctuation model [10. For fittin of the variation in, part of the proposed models for this variation is more accurate than that mentioned in [9 due to the better KolmoorovSmirnof test statistic obtained from the EISSN: 66X 71 Issue 3, Volume 1, March 013

4 WSEAS RANSAIONS on IRUIS SYSEMS data fittin usin a part of the proposed ones as will be seen later. As this model takes the form of the probability density function, much meaninful statistical information of the variations in f can be obtained. For examples, it can be seen that both variations in f have the followin means variances σ f σ where δ ( δ dδ 0 (1 ( δ 3 qinvnsubw WL ( α (3 α α 7ε (1 λv ( V f ( δf f 9µ q 19π, INV ε s ( δ dδ H (15 δ f ( δf dδf 0 (16 N f sub 7 W f ( δf dδf α 3 α WL (3 α ( V σ, f s, V (1 λv ( α H (17 σ f denote mean variance of alon with those of f respectively. Furthermore, the analytical expressions of many other meaninful statistical parameters such as moments of various orders, skewness kurtosis can also be obtained by simply apply the conventional mathematical statistic to the proposed model with the required mathematics can be performed even by h calculation. hese are the major benefits of this model. For the desinin with electronic AD tools, this model can serves as the mathematical basis for the desired simulations. he required computational effort is potentially smaller than that of the brute force Montearlo analysis based on the rom variations of the parameters at the physical level which is time expensive as mentioned in [16. Hence, the proposed models have been found to be the potential mathematical tool for the statistical/variability aware analysis/desin of various MOSFE based hih frequency applications. In the subsequent section, the verification of the proposed model will be discussed. 3 he Verification Similarly to [, 3, 9, the verification of the proposed model has been performed in both qualitative quantitative aspects. In the qualitative sense, the estimated distributions of rom variations in f obtained from the models have been raphically compared to their counterparts obtained from the Montearlo SPIE simulations of the benchmark circuits. On the other h for the quantitative point of view, numbers of KolmoorovSmirnof oodness of fit test (KStest have been performed by usin the cumulative distributions of such rom variations obtained from the same set of Montearlo SPIE simulations for the qualitative verifications. It should be mentioned here that both NMOS PMOS technoloies have been considered. he verification has been performed based on the up to dated IBM 90nm RF MOS technoloy by the model parameterization with the IBM 90nm RF MOS process parameters the usae of the BSIM.3 based benchmark circuits parameterized by the SPIE parameters extracted from such IBM 90nm RF MOS process. hese necessary parameters are provided by the MOSIS. Since the KStest relies on the cumulative distributions, it is worthy to derive the cumulative distribution function forms of the proposed models at this point. With the conventional mathematical statistic, they can be iven by DF ( δ δ ( u du 3 1 8qINV N subwwl ( α 1 erf 7ε (1 λv ( Vs DF ( δf δf f f ( u du (3 α α H 1 9µ q INVNsubW α 3 α (1 λv 1 erf 7 ( α 96π ε WL (3 α ( Vs VH 1 δ 1 δf (18 (19 Note that erf ( x denotes the error function of any arbitrary variable, x which can be mathematically defined as x erf ( x exp( u du. (0 π 0 EISSN: 66X 7 Issue 3, Volume 1, March 013

5 WSEAS RANSAIONS on IRUIS SYSEMS Accordin to [17, 18, the stratey of the KStest is to performed the comparison of the KS test statistic (KS the critical value (c where it can be stated that any model fits its taret data set if only if its KS is not exceed its c [17, 18. For this research, KS can be defined as KS max{ DF ( δx DF ( δx } (1 δx x circuit x model where x can be either or f while DF x (δx DF model x(δx represent the circuit cumulative distribution of any x obtained from the proposed models the counterpart obtained from the simulation of the benchmark circuit respectively. Furthermore, as the confidence level of the test is 99%, c can be iven by [ c ( n where n denotes the number of runs for the Montearlo SPIE analysis. Similarly to [9, it should be mentioned here that the model verification has been performed by usin n 3000 which yiel c In the upcomin subsections, the verification of the model based on NMOS technoloy the PMOS counterpart will be respectively discussed. 3.1 NMOS based model verification As in [9, for the verification the model s accuracy in the prediction of rom variation in, the chosen benchmark circuit is a sinle MOSFE with both drain source have been ac rounded where as the ate terminal has been fed by the ac input voltae. he input admittance which takes into account can be seen by lookin into the input terminal of this benchmark circuit. his methodoloy of findin the MOSFE s input admittance by usin SPIE analysis has also been used in [19. For NMOS technoloical basis, the core of this circuit can be icted in Fi.1. As the input conductance is extremely small for conventional MOSFEs, can be apprimately iven as follows [9 Y 1 I in in (3 jω jω Vin where Y in, I in V in denote the input admittance, input current input voltae respectively. Similarly to [9, the variation in the formerly defined above obtained from the Montearlo SPIE simulation of this circuit at 1 GHz has been adopted as the circuit based Δ for NMOS technoloy. On the other h, the chosen benchmark circuit for verifyin the model s accuracy in the prediction of rom variation in f is also a sinle MOSFE but both drain ate have been fed with their own ac voltaes where as the source terminal has been ac rounded. hese ac voltaes applied at the ate drain are V s V respectively. For NMOS technoloical basis, the core of this circuit can be icted in Fi.. From this circuit, f can be defined as the frequency which the current ain is unity. Alternatively, it is the frequency which the manitude of the small sinal input current is equal to that of the output one. his methodoloy has also been adopted in findin f of EP s enhancement mode GaN power transistor with SPIE simulation [0. Of course, the correspondin variation in f obtained from the Montearlo SPIE simulation of this circuit has been adopted as the circuit based Δf for NMOS technoloy. It should be mentioned here that these benchmark circuit uses the nominal channel lenth (L of 100nm which is closed to the minimum allowable value alon with the nominal aspect ratio (W/L of 50. For both circuits, the dc supplies of ±0.5 v have been used. Finally, these simulation strateies, parameters settin biasin condition have been used for the PMOS based model verification. By proceed in the similar manner to the model verifications in [, 3, 9, the raphical comparisons for the distributions Δ Δf with respected to their nominal values, denoted by /,Nom f /f,nom respectively are icted in Fi. 3 Fi. for the qualitative NMOS based verification. For this NMOS case, it can be seen that stron areements between the predicted distributions obtained from the proposed model the counterparts obtained from the Montearlo SPIE analysis of the benchmark circuits can be observed. Hence, proposed model has been qualitatively verified as hihly accurate for NMOS technoloy. For the quantitative verification, it can be seen by usin (19 that the resultin KS for x can be found as KS that for x f is KS which are both smaller than c his means that the proposed model can fit the variations in f obtained from the NMOS based benchmark circuits with 99% confidence. Furthermore, a ood areement can also be seen from the comparative plots for the cumulative distributions of /,Nom f /f,nom icted in Fi.5 Fi.6 respectively. At this EISSN: 66X 73 Issue 3, Volume 1, March 013

6 WSEAS RANSAIONS on IRUIS SYSEMS point, the proposed model verified as hihly accurate for NMOS technoloical basis. 3. PMOS based model verification For the model verification based on PMOS technoloy, the benchmark circuits similarly to those icted in Fi.1 Fi. can be used. hese circuits can be icted in Fi.7 Fi.8 which are adopted for verifyin the model s accuracy to predict the variation the accuracy for the prediction of such variation in f respectively. It should be mentioned here that, f their variations in this case can be determined from the benchmark circuits in the similar manner to those of the NMOS based verification. Furthermore, the similar verification methodoloy, parameters settin biasin condition applied to the previous NMOS based scenario can also be used for this PMOS based case. Also similarly to the NMOS based case, the raphical comparisons for the distributions of /,Nom f /f,nom respectively are icted in Fi.9 Fi.10 for the qualitative PMOS based verification which stron areements between those obtained from the proposed model the counterparts obtained from the Montearlo SPIE analysis of the benchmark circuits has also been observed. Hence, proposed model has been qualitatively verified as hihly accurate for PMOS technoloy. For the quantitative verification, it can be seen that KS for x can be found as KS that for x f is KS which are also smaller than c his means that the proposed model can fit the variations in f obtained from the PMOS based benchmark circuits with 99% confidence. Similarly to the NMOS based case, a ood areement can also be seen from the comparative plots for the cumulative distributions of /,Nom f /f,nom icted in Fi.11 Fi.1 respectively. At this point, the proposed model is verified as also hihly accurate for PMOS technoloy. Before leavin this section, it should be mentioned here that the resultin KS statistics for the model of variation in proposed in this research iven by KS for the NMOS based verification KS for the PMOS based one as mentioned above are lower than their correspondin counterparts formerly proposed in [9 iven by KS KS for NMOS based data fittin PMOS based one respectively. Accordin to [17, 18, this means that the refined model for the variation of proposed in this research is better fit to both NMOS based data PMOS based one due to its lower statistics so, it is more accurate than the previous model for the variation in proposed in [9. his is a result of the refinement in the model for variation. Fi.1. NMOS benchmark circuit for verifyin the model of I out V s Fi.. NMOS benchmark circuit for verifyin the model of f Probability I in V /,Nom(% Fi.3. NMOS based comparative distribution plots for /,Nom : he model based (line v.s. he benchmark circuit based (historam EISSN: 66X 7 Issue 3, Volume 1, March 013

7 WSEAS RANSAIONS on IRUIS SYSEMS Probability I in Y in f /f,nom(% Fi.. NMOS based comparative distribution plots for f /f,nom : he model based (line v.s. he benchmark circuit based (historam Fi.7. PMOS benchmark circuit for verifyin the model of I out umulative probability I in V s /,Nom(% Fi.5. NMOS based comparative cumulative distribution plots for /,Nom : he model based (line v.s.he benchmark circuit based (dots Fi.8. PMOS benchmark circuit for verifyin the model of f Probability umulative probability /,Nom(% f /f,nom(% Fi.6. NMOS based comparative cumulative distribution plots for f /f,nom : he model based (line v.s. he benchmark circuit based (dots Fi.9. PMOS based comparative distribution plots for /,Nom : he model based (line v.s. he benchmark circuit based (historam EISSN: 66X 75 Issue 3, Volume 1, March 013

8 WSEAS RANSAIONS on IRUIS SYSEMS Probability f /f,nom(% Fi.10. PMOS based comparative distribution plots for f /f,nom : he model based (line v.s. he benchmark circuit based (historam umulative probability Discussion In this section, some discussion reardin to the proposed model, some interestin applications of this model the results obtained from the model verification will be iven. Firstly, it can be obviously seen from the proposed models that many physical level parameters have been incorporated. Since these models describe the behavior of hih frequency performance variations these physical level parameters are ended on the fabrication technoloy of the MOSFE, it can be seen that such technoloy sinificantly affects the hih frequency performance variation. As mentioned above, f become romly varied due to f. Mathematically, they become rom variables. By usin (8, (9 the proposed models, their probability density functions can be simply derived as follows 3 3ε (1 λv ( V 7ε (1 λv ( V exp 8qINVNsubW α 1 s H ( c π INVqW L NsubW ( α(3 α ( s 3 ( c α H WL ( α (3 α, Nom /,Nom(% Fi.11. PMOS based comparative cumulative distribution plots for /,Nom : he model based (line v.s. he benchmark circuit based (dots umulative probability 8 3πε W L (3 α f( φ [3 µ q (1 λv ( V N sub W INV 96π εwl (3 α ( φ f exp{ [9µ q N W (1 λv α 3 α INV 0.5 ( V 7 s 3.5 sub s ( α H ( α H, Nom } α 3 α (5 where c denotes any sample values of f respectively. Furthermore, it can be observed from (15 (17 which have been derived from the proposed model that 3 σ (6 WL 1 σ (7 (1 λv 1 f 7 σ (8 WL f /f,nom(% Fi.1. PMOS based comparative cumulative distribution plots for f /f,nom : he model based (line v.s. he benchmark circuit based (dots σ f ( 1 λv (9 So, it can be seen that shrikin the transistor dimension can reduce the variation in with EISSN: 66X 76 Issue 3, Volume 1, March 013

9 WSEAS RANSAIONS on IRUIS SYSEMS increasin of variation in f as a penalty. Furthermore, application of the trendy low voltae desinin methodoloy which uses low supply voltae yiel the reduction in f variation with increasin in variation as a price to pay. So, these tradeoff issues must be taken into account in the desinin of MOSFE based hih frequency applications. For the in th exploration of the statistical relationship between the variation in the one in f, their correlation coefficient denoted by ρ must be investiated. Such, f ρ, f can be defined as E[( ( f f ρ, f (30 σ σ f where E[( ( f f is the covariance of both variations denoted by ov(δ, Δf which in turn can be defined as maximum oscillation frequency which is also an important hih frequency parameter can be precisely understood by usin the proposed model since such frequency is a function of f. his point can be demonstrated as follows, the maximum oscillation frequency denoted by f max is a critical hih frequency parameter when the ate parasitic resistance has been taken into account. Let such ate parasitic resistance be denoted by R, f max can be iven as a function of f as follows f f max (3 8π d R where d denotes the capacitance from drain to ate which is totally differrent from that from ate to drain denoted by d [1. he reason for this is that d d can be iven accordin to [1 by Q d d (35 V ov(, f E[( ( f ( δ ( δf f ( δ, δf dδ dδf, f f (31 d Q (36 V d ( δ, δf which denotes the joint, f probability density function of both variations can be found from the proposed model by solvin the followin equations δ f ( δ, δf dδf (, (3 f δ f f ( δ, δf dδ (, (33 By usin the proposed model alon with (1(17 which are obtained from this model for, σ, f, σ respectively, the manitude of such correlation coefficient has been found to be unity. his means that there exists a very stron statistical relationship between both variations. Secondly, apart from obtainin meaninful statistical parameters of f as formerly mentioned, the proposed model can serve as a basis for understin the behavior of the similar variations in other hih frequency parameters. For example, the behavior for such variation in the f Note that Q d denotes the drain chare where as V V d denote the ate drain voltaes respectively [1. It can be obviously seen from (35 (36 that d d. Since f is undeniably arised due to both rom dopant fluctuation process variation effects, the maximum oscillation frequency can be practically iven by f f f, Nom max ( f (37 8πd R where, fmax ( f denotes such practical maximum oscillation frequency which is undeniably fluctuated accordin to f induced by rom dopant fluctuation process variation effect while f,nom denotes the nominal value of f. So, the rom variation in the square of such f max denoted by can be simply found as f max f f max (38 8π d R By usin (17 which obtained from the proposed model, the variance of can be simply iven by f max EISSN: 66X 77 Issue 3, Volume 1, March 013

10 WSEAS RANSAIONS on IRUIS SYSEMS 9µ q INVNsubW α 3 α (1 λv [ f max 7 ( α 188π drε WL (3 α ( Vs H Var (39 Hence, it can be seen at this point that the behavior of rom variation in f max is now well understood via the above information on the variation of f max which has been obtained by usin the proposed model. For obtainin an in th insiht, the probability density function of fmax ( f denoted by ( φ max which completely describes the fluctuation in the maximum oscillation frequency analytically, can also be obtained by usin the proposed model. Let ø max denotes any sampled value of fmax ( f, by usin the principle of rom variable transformation with (37 as a mappin function, φ can be iven by ( φ max ( max π drφmax ( φmax f, Nom/8π dr 16 exp[ (0 σ ( σ /8π R f f where σ f can be found by usin (17 which can be obtained from the proposed model. At this point, it can be obviously seen that ( φ max which describes the fluctuation in the maximum oscillation frequency, can be simply obtained by usin the proposed model. Furthermore, the proposed model is applicable as the mathematical foundation for the modelin of the hih frequency performance mismatch of the lobally spaced MOSFEs for example, the mismatch in f of such spaced devices. Let these mismatches be denoted by D Df respectively. Since these transistors have similar local variations low correlation as they are lobally spaced, the distributions of D Df can be simply iven by usin the proposed model as follows d α 1 H 3 3ε (1 λv( Vs D( d πinvqw L NsubW ( α(3 α (1 α 7ε (1 λ ( V Vs VH d exp 3 16qINVNsubW WL ( α (3 α Df 3πε W L (3 α ( df [3µ q (1 λv ( V N sub W INV (1 λv α 3 α 7 INV NsubW 0.5 ( V s 3.5 s ( α H ( α H 8π ε WL (3 α df exp{ [9µ q } α 3 α ( where d df denote any sampled values of D Df respectively. Now, the discussion reardin to the results obtained from the model verification will be iven. It can be seen from the formerly shown Monte arlo SPIE analysis results that the variations in both ate capacitance transition frequency follows the Gaussian distribution as icted in Fi.3, Fi., Fi.9 Fi.10. Similarly to the results proposed in [9, the maximum percentae of variation in denoted by Max[ / obtained from the NMOS based benchmark circuit for verifyin the model of icted in Fi.1 is hiher than its counterparts obtained from the PMOS based one shown in Fi.7. hese maximum percentaes are similar to those proposed in [9 since they have been enerated from the ceteris paribus scenario. Furthermore, the similar relationship can be seen amon the maximum percentae of variation f denoted by Max[ f /f obtained from the NMOS based benchmark circuit for verifyin the model of f shown in Fi. its counterpart obtained from the PMOS based circuit icted in Fi.8. All of these maximum percentaes are concluded in able I. It can be observed from these percentaes that PMOS technoloy is more robust to the rom dopant fluctuation process variation effects than its NMOS counterpart due to its lower variations. At this point, the validity of the similar conclusion proposed in [9 has been emphasized. Furthermore, it has been observed that the KS test statistics for the PMOS based verification are smaller than their NMOS based counterparts as can be seen in able II. his means that the proposed model is better fit to the PMOS based data than the NMOS based one due to the smaller statisitics. So, it can be seen that this model can predict the variations for PMOS transistor with hiher accuracy than the similar prediction for the NMOS one. Finally, the one of the tentative further researches is to perform the similar modelin with specific orientation to the nanometer level MOS technoloy as the modelin for other parameters such as I d m of the nanoscale MOSFE which have been proposed in [, 3. EISSN: 66X 78 Issue 3, Volume 1, March 013

11 WSEAS RANSAIONS on IRUIS SYSEMS able 1. Max[ / Max[ f /f Max[ / (% Max[ f /f (% NMOS PMOS NMOS PMOS able. he comparison of KS test statistics From verification From f verification NMOS PMOS NMOS PMOS onclusion he probabilistic models of rom variations in MOSFE s hih frequency performance defined in terms of variations in f have been proposed. Both rom dopant fluctuation process variation effects which are the crucial causes of the MOSFE s hih frequency characteristic variations [7 have been taken into account. he state of the art short channel MOS technoloy has been focused. hese models have been derived by usin the alphapower law which has been proposed in [1 has also been previously adopted in [1, [ [9. he modern physical level variation model proposed in [11 has been adopted as the modelin basis instead of the classical one in [10. his ives the sinificant refinement in the model of variation in compared to the previous one proposed in [9. he proposed probabilistic models have been verified with both NMOS PMOS technoloies based on the IBM 90nm RF MOS process by usin the Montearlo SPIE simulations alon with the KS tests. hese models are very accurate since they can fit the Montearlo SPIE based data distributions with 99% confidence. Hence, the proposed models have been found to be the convenient mathematical tool for the statistical/variability aware analysis/desin of various MOSFE based hih frequency applications such as active inductor, active transformer, hih frequency filter, optical front en, clock/data recovery circuits many Bluetooth devices. Acknowledement he author would like to acknowlede Mahodol University, hail for online database service. References: [1 H. Masuda,. Kida S. Ohkawa, omprehensive matchin characterization of analo MOS circuits, IEIE rans. Fundamental, Vol. E9A, No., 009, pp [ R. Banchuin, Process induced rom variation models of nanoscale MOS performance: efficient tool for the nanoscale reime analo/mixed sinal MOS statistical/variability aware desin, Proceedins of the 011 International onference on Information Electronic Enineerin, 011, pp. 61 [3 R. Banchuin, omplete circuit level rom variation models of nanoscale MOS performance, International Journal on Information Electronic Enineerin, Vol. 1, No.1, 011, pp [ K. Haseawa, M. Aoki,. Yamawaki, S. anaka, Modelin transistor variation usin a power formula its application to sensitivity analysis on harmonic distortion in differential amplifier, Analo Interated ircuits Sinal Processin, 011. [5 A. R. Brown A. Asenov., apacitance fluctuations in bulk MOSFEs due to rom discrete dopants, Journal of omputer Electronic (008, Vol.7, 008, pp [6 Y. Li.H. Hwan, Hihfrequency characteristic fluctuations of nanomosfe circuit induced by rom dopants, IEEE ransaction on Microwave heory echniques, Vol. 56, No.1, 008, pp [7 M.H. Han, Y. Li.H. Hwan, he impact of hihfrequency characteristics induced by intrinsic parameter fluctuations in nano MOSFE device circuit, Microelectronics Reliability, Vol.50, 010, pp [8 H.S. Kim,. hun, J. Lim, K. Park, H. Oh, H.K. Kan, haracterization modelin of RFperformance (f fluctuation in MOSFEs, IEEE Electronic Devices Letters, Vol. 30, No.8, 009, pp [9 R. Banchuin, he novel analytical probabilistic model of rom variation in MOSFE s hih frequency performance, Proceedins of the IASED Asian onference on Modelin, Identification ontrol, 01, pp. to be published. [10 M. J. M. Pelrom, A.. J. Duinmaijer, A. P. G.Welbers, Matchin properties of MOS transistors, IEEE Journal of SolidState ircuits, Vol., No.5, 1989, pp EISSN: 66X 79 Issue 3, Volume 1, March 013

12 WSEAS RANSAIONS on IRUIS SYSEMS [11 K. akeuchi, A. Nishida. Hiramoto, Rom fluctuations in scaled MOS Devices, Proceedins of the 009 International onference on Simulation of Semiconductor Processes Devices, 009, pp [1. Sakurai A. R. Newton, Alphapower law MOSFE model its applications to MOS inverter delay other formulas, IEEE Journal on SolidState ircuits, Vol. 5, No., 1990, pp [13 H. Abebe, H. Morris, E. umberbatch V. yree, ompact ate capacitance model with polysilicon letion effect for MOS device, Journal of Semiconductor echnoloy Science, Vol 7, No.3, 007, pp [1 R.. Howe. G. Sodini, Microelectronics: An Interated Approach, Prentice Hall, [15 L. Weifen S. Linlin, Modelin of current mismatch induced by rom dopant fluctuation in nanomosfes, Journal of Semiconductor, Vol. 3, No.8, 011, pp [16 G. ijan,. uma A. Burmen, Modelin simulation of MOS transistor mismatch, Proceedins of the 6 th Eurosim onress on Modellin Simulation, 007, pp. 18 [17. Altiok B. Melamed, Simulation Modelin Analysis with ARENA, Academic Press, 007. [18 S.A. Kluman, H.H Panjer G.E. Willmot, Loss Models: From Data to Decisions, Wiley, 008 [19 H hoi, J.S. Goo,.Y. Oh, R.W. Dutton, A. Bayoumi, M. ao, P.V. Voorde, D. Vook.H. Diaz, MOS V characterization of ultrathin ate ide thickness ( nm, IEEE Electronic Devices Letters, Vol. 0, No.6, 1999, pp. 96. [0 R. Beach, A. Babakhani R. Strittmatter, ircuit simulation usin EP device models, Application notes: ircuit Simulation, Device Models, 011, pp. 11. [1 D.L. Pulfrey, Understin Modern ransistors Diodes, ambride University press, 010 EISSN: 66X 80 Issue 3, Volume 1, March 013

Analytical Prediction Formula of Random Variation in High Frequency Performance of Weak Inversion Scaled MOSFET

Analytical Prediction Formula of Random Variation in High Frequency Performance of Weak Inversion Scaled MOSFET Analytical Prediction ormula of Random Variation in Hih reuency Performance of Weak Inversion Scaled MOSET Rawid Banchuin * and Rounsan Chaisricharoen * Department of Computer Enineerin, am University,

More information

A Novel Complete High Precision Standard Linear Element-Based Equivalent Circuit Model of CMOS Gyrator-C Active Transformer

A Novel Complete High Precision Standard Linear Element-Based Equivalent Circuit Model of CMOS Gyrator-C Active Transformer WSEAS TANSATIONS on IUITS and SYSTES A Novel omplete Hih Precision Standard Linear Element-Based Equivalent ircuit odel of OS Gyrator- Active Transformer AWID BANHUIN Department of omputer Enineerin Siam

More information

Generic Stochastic Effect Model of Noise in Controlling Source to Electronically Controlled Device

Generic Stochastic Effect Model of Noise in Controlling Source to Electronically Controlled Device Generic Stochastic Effect Model of oise in Controlling Source to Electronically Controlled Device RAWID BACHUI Department of Computer Engineering Siam University 35 Petchakasem Rd., Phasi-charoen, Bangkok

More information

ANALYSIS OF POWER EFFICIENCY FOR FOUR-PHASE POSITIVE CHARGE PUMPS

ANALYSIS OF POWER EFFICIENCY FOR FOUR-PHASE POSITIVE CHARGE PUMPS ANALYSS OF POWER EFFCENCY FOR FOUR-PHASE POSTVE CHARGE PUMPS Chien-pin Hsu and Honchin Lin Department of Electrical Enineerin National Chun-Hsin University, Taichun, Taiwan e-mail:hclin@draon.nchu.edu.tw

More information

Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs

Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs PACS 85.0.Tv Impact of sidewall spacer on ate leakae behavior of nano-scale MOSFETs Ashwani K. Rana 1, Narottam Chand, Vinod Kapoor 1 1 Department of Electronics and Communication, National Institute of

More information

An Improved Logical Effort Model and Framework Applied to Optimal Sizing of Circuits Operating in Multiple Supply Voltage Regimes

An Improved Logical Effort Model and Framework Applied to Optimal Sizing of Circuits Operating in Multiple Supply Voltage Regimes n Improved Loical Effort Model and Framework pplied to Optimal Sizin of Circuits Operatin in Multiple Supply Voltae Reimes Xue Lin, Yanzhi Wan, Shahin Nazarian, Massoud Pedram Department of Electrical

More information

Is quantum capacitance in graphene a potential hurdle for device scaling?

Is quantum capacitance in graphene a potential hurdle for device scaling? Electronic Supplementary Material Is quantum capacitance in raphene a potential hurdle for device scalin? Jaeho Lee 1,,, Hyun-Jon hun 1,3, (), David H. Seo 1, Jaehon Lee,4, Hyuncheol Shin, Sunae Seo 1,5,

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

V DD. M 1 M 2 V i2. V o2 R 1 R 2 C C

V DD. M 1 M 2 V i2. V o2 R 1 R 2 C C UNVERSTY OF CALFORNA Collee of Enineerin Department of Electrical Enineerin and Computer Sciences E. Alon Homework #3 Solutions EECS 40 P. Nuzzo Use the EECS40 90nm CMOS process in all home works and projects

More information

EE 435 Lecture 13. Cascaded Amplifiers. -- Two-Stage Op Amp Design

EE 435 Lecture 13. Cascaded Amplifiers. -- Two-Stage Op Amp Design EE 435 Lecture 13 ascaded Amplifiers -- Two-Stae Op Amp Desin Review from Last Time Routh-Hurwitz Stability riteria: A third-order polynomial s 3 +a 2 s 2 +a 1 s+a 0 has all poles in the LHP iff all coefficients

More information

Stability and Bifurcation Analysis of Electronic Oscillators: Theory and some Experiments

Stability and Bifurcation Analysis of Electronic Oscillators: Theory and some Experiments ISE'9 J. Kenne J.. hedjou K. Kyamakya University of Dschan (ameroon ( University of Klaenfurt (Austria ( Stability and Bifurcation Analysis of Electronic Oscillators: heory and some Eperiments Abstract.

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

Modeling of High Voltage AlGaN/GaN HEMT. Copyright 2008 Crosslight Software Inc.

Modeling of High Voltage AlGaN/GaN HEMT. Copyright 2008 Crosslight Software Inc. Modelin of Hih Voltae AlGaN/GaN HEMT Copyriht 2008 Crossliht Software Inc. www.crossliht.com 1 Introduction 2 AlGaN/GaN HEMTs - potential to be operated at hih power and hih breakdown voltae not possible

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

Analysis and Design of Analog Integrated Circuits Lecture 7. Differential Amplifiers

Analysis and Design of Analog Integrated Circuits Lecture 7. Differential Amplifiers Analysis and Desin of Analo Interated Circuits ecture 7 Differential Amplifiers Michael H. Perrott February 1, 01 Copyriht 01 by Michael H. Perrott All rihts reserved. Review Proposed Thevenin CMOS Transistor

More information

EECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i-

EECS240 Spring Lecture 21: Matching. Elad Alon Dept. of EECS. V i+ V i- EECS40 Spring 010 Lecture 1: Matching Elad Alon Dept. of EECS Offset V i+ V i- To achieve zero offset, comparator devices must be perfectly matched to each other How well-matched can the devices be made?

More information

Chapter 4 Field-Effect Transistors

Chapter 4 Field-Effect Transistors Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

Effect of Frequency and Moisture Variation on Dielectric Properties of Pearl Millet in Powder Form

Effect of Frequency and Moisture Variation on Dielectric Properties of Pearl Millet in Powder Form J. Environ. Nanotechnol. Volume (013) 01-05 pp. ISSN (Print) : 79-0748 ISSN (Online) : 319-5541 Effect of Frequency and Moisture Variation on Dielectric Properties of Pearl Millet in Powder Form Nidhi

More information

CHARACTERIZATION, MODELING, AND SIMULATION OF In 0.12 Al 0.88 N/GaN HEMTs

CHARACTERIZATION, MODELING, AND SIMULATION OF In 0.12 Al 0.88 N/GaN HEMTs CHARACTERIZATION, MODELING, AND SIMULATION OF In 0.12 Al 0.88 N/GaN HEMTs Marián Molnár 1,2, Gesualdo Donnarumma 1,Vassil Palankovski 1, Ján Kuzmík 1,3, Daniel Donoval 2, Jaroslav Kováč 2, and Siefried

More information

MODELING A METAL HYDRIDE HYDROGEN STORAGE SYSTEM. Apurba Sakti EGEE 520, Mathematical Modeling of EGEE systems Spring 2007

MODELING A METAL HYDRIDE HYDROGEN STORAGE SYSTEM. Apurba Sakti EGEE 520, Mathematical Modeling of EGEE systems Spring 2007 MODELING A METAL HYDRIDE HYDROGEN STORAGE SYSTEM Apurba Sakti EGEE 520, Mathematical Modelin of EGEE systems Sprin 2007 Table of Contents Abstract Introduction Governin Equations Enery balance Momentum

More information

EE 330 Lecture 33. Basic amplifier architectures Common Emitter/Source Common Collector/Drain Common Base/Gate. Basic Amplifiers

EE 330 Lecture 33. Basic amplifier architectures Common Emitter/Source Common Collector/Drain Common Base/Gate. Basic Amplifiers 33 Lecture 33 asic aplifier architectures oon itter/source oon ollector/drain oon ase/gate asic plifiers nalysis, Operation, and Desin xa 3 Friday pril 3 eview Previous Lecture Two-Port quivalents of Interconnected

More information

ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 342 Electronic Circuits. 3. MOS Transistors ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

Experimental and Computational Studies of Gas Mixing in Conical Spouted Beds

Experimental and Computational Studies of Gas Mixing in Conical Spouted Beds Refereed Proceedins The 1th International Conference on Fluidization - New Horizons in Fluidization Enineerin Enineerin Conferences International Year 007 Experimental and Computational Studies of Gas

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

More information

Efficient method for obtaining parameters of stable pulse in grating compensated dispersion-managed communication systems

Efficient method for obtaining parameters of stable pulse in grating compensated dispersion-managed communication systems 3 Conference on Information Sciences and Systems, The Johns Hopkins University, March 12 14, 3 Efficient method for obtainin parameters of stable pulse in ratin compensated dispersion-manaed communication

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

A Compact Gate Tunnel Current Model for Nano Scale MOSFET with Sub 1nm Gate Oxide

A Compact Gate Tunnel Current Model for Nano Scale MOSFET with Sub 1nm Gate Oxide A Compact Gate Tunnel Current Model for Nano Scale MOSFT with Sub 1nm Gate Oxide Ashwani Kumar 1, Narottam Chand 2,Vinod Kapoor 1 Department of lectronics and Communication nineerin Department of Computer

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

More information

Lightning Transients on Branched Distribution Lines Considering Frequency-Dependent Ground Parameters

Lightning Transients on Branched Distribution Lines Considering Frequency-Dependent Ground Parameters 214 International Conference on Lihtnin Protection (ICLP), Shanhai, China Lihtnin Transients on Branched Distribution Lines Considerin Frequency-Dependent Ground Parameters Alberto De Conti LRC Lihtnin

More information

A new small-signal RF MOSFET model

A new small-signal RF MOSFET model A new sall-sinal F MOSFET odel KWO-MING HANG, HAN-PANG WANG Departent of Electronics Enineerin, National hiao-tun Uniersity, Hsinchu, Taiwan 3,. O.. Tel: 8863573887. Fax: 8863573887. Astract: In this paper,

More information

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture No. # 08 MOS Inverters - III Hello, and welcome to today

More information

MOSFET Capacitance Model

MOSFET Capacitance Model MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

EE 435. Lecture 18. Two-Stage Op Amp with LHP Zero Loop Gain - Breaking the Loop

EE 435. Lecture 18. Two-Stage Op Amp with LHP Zero Loop Gain - Breaking the Loop EE 435 Lecture 8 Two-Stae Op Amp with LHP Zero Loop Gain - Breakin the Loop Review from last lecture Nyquist and Gain-Phase Plots Nyquist and Gain-Phase Plots convey identical information but ain-phase

More information

MOSFET Physics: The Long Channel Approximation

MOSFET Physics: The Long Channel Approximation MOSFET Physics: The ong Channel Approximation A basic n-channel MOSFET (Figure 1) consists of two heavily-doped n-type regions, the Source and Drain, that comprise the main terminals of the device. The

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

EE 435. Lecture 10: Current Mirror Op Amps

EE 435. Lecture 10: Current Mirror Op Amps EE 435 ecture 0: urrent Mirror Op mps Review from last lecture: Folded ascode mplifier DD DD B3 B3 B B3 B2 B2 B3 DD DD B B B4 I T QURTER IRUIT Op mp 2 Review from last lecture: Folded ascode Op mp DD M

More information

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS 98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC

More information

Effects of etching holes on complementary metal oxide semiconductor microelectromechanical systems capacitive structure

Effects of etching holes on complementary metal oxide semiconductor microelectromechanical systems capacitive structure Article Effects of etchin holes on complementary metal oxide semiconductor microelectromechanical systems capacitive structure Journal of Intellient Material Systems and Structures 24(3) 310 317 Ó The

More information

THE ACCURATE determination of the MOSFET threshold

THE ACCURATE determination of the MOSFET threshold 4180 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 1, DECEMBER 011 On the MOSFET Threshold Voltae Extraction by Transconductance and Transconductance-to-Current Ratio Chane Methods: Part II Effect

More information

ECEG 351 Electronics II Spring 2017

ECEG 351 Electronics II Spring 2017 G 351 lectronics Sprin 2017 Review Topics for xa #1 Please review the xa Policies section of the xas pae at the course web site. Please especially note the followin: 1. You will be allowed to use a non-wireless

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

Transistors - a primer

Transistors - a primer ransistors - a primer What is a transistor? Solid-state triode - three-terminal device, with voltage (or current) at third terminal used to control current between other two terminals. wo types: bipolar

More information

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,

More information

Mixed-Signal IC Design Notes set 1: Quick Summary of Device Models

Mixed-Signal IC Design Notes set 1: Quick Summary of Device Models ECE194J /594J notes, M. Rodwell, copyrihted 2011 Mixed-Sinal IC Desin Notes set 1: Quick Summary of Device Models Mark Rodwell University of California, Santa Barbara rodwell@ece.ucsb.edu 805-893-3244,

More information

Dielectric characteristics of glass fibre reinforced plastics and their components

Dielectric characteristics of glass fibre reinforced plastics and their components Plasticheskie Massy, No. 11, 2004, pp. 20 22 Dielectric characteristics of lass fibre reinforced plastics and their components V. I. Sokolov, S. I. Shalunov, I. G. Gurtovnik, L. G. Mikheeva, and I. D.

More information

6.012 Electronic Devices and Circuits Spring 2005

6.012 Electronic Devices and Circuits Spring 2005 6.012 Electronic Devices and Circuits Spring 2005 May 16, 2005 Final Exam (200 points) -OPEN BOOK- Problem NAME RECITATION TIME 1 2 3 4 5 Total General guidelines (please read carefully before starting):

More information

THE INVERTER. Inverter

THE INVERTER. Inverter THE INVERTER DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance» Speed (delay)» Power Consumption» Energy Noise in Digital Integrated Circuits v(t) V DD i(t) (a)

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

Microelectronics Part 1: Main CMOS circuits design rules

Microelectronics Part 1: Main CMOS circuits design rules GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!

More information

EECE488: Analog CMOS Integrated Circuit Design. Introduction and Background

EECE488: Analog CMOS Integrated Circuit Design. Introduction and Background EECE488: Analo CMOS Interated Circuit Desin Introduction and Backround Shahriar Mirabbasi Departent of Electrical and Coputer Enineerin University of British Colubia shahriar@ece.ubc.ca Technical contributions

More information

Round-off Error Free Fixed-Point Design of Polynomial FIR Predictors

Round-off Error Free Fixed-Point Design of Polynomial FIR Predictors Round-off Error Free Fixed-Point Desin of Polynomial FIR Predictors Jarno. A. Tanskanen and Vassil S. Dimitrov Institute of Intellient Power Electronics Department of Electrical and Communications Enineerin

More information

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B) 1 Introduction to Transistor-Level Logic Circuits 1 By Prawat Nagvajara At the transistor level of logic circuits, transistors operate as switches with the logic variables controlling the open or closed

More information

Active filter synthesis based on nodal admittance matrix expansion

Active filter synthesis based on nodal admittance matrix expansion Tan et al. EURASIP Journal on Wireless Communications and Networkin (1) 1:9 DOI 1.118/s18-1-881-8 RESEARCH Active filter synthesis based on nodal admittance matrix expansion Linlin Tan, Yunpen Wan and

More information

Self-heat Modeling of Multi-finger n-mosfets for RF-CMOS Applications

Self-heat Modeling of Multi-finger n-mosfets for RF-CMOS Applications Self-heat Modeling of Multi-finger n-mosfets for RF-CMOS Applications Hitoshi Aoki and Haruo Kobayashi Faculty of Science and Technology, Gunma University (RMO2D-3) Outline Research Background Purposes

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Lecture 5 Processing microarray data

Lecture 5 Processing microarray data Lecture 5 Processin microarray data (1)Transform the data into a scale suitable for analysis ()Remove the effects of systematic and obfuscatin sources of variation (3)Identify discrepant observations Preprocessin

More information

Polytech Montpellier MEA4 M2 EEA Systèmes Microélectroniques. Analog IC Design

Polytech Montpellier MEA4 M2 EEA Systèmes Microélectroniques. Analog IC Design Analo C Desin - Academic year 05/06 - Session 3 04/0/5 Polytech Montellier MEA4 M EEA Systèmes Microélectroniques Analo C Desin From transistor in to current sources Pascal Nouet 05/06 - nouet@lirmm.fr

More information

Analysis and Design of Analog Integrated Circuits Lecture 14. Noise Spectral Analysis for Circuit Elements

Analysis and Design of Analog Integrated Circuits Lecture 14. Noise Spectral Analysis for Circuit Elements Analysis and Design of Analog Integrated Circuits Lecture 14 Noise Spectral Analysis for Circuit Elements Michael H. Perrott March 18, 01 Copyright 01 by Michael H. Perrott All rights reserved. Recall

More information

CMOS Inverter (static view)

CMOS Inverter (static view) Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:

More information

Simple and accurate modeling of the 3D structural variations in FinFETs

Simple and accurate modeling of the 3D structural variations in FinFETs Simple and accurate modeling of the 3D structural variations in FinFETs Donghu Kim Electrical Engineering Program Graduate school of UNIST 2013 Simple and accurate modeling of the 3D structural variations

More information

Wire antenna model of the vertical grounding electrode

Wire antenna model of the vertical grounding electrode Boundary Elements and Other Mesh Reduction Methods XXXV 13 Wire antenna model of the vertical roundin electrode D. Poljak & S. Sesnic University of Split, FESB, Split, Croatia Abstract A straiht wire antenna

More information

Long Channel MOS Transistors

Long Channel MOS Transistors Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

A Multigrid-like Technique for Power Grid Analysis

A Multigrid-like Technique for Power Grid Analysis A Multirid-like Technique for Power Grid Analysis Joseph N. Kozhaya, Sani R. Nassif, and Farid N. Najm 1 Abstract Modern sub-micron VLSI desins include hue power rids that are required to distribute lare

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing

II III IV V VI B C N. Al Si P S. Zn Ga Ge As Se Cd In Sn Sb Te. Silicon (Si) the dominating material in IC manufacturing II III IV V VI B N Al Si P S Zn Ga Ge As Se d In Sn Sb Te Silicon (Si) the dominating material in I manufacturing ompound semiconductors III - V group: GaAs GaN GaSb GaP InAs InP InSb... The Energy Band

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 1 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

Nonlinear Model Reduction of Differential Algebraic Equation (DAE) Systems

Nonlinear Model Reduction of Differential Algebraic Equation (DAE) Systems Nonlinear Model Reduction of Differential Alebraic Equation DAE Systems Chuili Sun and Jueren Hahn Department of Chemical Enineerin eas A&M University Collee Station X 77843-3 hahn@tamu.edu repared for

More information

Altitude measurement for model rocketry

Altitude measurement for model rocketry Altitude measurement for model rocketry David A. Cauhey Sibley School of Mechanical Aerospace Enineerin, Cornell University, Ithaca, New York 14853 I. INTRODUCTION In his book, Rocket Boys, 1 Homer Hickam

More information

Gate capacitances of high electron mobility transistors

Gate capacitances of high electron mobility transistors Gate capacitances of high electron mobility transistors Author Alam, Khurshid Published 00 onference Title Proceedings of IEE00 opyright Statement 00 IEEE. Personal use of this material is permitted. However,

More information

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier

More information

Comparison of bulk driven, floating gate and sub threshold methods in designing of a typical amplifier

Comparison of bulk driven, floating gate and sub threshold methods in designing of a typical amplifier Journal of Novel Applied ciences Available online at www.jnasci.or 03 JNA Journal-03--9/49-436 IN 3-549 03 JNA Coparison of bulk driven, floatin ate and sub threshold ethods in desinin of a typical aplifier

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

Assessment of the MCNP-ACAB code system for burnup credit analyses. N. García-Herranz 1, O. Cabellos 1, J. Sanz 2

Assessment of the MCNP-ACAB code system for burnup credit analyses. N. García-Herranz 1, O. Cabellos 1, J. Sanz 2 Assessment of the MCNP-ACAB code system for burnup credit analyses N. García-Herranz, O. Cabellos, J. Sanz 2 Departamento de Ineniería Nuclear, Universidad Politécnica de Madrid 2 Departamento de Ineniería

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

Lab 4: Frequency Response of CG and CD Amplifiers.

Lab 4: Frequency Response of CG and CD Amplifiers. ESE 34 Electronics aboratory B Departent of Electrical and Coputer Enineerin Fall 2 ab 4: Frequency esponse of CG and CD Aplifiers.. OBJECTIVES Understand the role of input and output ipedance in deterinin

More information

The Intrinsic Silicon

The Intrinsic Silicon The Intrinsic ilicon Thermally generated electrons and holes Carrier concentration p i =n i ni=1.45x10 10 cm-3 @ room temp Generally: n i = 3.1X10 16 T 3/2 e -1.21/2KT cm -3 T= temperature in K o (egrees

More information

Excerpt from the Proceedings of the COMSOL Conference 2008 Hannover

Excerpt from the Proceedings of the COMSOL Conference 2008 Hannover Excerpt from the Proceedins of the COMSO Conference 8 Hannover Modelin and Characterization of Superconductin MEMS for Microwave Applications in Radioastronomy N. Al Cheikh *,1, P. Xavier 1, J.-M. Duchamp

More information

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Metal-Oxide-Semiconductor ield Effect Transistor (MOSET) Source Gate Drain p p n- substrate - SUB MOSET is a symmetrical device in the most general case (for example, in an integrating circuit) In a separate

More information

We are IntechOpen, the world s leading publisher of Open Access books Built by scientists, for scientists. International authors and editors

We are IntechOpen, the world s leading publisher of Open Access books Built by scientists, for scientists. International authors and editors We are IntechOpen, the world s leadin publisher of Open Access books Built by scientists, for scientists 3,800 116,000 120M Open access books available International authors and editors Downloads Our authors

More information

Slip-Flow and Heat Transfer in Isoflux Rectangular Microchannels with Thermal Creep Effects

Slip-Flow and Heat Transfer in Isoflux Rectangular Microchannels with Thermal Creep Effects Journal of Applied Fluid Mechanics, Vol. 3, No. 2, pp. 33-4, 200. Available online at www.jafmonline.net, ISSN 735-3645. Slip-Flow and Heat Transfer in Isoflux Rectanular Microchannels with Thermal Creep

More information

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance CMOS INVERTER Last Lecture Metrics for qualifying digital circuits»cost» Reliability» Speed (delay)»performance 1 Today s lecture The CMOS inverter at a glance An MOS transistor model for manual analysis

More information

SUPPLEMENTARY INFORMATION

SUPPLEMENTARY INFORMATION Hihly efficient ate-tunable photocurrent eneration in vertical heterostructures of layered materials Woo Jon Yu, Yuan Liu, Hailon Zhou, Anxian Yin, Zhen Li, Yu Huan, and Xianfen Duan. Schematic illustration

More information

MODEL MECHANISM OF CMOS DEVICE FOR RELIBILITY ENHANCEMENT

MODEL MECHANISM OF CMOS DEVICE FOR RELIBILITY ENHANCEMENT MODEL MECHANISM OF CMOS DEVICE FOR RELIBILITY ENHANCEMENT Sandeep Lalawat and Prof.Y.S.Thakur lalawat_er2007@yahoo.co.in,ystgecu@yahoo.co.in Abstract This paper present specific device level life time

More information

Normed Distances and Their Applications in Optimal Circuit Design

Normed Distances and Their Applications in Optimal Circuit Design Optimization and Enineerin, 4, 197 213, 2003 c 2003 Kluwer Academic Publishers. Manufactured in he Netherlands Normed Distances and heir Applications in Optimal Circuit Desin ABDEL-KARIM S.O. HASSAN Department

More information

Philips Research apple PHILIPS

Philips Research apple PHILIPS c Electronics N.V. 1997 Modelling Compact of Submicron CMOS D.B.M. Klaassen Research Laboratories The Netherlands Eindhoven, contents accuracy and benchmark criteria new applications í RF modelling advanced

More information

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers

6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers 6.776 High Speed Communication Circuits Lecture 10 Noise Modeling in Amplifiers Michael Perrott Massachusetts Institute of Technology March 8, 2005 Copyright 2005 by Michael H. Perrott Notation for Mean,

More information