Integrated Circuit Fundamentals

Transcription

1 Chapter UEE3/UEEG43 Integrated Circuit Design Integrated Circuit undamentals

2 Prepared by Dr. Lim oo King 0 Jan 011.

3 Chapter Integrated Circuit undamentals Introduction Effects of Bias Voltage Threshold Voltage MOET Current-Voltage Characteristics Linear Region aturation Region Drain Conductance and Transconductance Cut-off requency Non-Ideal Effects ub-threshold Conduction Channel Length Modulation Mobility Variation Velocity aturation Ballistic Transport hort-channel Effects Narrow-Channel Effects Drain-Induced Barrier Lowering Gate-Induced Drain Leakage Threshold djustment by Ion Implantation Exercises Bibliography i -

4 igure.1: The energy band diagrams of three biased voltage conditions of an ideal p- type MO capacitor... Error! Bookmark not defined. igure.: The energy band diagram of p-type MO device at inversion condition... 1 igure.3: Charge density, electric field, and electrostatic potential of MO in inversion mode... igure.4: -D structure of an n-moet... 6 igure.5: Channel geometry showing the flow of current I D analysis... 9 igure.6: Characteristic curve of MOET... 3 igure.7: The ideal and experimental drain current of a MOET igure.8: igure.9: Energy band diagrams of n-moet showing accumulation and weak inversion modes Experimental results of electron mobility versus effective transverse electric field at inversion igure.10: Comparison of drain-to-source current I D for constant mobility condition and electric field and saturation velocity dependence igure.11: Charge sharing in short-channel threshold voltage model igure.1: Threshold voltage V t versus channel length L for n-channel MOET... 4 igure.13: Lightly doped drain design and corresponding doping profile LDD and non- LDD drain igure.14: Cross-section of an n-channel MOET showing depletion width along the width W igure.15: Potential energy of electron along channel surface and DIBL igure.16: Energy band diagram showing GIDL igure.17: Ion-implanted profile apprimated by a step function ii -

5 Chapter Integrated Circuit undamentals.0 Introduction In this chapter, we will discuss the theory of basic MO which includes the effects of MO with bias voltage and the theory of MO transistor. The currentvoltage characteristics and the threshold voltage are the main topics of discussion. The non-ideal effects of the MO transistor due to scaled down issues are particularly discussed..1 Effects of Bias Voltage There are three important regimes when the MO capacitor is under gate voltage bias V G. These are accumulation, depletion, and inversion modes (refer to ig..1(b), ig..1(d), and ig..1(e)). The energy band diagram of a p- MO without gate voltage bias is shown in ig..1(a). Owing to the difference in work function, and interface charge trapping, the valence band is bending toward the ermi level at the interface, whist the conduction band is bending away from the ermi level. lat-band Condition: If the negative bias voltage i.e. V G < 0 is applied to the metal with respect to the p-type semiconductor, the ermi level of the metal is raised by an amount qv G. This would cause the reduction the bend of conduction and valence bands. urther increase of gate voltage will eventually cause the conduction and valence bands aligned with the ermi level. This is the flat-band condition illustrated in ig..1(b). ccumulation Mode: If the negative bias voltage i.e. V G < 0 is applied between the metal and semiconductor, the ermi energy level of the metal is raised by an amount qv G and the valence band of the semiconductor bends toward the ermi level. This would cause the hole to accumulate at the surface near the ide. The illustration is shown in ig..1(c). Depletion Mode: If the positive bias voltage i.e. V G > 0 is applied to the metal with respect to the p-type semiconductor, the ermi level of the metal is lowered by an amount qv G. This would cause the valence band of the semiconductor to move away from the ermi level of the metal. s a result, the

6 Integrated Circuit undamentals hole depletes into the bulk as such that the hole concentration near the interface falls below the concentration value in the bulk semiconductor. The illustration I shown in ig..1(d). Inversion Mode: If the positive bias voltage i.e. V G >> 0 is further increased, eventually the conduction band of the semiconductor comes closer to the ermi level. s a result, electron density near the interface surface starts to increase. urther increase of bias voltage would cause the conduction band of the semiconductor to bend further and crosses the ermi level of the metal. In this condition, the density of electron increases very high and the semiconductor at the interface is inverted into n-type semiconductor. The illustration is shown in ig..1(e). (a) No voltage bias at gate (b) lat-band condition

7 Integrated Circuit undamentals (c) Negative voltage bias at gate accumulation mode (d) Positive voltage bias at gate depletion mode

8 Integrated Circuit undamentals (e) High positive voltage bias at gate - inversion mode igure.1: The energy band diagrams of three biased voltage conditions of an ideal p-type MO capacitor When the surface potential qф, which is potential difference of the intrinsic energy level at the interface with the intrinsic energy level in the bulk, is zero, it implies flat-band condition. or p-type MO, when qф is a positive, it implies depletion mode. When qф is a positive value and larger than qφ then inversion occurs. When qф is a negative value, it implies accumulation. imilar explanation is applied to n-type MO device. The energy band diagram of the p-type MO device under inversion condition is shown in ig... Notice that inversion occurred when the surface potential is twice the ermi potential, which follows equation (.1). qφ (inv) qφ (.1) The ermi potential at the bulk qφ is φ kt N ln q ni (.) where N is the acceptor doping concentration for p-type semiconductor, n i is the intrinsic carrier concentration and kt/q is the thermal voltage. ubstituting equation (.) into equation (.1) yields equation (.3)

9 kt N Integrated Circuit undamentals Φ (inv) ln φ (.3) q ni igure.: The energy band diagram of p-type MO device at inversion condition Besd on ig.., the electron charge concentration n(z) is defined from equation equation qφ(z) n ( z) ND exp kt qφ(z) p ( z) N exp. kt. Threshold Voltage, while the hole concentration p(z) is defined from Threshold voltage V t is defined as the gate voltage V G needed to induce sufficient number of charge carrier in the channel for conduction. It is the minimum applied gate voltage to induce inversion of the channel for conduction. To find the threshold voltage V t, one needs to understand how the voltage is dropped across the MO capacitor. ig..3 shows the MO structure with a voltage V G applied to its gate. pplying Kirchhoff s voltage law, the gate voltage V G is - 1 -

10 Integrated Circuit undamentals V G V + V s (.4) igure.3: Charge density, electric field, and electrostatic potential of MO in inversion mode Equation (.4) is an ideal equation without considering the trapped charge within the ide that alters the electric field and the differences in the electrical characteristics of the gate and substrate materials. Thus, a term flat-band voltage is used to account these effects, which is 1 V fb ( φ ) ( Q + Q ) φ f (.5) G C where ( φ ) is the work function difference between gate and substrate and G φ is also apprimately equal to ( ) kt N N D,poly φ G φ ln q ni for an n-type polysilicon gate with p-substrate. If the poly gate is a p-type, then the work function difference between gate and substrate is ( ) work function is derived from φ Φ kt N ln q n i D φ Φ + kt N ln q n i kt N φ G φ,poly ln q N. The for p-type material and for n-type material. Φ is a work function constant. - -

11 Integrated Circuit undamentals Q f is the fixed surface charge density at the ide-silicon interface and Q is the trapped charge within the ide. Re-writing equation (.5), it becomes V fb kt N N D,poly Q Q ln + f q n i C (.6) Equation (.4) shall then be modified to V G V fb + V + V (.7) The voltage drops across ide V is V E.d. t semiconductor-ide interface, the surface charge Q is also equal to charge on ide Q, which is ε s E s ε E. Q is also equal to Q C V V ε E ε d. Re-writing equation (.7), it becomes V ε d. Thus, V is equal to V G V fb + V + ε E C (.8) or charge balancing, Q Q Q dep, where depletion charge Q dep is equal to Q dep qn d dep. The depletion thickness d dep is equal to d dep εv qn 1/. t inversion, V G V tn and V φ, d dep becomes maximum value. Thus, the maximum depletion charge Q depmax is equal to ( 4ε φ ) 1/ and surface electric field E is E Q dep max ε 4qε ε N φ qn. ubstituting expression ( 4ε φ ) 1/ to replace ε E in equation (.8), the threshold voltage equation becomes qn V tn V fb + φ + 4ε qn φ / C (.9) or V V fb + φ + Q / C (.10) tn If the substrate of the MO transistor is biased with a voltage V UB then the threshold voltage V tn is redefined as - 3 -

12 Integrated Circuit undamentals V V fb + φ + ε qn (φ + V ) / C (.11) tn UB The equation shows that the threshold voltage increases with positive V UB bias since the surface potential is increased by a value V UB. Under normal processing conditions, the flat-band voltage is negative and usually yields a negative threshold voltage. or CMO switching circuits that use a positive power rail, a positive threshold voltage is needed. This is accomplished by performing a threshold adjustment ion implant with a dose giving the number of implanted ion. This modifies the equation for the value of the threshold voltage. Implanting acceptor ions into the substrate is equivalent to introducing additional bulk charge at the surface; the implant thus induces a positive shift. The equation to follow for the ion implant adjustment is qd V tn UB ± C I V fb + φ + ε qn ( φ + V ) / C (.1) where D I is the dosage, the number implanted ion per unit area. If there is no substrate voltage V UB, in which sometime is called zero body bias then equation (.11) becomes Vtno V fb + φ + εqn (φ ) / C, where V tno is the threshold voltage without the substrate voltage or body bias voltage. The equation (.11) can be re-written in terms of V tno and substrate voltage as The term V ε C ε qn ( (φ + V ) φ ) tn Vtno + UB COX OX (.13) qn is denoted as gamma γ, which is called bulk threshold parameter. Equation (.13) clearly shows that as the V UB voltage increases the threshold voltage of the device increases. Rewriting equation (.13), it becomes V ( (φ + V ) φ ) t Vto ± γ UB (.14) The positive sign is used to denote n-mo transistor and negative sign for p- MO transistor. In order to eliminate the effect of parasitic npn or pnp transistor of the n- MO transistor and p-mo transistor, the substrate of the p-mo transistor, - 4 -

13 Integrated Circuit undamentals which is an n-type semiconductor, is usually biased with V DD voltage, whilst the substrate of n-mo transistor, which is p-type semiconductor, is biased with V voltage i.e. zero volt. By Kirchhoff s voltage law, the source voltage V and substrate voltage V UB relationship is V +V -UB +V UB 0. Equation (.14) therefore can be written as one equation for p-mo transistor and one for n-mo transistor. They are V V ( (φ + V V ) φ ) tp Vtpo γ UB (.15) ( (φ + V V ) φ ) tn Vtno + γ UB (.16) With substrate of p-mo transistor biased with V DD, and source and substrate are tied together, the V UB- is equal to zero. Therefore, the threshold voltage of p-mo transistor is V ( (φ + V ) φ ) tp Vtpo γ DD (.17) With the substrate of n-mo transistor biased with V and source and substrate are tied together, V -UB is equal to zero. Therefore, the threshold voltage of the n-mo transistor is ( (φ ) φ ) Vtno V tn Vtno + γ (.18) One can see that V tp of p-mo transistor is lower than V tpo, whilst the V tn of n- MOET is same as V tno for the substrate biased condition mentioned above..3 MOET MOET is a MO transistor and is essentially consist of a MO capacitor and two diffused or implanted regions that serve as ohmic contacts to an inversion layer of free charge carriers with the semiconductor-silicon diide interface. igure.4 illustrates the -D structure of an n-moet

14 Integrated Circuit undamentals igure.4: -D structure of an n-moet Gradual Channel pprimation Model and Constant Mobility pprimation Model can be used to study the characteristics of MOET. The model is used to study how the conduction channel of the MOET is changed by the horizontal electric field generated by the drain to source voltage V D and how the conducting channel is modulated by the vertical electric field generated by the gate to source voltage V G. This is done by studying the drain to source current I D versus drain to source voltage V D characteristic for different applied gate to source voltage V G and the transconductance of the device, which is the study of I D current changes with the change of V G voltage. These two studies are connected with the physical studies of the linear and saturation regions of the drain to source characteristics with various gate-to-source voltage V G. Based on this understanding, one has to look at the two dimensional Poisson s equation in order to understand the actual conduction mechanism of current from drain to source via the inverted channel. There are two electric field components present in MOET when it is in operation. These fields can be represented by the two dimensional Poisson s equation that has one horizontal field E X and one vertical field E Y. E X X E Y Y ρ ε + (.19) Gradual Channel pprimation Model is true only if X is very small and X constant so that the Poisson s equation can be apprimated as E - 6 -

15 Integrated Circuit undamentals E Y Y ρ ε (.0) The vertical electric potential of the conduction channel with thickness δd is given as EY Y EY. δd E Y Y ε ε s ( V V ) d G t kt / q (.1) On the other hand, the variation of horizontal electric field can be apprimated as E X X V D (.) L where L is the channel length and V D is the voltage between drain and source of the MO transistor. Here, it is assumed that the field strength changes gradually from a small value near the source to a value of the order V D /L near the drain. The mobilities of the electron and hole µ n, µ p of the MO transistor are not the same as the mobility in the semiconductor bulk moving into the crystal lattice. Knowing the electrons or holes are moving on the surface between the semiconductor and ide interface, their mobilities are very much depending on the surface impeding collision and ionized impurity scattering. However electrons and holes moving not closed to the interface would have a higher mobility. One also has to consider the influence of horizontal electric field resulted from drain to source voltage. Thus, there is an effective mobility µ for both hole and electron. If the drain-to-source voltage is small, the effective channel length and carrier charge will be more or less uniform from the source to drain and effective mobility will be essentially the same for all x values. However, one cannot ignore the effect of gate voltage on the mobility. s the gate-to-source voltage increases, the electron is moving closed to the interface. The effect of scattering will be more. Thus mobility decreases which can be observed from equation (.3)

16 Integrated Circuit undamentals n µ 0 1+ θ(vg V t ) µ (.3) where µ 0 is constant and θ is the mobility degradation parameter. It can be shown that the effective mobility µ n of electron is about 0.6 of the bulk mobility at (V G V t ) 4V to about 0.5 for (V G V t ) 13V..3.1 Current-Voltage Characteristics The surface potential above threshold regime is equal to V s (x) ( φ + V( x)), where V(x) is the channel potential at position x along the channel in the direction from source to drain. However, from Gradual Channel pprimation Model, one can say that V(x) is equal to zero at the source side because the source and the substrate are normally shorted together and biased at V for an n-mo transistor and biased at V DD for p-mo transistor. Thus, V(x) is equal to the drain-to-source voltage V D at the drain side. This shall mean that the gate voltage with respect to source V G is equal to V Qs (x) V fb + + φ V(x) (.4) C G + Q s (x) is the surface charge, which is consisting of free electron charge Q n (x) and fixed charge acceptors in the depletion region Q DEP (x). Therefore, the surface charge of is given by equation (.5). Q s (x) Q n (x) + Q DEP (x) (.5) rom Constant Mobility pprimation Model, the electron mobility µ n is constant and there is only drift and negligible diffusion, the drain-to-source current I D can be calculated from current density J n qµ n ne after ignoring the dn diffusion portion qd n. Indeed drift current is only required to be considered dx since the drain is reversed biased with respect to source. Using the channel geometry of the current flow shown in ig..5, drain-to source-current I D is made of summation of all small rectangular current elements with surface area Wdy across the channel of thickness dx for the whole channel length L

17 Integrated Circuit undamentals igure.5: Channel geometry showing the flow of current I D analysis Thus drain to source current can be calculated equation (.6). I D J ny dydw W y(x) 0 J ny dy y(x) dv(x) W q µ n (x, y)n s (x, y) dy dx 0 (.6) where the second expression of equation (.6) is equal to effective mobility of the electron µ n, which is equation (.3). Knowing that the threshold voltage is V t φ +V fb + Q C DEP and V φ + V + V(x) + V (x) + V G fb after inversion with mobile ion density n s, the surface free charge density per unit area n s (x) in x- direction is n (x) C q [ V φ V V(x) ] ε OX N ns [ V(x) + φ ] G fb (.7) ubstituting equation (.7) into I D dx qµ n n s WdV(x) and integrating the equation with the boundary conditions for V( x) x0 0 and V( x) x L V D and x 0 to x L, I D, it yields the drain to source equation (.). q I D Wµ V V n G fb L C ε qn 3C φ V D V D [( V + φ ) ( φ ) ] 3 / 3 / D (.8) - 9 -

18 Integrated Circuit undamentals t pinch-off condition where n 0 and V( x) x L V D V DT, equation (.8) is equal zero for V(x) V D. olving the quadratic equation for V D shall yield, V D εqn V φ + DT VG V fb C 1 (VG V fb )C 1+ ε qn (.9) Beyond pinch-off, the drain current I D essentially remain constant but it may be complicated by channel modulation and other effects..3. Linear Region or very small drain to source voltage where V D << (V G -V fb -φ ) and V D << φ, equation (.8) can be simplified to equation (.30) and expanding the Taylor s series for the second term. Wµ nc VD I (V V )V D G t D (.30) L This is the equation for the linear region of the MOET s characteristics..3.3 aturation Region fter pinch-off, I D is assumed to be constant. It is true only if the doping concentration is low and the ide thickness is thin. The term in equation (.9) involving N / C can be ignored and terms involving N / C can be retained. This gives the shall mean that V DT V V φ ( V V ) 1/ G fb ε C qn (.31) If the voltage drops across the ide is negligible, then at strong inversion the quantity (V G V fb ) is equal to V G V fb φ. Based on the above assumption, equation (.31) can be simplified as G fb V DT V V (.3) G t fter substituting equation (.31) into equation (.9),

19 Integrated Circuit undamentals I DT Wµ nc L {( V V φ ) G fb ε qn 3C (V G (V V ) t G [( V V + φ ) ( φ ) ] 3 / 3 / G t V t ) (.33) ince the current does not change with V D in this equation, further simplification can be done once pinch-off occurred. i.e. N / C is small such that V t V fb + φ. The equation (.33) shall be simplified to I Wµ C (V V ) n G t DT ( VG Vt ) (.34) L Wµ n (VG V t ) L C This is the equation for the saturation region of the MOET characteristics. typical ideal characteristic curve of an n-mo transistor is shown in ig..6. The curve shows three regions of the characteristic, which are the linear, saturation, and cut-off regions. The MO transistor device will be turned off if the V G voltage is less than the threshold voltage V t. Note also that the dotted line is a line denotes that V D V G V t. This is a dividing line that determines the operational condition of the MO transistor. It is also the line showing the pinch-off the current. If the condition is V D < V G V t then the MO transistor is in linear region or at time it is referred as triode region. This is the region that the MO transistor device would work as a digital logic device. If the condition is such V D > V G V t then the MO transistor is in saturation region. This is the region that the MO transistor device works as an amplifier device

20 Integrated Circuit undamentals igure.6: Characteristic curve of MOET.3.4 Drain Conductance and Transconductance Having defined the equations for linear and saturation regions of the MO transistor, the next two important parameters of MO transistor to be defined are the drain conductance and the transconductance. The drain conductance g D is defined as g D I V D D V Cons tan t G Wµ nc (VG V t ) (.35) L Drain conductance is also equal to equation (.30) if the term V D is moved to the left-hand side of the equation as denominator. The transconductance g m at saturation region is defined as g m I V DT G VD cons tan t Wµ nc L (V G V ) t (.36) - 3 -

21 Integrated Circuit undamentals.3.5 Cut-off requency The cut-off frequency f max of the MO transistor is defined as the maximum operating frequency of the MO transistor when it is in saturation mode with the assumption that the mobility of the carrier is constant. Thus, the cut-off frequency for p-mo transistor is defined as f max g m πc G (.37) where C G is the gate to source capacitance, which estimated to be ide capacitance per unit area multiplies by area WL. Thus, the gate-to-source capacitance is C C WL G. g πc m p G f max t (.38) G µ (V πl V ) or the short channel device, the cut-off frequency is assumed to depend on the transit time t tr of the carrier in the channel. Thus, f max πt v πl 1 sat tr (.39) where by t tr is also apprimately equal to the channel length L divided by carrier saturation velocity v sat. i.e. t rr L/v sat..4 Non-Ideal Effects Owing to scaling down of integration, many physical parameters of the material are no longer can be considered ideal parameters. Phenomenon such as hot electron, reaching saturation velocity, prominent interface scattering etc are dominating at small device structure. The non-ideal effects for MO transistor to be considered in this lecture are sub-threshold, channel length modulation, mobility variation, velocity saturation, ballistic effect, short-channel effect, narrow channel effect etc..4.1 ub-threshold Conduction The ideal current-voltage characteristic of MO transistor shows that there is no conduction current when the gate to source voltage V G is less than or equal to

22 Integrated Circuit undamentals the threshold voltage V t i.e. V G V t. However, in reality there is a subthreshold current flows caused by the surface of semiconductor develops into a lightly doped n-type material joining the n-type drain and source for the case of n- MO transistor. Owing to the way that drain is biased, there is also a small amount of drift current is being registered before the channel is switched on. The ideal and experimental current characteristics of MO transistor are shown in ig..7. igure.7: The ideal and experimental drain current of a MOET Upon the gate to source bias and when the surface potential Φ is less than φ, the ermi level is closer to conduction band. Thus, it causes the p-type material near the ide interface turns into lightly doped n-type. This would expect some conduction between n + -source and drain through this inverted n-type substrate. The condition for φ <Φ < φ is known as weak inversion. The energy band diagrams of an n-mo transistor during accumulation and weak inversion are shown in ig..8. The sub-threshold current I D-ub is equal to I W kt q( VG Vt ) qvd D ub µ nc exp 1 exp (.40) L q ηkt where µ n is the electron mobility, C is the gate capacitance per unit area, W is the channel width, L is the channel length, V t is the threshold voltage of the kt

23 Integrated Circuit undamentals MO, and η is the sub-threshold parameter related to the sub-threshold swing which is the gate voltage change needed to raise the sub-threshold current by one decade following the relation ηv t (ln 10). The sub-threshold parameter η is given by η 1+ C C D (.41) where C D is the depletion channel capacitance per unit area. igure.8: Energy band diagrams of n-moet showing accumulation and weak inversion modes.4. Channel Length Modulation s the drain-to-source voltage V D exceeds V DT, the drain to source current I D is independent of the V D. In reality there is a shortening of the channel L, which is supported by the excess voltage drain-to-source voltage V D (V D V DT ). W The depletion width at drain W D is governed by equation ε [φ + V ] D D. The incremental change in depletion length, which is also qn equal to L, is equal to

24 Integrated Circuit undamentals ε [ φ + V + V φ V ] (.4) L DT D + qn ' The drain current I D with channel modulation taken in account shall be what is shown in equation (.38). DT I ' D L L L I DT (.43) The result shows that there is an increase of output conductance of the device as the drain-to-source V D exceeded the saturated drain-to-source voltage V DT..4.3 Mobility Variation In reality there are two factors influencing the mobility of carrier in MO transistor. The increase of gate voltage forces the carrier to move closer to the interface whereby the roughness and ide impurities cause higher degree of scattering on the carrier due to coulumbic interaction. The effective mobility of the carrier decreases as its drift velocity V drift approaches saturation limit. igure.7 shows the results of deviation of ideal drain current characteristic due these effects. or a small electric field, the mobility is constant with respect to drift velocity. t high electric field, the mobility is no longer constant and will be degraded until it reaches zero when the drift velocity of the carrier reaches its saturation velocity. The relationship between the inversion charge mobility and transverse electric field is usually measured experimentally. The effective transverse electric field E eff for electron is defined as 1 1 E eff Q DEP + Q n ε (.44) However, for hole with mobile charge Q p, equation (.44) has to be modified slightly to 1 1 E eff Q DEP + Q p ε 3 (.45)

25 Integrated Circuit undamentals The effective inversion mobility can be determined from the channel conductance as a function of gate voltage. The effective inversion mobility µ eff is defined as 1/ 3 1/ 3 E eff 1 1 µ eff µ 0 0 QDEP + Qn E µ (.46) 0 εe0 m where µ 0 and E 0 are experimentally determined constants, and m is either or 3. Based on equation (.41), the experimentally results of electron mobility versus effective transverse electric field at inversion is shown in ig..9. The linear drain-to-source current equation, which is equation (.30) Wµ nc VD I (V V )V D G t D, should then be modified to equation (.47) L by adding in the scattering effect of mobility and transverse electric effect, which are equation (.3) and (.46) respectively. 1/ 3 Wµ oc E eff VD I D (V V )V (.47) L 1 [ ] G t D + θ(vg V t ) E o igure.9: Experimental results of electron mobility versus effective transverse electric field at inversion

26 Integrated Circuit undamentals imilarly, the saturation current equation shown in equation (.34) can be modified to include the scattering effect of mobility and transverse electric effect..4.4 Velocity aturation In the ideal current-voltage analysis, the mobility of the electron is assumed to be constant which shall mean that the drift velocity increases without limit as the electric field increases. However, the velocity saturates with increase electric field. or short channel device, velocity saturation becomes more prominent since the horizontal electric field is generally large. The current saturation for ideal current-voltage relationship occurred when inversion charge density n s at drain is equal zero. i.e. when V D V G V t. or n-mo transistor, the velocity saturation can cause the current saturation condition if the electric field is apprimately 1.0x10 4 Vcm -1. or drain-tosource voltage V D of 5V and channel length L equals to 1.0µm, the average electric field shall be 1.0x10 5 Vcm -1. This shall mean that saturation velocity is likely to occur for short channel device. The modified saturation current I DT shall be I DT WC (V G V t )v sat (.48) where the saturation velocity v sat is apprimately 1.0x10 7 cms -1 for electron in bulk and C is the ide capacitance per cm and W is the gate width. aturation velocity will decrease as gate voltage increases due to increase scattering effect. The saturation current I DT is smaller for velocity saturation condition and it is having linear relation as shown in equation (.48) rather square law dependence as shown in equation (.34). igure.10 shows the comparison of drain-to-source current I D for constant mobility and electric field conditions and saturation velocity dependence. There are several models of mobility versus electric field. One of commonly use equation is µ µ eff µ + eff E 1 vsat 1 / (.49)

27 Integrated Circuit undamentals rom equation (.48), the transconductance curve g m is found to be g m I DT WC V G v sat. This shall mean that transconductance is independent of gate-to-source V G and drain-to-source V D voltages. rom equation (.38), the cutoff frequency f max for constant mobility condition shall be given by equation (.50), which is equation (.39). g m WC vsat vsat f max πc πc WL πl G (.50) igure.10: Comparison of drain-to-source current I D for constant mobility and electric field conditions and saturation velocity dependence.4.5 Ballistic Transport The average drift velocity v drift is a function of mean time between collisions or mean distance l between scattering events. or long channel device, the channel L is greater than l. s the channel length L decreases, the average distance between collision l is comparable to channel length L. If channel length L is reduced to such that L < l, then large fraction of carrier could travel from source to drain without experience scattering event. This motion of carrier is called ballistic event. Ballistic transport means carriers travel faster than average drift

28 Integrated Circuit undamentals velocity or saturation velocity. This would lead to very fast device. Ballistic transport will occur for sub-micron device that has less than 1.0µm channel length. s the channel length of MO transistor technology continues to shrink toward 0.1µm or less value, the ballistic transport phenomenon will become more important..4.6 hort-channel Effects s the channel length of the device decreases, the fraction of charge in the channel controlled by the gate decreases. The reverse bias depletion region at the drain side extends further into the channel area and the gate will control even less bulk charge. s the channel becomes very short, the electric field across the channel is high. The carrier becomes "hot" because the kinetic energy of the carrier is very high. This can cause tunneling of the carrier into ide layer that produces gate current because the breakdown of covalent bonds. Radiation effect is more severe for short channel device than the long channel device. small change in the ide charge or interface-state can cause serious effect especially from γ-ray radiation, which generates a burst of charges. This definitely will cause "soft error" for memory device. V The threshold voltage V t of the device follows equation (.10), which is t V fb + φ + 4εeN φ / C Q C when charge ide Q is assumed present. The short-channel effect on the threshold voltage can be determined from the short-channel threshold model shown in ig..11. r j is the diffused junction depth. The assumption for lateral diffused distance under the gate is same as vertical diffused distance. This assumption is not quite true for ion-implanted drain and source. The analysis is based on trapezoidal region under the gate controlled by the gate

29 Integrated Circuit undamentals igure.11: Charge sharing in short-channel threshold voltage model s it is shown in ig..3, the potential difference across the bulk depletion region is φ at threshold inversion point. The built-in potential barrier height of source and drain is apprimately φ. This implies that the depletion width of the three regions are essential equal which is x s x d x DEP x DEP. Using the geometrical apprimation, the average bulk charge per unit area Q b ' in the trapezoid is L + L' L shall be L + L Qb qn x DEP (.51) L j can be shown, as equals to 1 1+ DEP 1 Q r L r xdep 1 1+ j xdep 1 L rj b qn x r j then equation (.51) '. Q b shall be equal to 4 qn φ ε. ince Q DEP is equal to qn x DEP, for non short-channel effect, therefore, the change of threshold voltage V t caused by short-channel effect is V t Q, b Q C DEP qn x C DEP r j L DEP 1 x + 1 rj (.5) Essentially it shows that the threshold voltage is lower by a value shown in equation (.5) for short-channel device. hort-channel effect for n-mo transistor becomes more significant when the channel length L is less than.0µm as illustrated in ig

30 Integrated Circuit undamentals s mentioned earlier, when channel becomes very short, the electric field across the channel may be high because the applied voltage may not be scaled down according. s the result, the carrier becomes "hot" because the kinetic energy of the carrier is very high. This can cause tunneling of carrier into ide and near punchthrough condition especially with the presence of parasitic bipolar device. igure.1: Threshold voltage V t versus channel length L for n-mo transistor To overcome this problem is to alter the doping profile of the drain contact by Lightly Doped Drain LDD design approach. By introducing a lightly doped region, it reduces the peak electric field in the depletion region at drain and hence reduces the breakdown effect. The magnitude of the electric field at ide-semiconductor interface in the LDD structure is less than in the conventional structure. igure.13 shows the design and the corresponding doping profile LDD and non-ldd drain. (a) Lightly doped design - 4 -

31 Integrated Circuit undamentals (b) LDD doping profile igure.13: Lightly doped drain design and corresponding doping profile LDD and non- LDD drain.4.7 Narrow-Channel Effects igure.14 shows the cross section of an n-mo transistor showing the depletion region along the width W of the device. igure.14: Cross-section of an n-mo transistor showing depletion width along the width There is an additional depletion region at each ends of channel width. The charges in the region are controlled by gate voltage, which is not included in earlier derivation of the ideal threshold voltage. If neglecting short-channel effects, the gate-controlled bulk channel can be written as Q B Q B0 + Q B (.53) where Q B is the total bulk charge, Q B0 is the ideal bulk charge and Q B is the additional bulk charge. or uniformly doped p-type semiconductor, the total bulk charge Q B is Q B qn WLx + qn ( ) (.54) DEP LxDEP ξx DEP

32 Integrated Circuit undamentals or Q B qn WL ξx 1+ Z DEP x DEP (.55) where ξ π for semi-circle end, a fitting parameter for lateral depletion width. Thus, the change in threshold voltage V t is V t qn x C DEP ξx W DEP (.56).4.8 Drain-Induced Barrier Lowering If a short-channel length MO transistor is not scaled properly, such as reducing channel length with reducing the applied drain-to-source voltage, the source/drain junctions are too deep or the channel doping concentration is too low, there can have electrostatic interaction between drain and source, which is known as Drain-Induced Barrier Lowering DIBL. This leads to punchtrough leakage or breakdown between source and drain. igure.15 shows the potential energy of electron along the channel surface and DIBL. Once the source-channel barrier is lower by DIBL, there can be significant leakage current with gate being unable to shut off. To overcome DIBL, the source and drain junctions must be made sufficiently shallow which is scaled properly as the channel length reduced. econdly the channel doping concentration must be sufficiently high to prevent the drain from being able to control the source junction. or short-channel MO transistor, the DIBL is related to channel length modulation of pinch-off region L. Therefore, the characteristic of saturation drain-to-source current follows equation (.43)

33 Integrated Circuit undamentals igure.15: Potential energy of electron along channel surface and DIBL.4.9 Gate-Induced Drain Leakage s you can see in ig..7, there is sub-threshold current when the gate voltage is below the threshold voltage V t. s the gate voltage goes more negative, the sub-threshold current is indeed increasing. This on-state leakage is known as gate-induced drain leakage GIDL. The gate voltage is getting more negative is equivalent to the gate voltage is set at zero volt and voltage at drain is getting more positive. The drain doping concentration is high and a narrow depletion is normally formed. If the band bending is more than the band-gap E G across the narrow depletion region, then a condition of band-to-band tunneling of electron from valence band to conduction is exist. The electron flows to drain as gateinduced drain leakage GIDL current. ig..16 shows the energy band diagram of n + poly io n + -drain. igure.16: Energy band diagram showing GIDL

34 Integrated Circuit undamentals.5 Threshold djustment by Ion Implantation s you know the threshold voltage of an MO transistor is dependent on fixed ide, metal-semiconductor work function difference, ide thickness, and semiconductor doping concentration. The results of fabrication based on dependent variables may not be acceptable. The threshold voltage of the device needs to be adjusted which can be done by ion implantation. Ion implantation would adjust the doping concentration of substrate near the ide. Ion implantation can precisely control the amount of dopant to be added. dding acceptor ion into either p- or n-substrate would shift the threshold voltage more positive because the depletion region is thicker. Likewise, adding donor ion would shift threshold voltage more negative because the depletion region is thinner. s the first apprimation, if D I acceptor per cm of ion is to be implanted into p-type substrate, the shift of threshold voltage V t is qd I V t (.57) C If the ion implantation is a step junction, the threshold voltage after a step implant for case where x DEP > x i is V t q(n N )x i Vto + (.58) C whereby D I (N - N )x i. N is the implant doping concentration; x I is the induced depletion thickness by implanted ion on pre-implant depletion thickness x DEP. V to is the pre-implant threshold voltage, which follows equation Vtno V fb + φ + εqn (φ ) / C. igure.17 illustrates the ion-implanted profile apprimated by a step function

35 Integrated Circuit undamentals Exercises igure.17: Ion-implanted profile apprimated by a step function.1. ind the work function difference for an n-type polysilicon gate n-mo transistor that has poly gate doping concentration and substrate doping concentration of 1.5x10 19 cm -3 and 1.0x10 15 cm -3 respectively... The work function difference between l-io -p-type silicon MO transistor is -0.15V given concentration of p-type is 1.0x10 1 cm -3 and the work function of l is 4.8V. Calculate the value of the work function constant Φ for the device..3. If the thickness of the ide for the l-io -p-type silicon MO is 600 0, the flat-band potential is -0.87V, and the concentration of p-type semiconductor is 5.0x10 16 cm -3, calculate the threshold voltage V t of the MO..4. MO capacitor has an aluminum gate and p-type substrate with doping concentration 5.0x10 16 cm -3. Its ide thickness is 450 o and cross sectional area is 1x10 - cm. Calculate the ide capacitance..5. Consider an n-mo transistor with gate width W 10µm and gate length L 1.5µm and ide capacitance C 10-7 /cm. In the linear region for a fixed V D 0.1V, the drain current is found to be 40µ for V G 1.5V and 80µ for V G.5V respectively. Calculate the threshold voltage V t and mobility µ n of this MO transistor

36 Integrated Circuit undamentals.6. n n-mo transistor has effective mobility of 750cm /V-s, channel length L of 1.0x10-4 cm, threshold voltage V t of 1.5V, and gate voltage V G 3.0V for a small signal application. Calculate the cut-off frequency using constant mobility model and the case of having short-channel effect where the saturation velocity of the carrier is 10 7 cms Consider an n-mo transistor has channel width W 8µm and channel length L 0.5µm and is made of process where process transconductance K 180µ/V, V tn 0.7V and V DD 3.3V. Calculate the linear drain to source resistance..8. Consider an n-mo transistor that is characterized by ide thickness 80 o, substrate doping concentration 1.x10 15 cm -3, doping concentration of n-type poly gate 1x10 19 cm -3, fixed ide 1x10 11 x1.60x10-19 Ccm - and receiving acceptor ion implant dosage of x10 1 cm - for threshold adjustment. (i) Calculate the threshold voltage of this MO transistor at room temperature. (ii) If the substrate of this MO transistor is biased with 1.0V, what is the ion implant dosage required to maintain same threshold voltage?.9. n n-mo transistor has the following information: Oxide thickness d 100 0, substrate doping concentration N 8x10 14 cm -3, zero bias substrate threshold voltage V tno 0.6V and mobility µ n 580cm /V-s. Calculate the process transconductance K and bulk-threshold parameter γ of the device

37 Integrated Circuit undamentals Bibliography 1. John P. Uyemura, Chip Design for ubmicron VLI: CMO Layout and imulation, Thomson, John P. Uyemura, Introduction to VLI Circuits and ystems, John Wiley & ons, Inc Etienne icard and onia Delmas Bendhia, Basics of CMO Cell Design, TT McGraw Hill, ung-mo Kang and Yusuf Leblebici, CMO Digital Integrated Circuits nalysis and Design, third edition, McGraw Hill, Jasprit ingh, emiconductor Device, McGraw Hill Inc Robert. Pierret, emiconductor undamentals, Volume I Modular eries on olid tate Devices, second edition, ddison-wesley Publishing Co John P. Uyemura, CMO Logic Circuit Design, Kluwer cademic Publishers,