MOS Devices and Circuits

Transcription

1 hapter 3 Microelectronics and emiconductor Materials MO Devices and ircuits

2 Prepared by Dr. Lim oo King 0 Jan 011

3 hapter 3 MO Devices and ircuits Introduction MO apacitor Effects of Bias Voltage apacitance of MO apacitor Threshold Voltage of MO apacitor MOFET urrent-voltage haracteristics Linear Region aturation Region Drain onductance and Transconductance ut-off Frequency MOFET Device cale Dowm MO ircuits p-mofet and n-mofet Logic Gates MOFET Flip-Flop ircuits Random Access Memory Devices Power Dissipation of MO ircuit Exercises Bibliography i -

4 Figure 3.1: A -D schematic structure of a MO device Energy band diagram of the MO structure at thermal equilibrium with zero bias voltage condition Figure 3.: The energy band diagrams of three biased voltage conditions of an ideal p- type MO capacitor Figure 3.3: The energy band diagram of p-type MO device at inversion condition Figure 3.4: The equivalent circuit of an ideal MO capacitance Figure 3.5: (a) Integrated MO capacitor and (b) pn junction capacitor Figure 3.6: apacitance-voltage curve of p-type MO Figure 3.7: The equivalent circuit of the MO capacitor Figure 3.8: V plot for the presence of fixed charge Figure 3.9: The effect of interface state on V plot of a MO Figure 3.10: harge density, electric field, and electrostatic potential of MO in inversion mode Figure 3.11: The structure of depletion-enhancement n-channel and p-channel MOFET Figure 3.1: The structure of enhancement n-channel and p-channel MOFET Figure 3.13: ymbol of depletion-enhancement MOFET Figure 3.14: ymbol of enhancement MOFET Figure 3.15: A -D structure of an n-mofet Figure 3.16: hannel geometry showing the flow of current I D analysis Figure 3.17: haracteristic curve of MOFET Figure 3.18: Evolution of lithography... 1 Figure 3.19: Generalized scaling theory for MO transistor Figure 3.0: The connection of n-mofet and p-mofetand their output states with respect to input states Figure 3.1: n-mofet NOT gate (a) using enhancement n-mofet as load resistor (b) using depletion-enhancement n-mofet as load resistor Figure 3.: (a) p-mofet NOT gate (b) p-mofet NOR gate, and (c) NAND gate designed using depletion-enhancement n-mofet as load resistor Figure 3.3: Block diagram of a MO circuit Figure 3.4: MO circuit of a NOT gate Figure 3.5: MO circuit of a NOR gate Figure 3.6: MO circuit of an OR gate Figure 3.7: MO circuit of a NAND gate Figure 3.8: MO circuit of an AND gate Figure 3.9: MO circuit of Boolean function f(a, B, ) = A (B ) Figure 3.30: A basic bi-stable element Figure 3.31: MO circuit of a bi-stable element Figure 3.3: R flip-flop Figure 3.33: A D flip-flop Figure 3.34: Logic circuit of a JK flip-flop Figure 3.35: T flip-flop Figure 3.36: The six-transistor static RAM cell Figure 3.37: A 1-bit dynamic RAM cell Figure 3.38: harging and discharging circuits of a NOT gate ii -

5 hapter 3 MO Devices and ircuits 3.0 Introduction In this chapter, we will discuss the fundamental theory that needed for the integrated circuit design. We will begin with the effects of bias voltage on the MO capacitor. It is then followed by deriving the characteristic equations of the the MO transistor, which also including the threshold voltage equation. The non-ideal effects of the MO transistor due to scaled down issues are particularly discussed at the last section. 3.1 MO apacitor Before studying MOFET device, let's examine metal ide semiconductor MO capacitor. MO capacitor is the basic building block of today s silicon integrated circuit technology. omplimentary metal ide semiconductor MO, n-channel metal ide semiconductor nmo, p-channel metal ide semiconductor pmo, power MOFET, and many other devices consist of basic MO structure. In the modern device, the metal is replaced by n + or p + polysilicon that has low flat band potential, which enhances the switching speed especially in the MO memory device. The MO structure is formed as a sandwich consisting of a semiconductor layer either p or n-type from a single crystal of silicon, a layer of silicon diide, and a layer of metal or n + or p + polysilicon layer. Figure 3.1(a) shows a typical structure of a MO capacitor. The energy band diagram for ideal MO capacitor at thermal equilibrium with zero biased voltage condition is shown in Fig. 3.1(b) and (c), whereby E F is the Fermi energy level of metal and semiconductor. E is the conduction band of the semiconductor. E V is the valence band of the semiconductor, E i is the intrinsic energy level, E VA is the energy level at vacuum, e m represents the minimum energy required to move an electron from Fermi level of metal to vacuum, and e is defined as the energy required to remove an electron from the Fermi level of the semiconductor to vacuum

6 (a) (b) ` (c) Figure 3.1: A -D schematic structure of a MO device Energy band diagram of the MO structure at thermal equilibrium with zero bias voltage condition

7 3.1.1 Effects of Bias Voltage There are three important regimes when the MO capacitor is under gate voltage bias V G. These are accumulation, depletion, and inversion modes (refer to Fig. 3.(b), Fig. 3.(d), and Fig. 3.(e)). The energy band diagram of a p- MO without gate voltage bias is shown in Fig. 3.(a). Owing to the difference in work function, and interface charge trapping, the valence band is bending toward the Fermi level at the interface, whist the conduction band is bending away from the Fermi level. Accumulation Mode: If the negative bias voltage i.e. V G < 0 is applied between the metal and semiconductor, the Fermi energy level of the metal is raised by an amount qv G and the valence band of the semiconductor bends toward the Fermi level. This would cause the hole to accumulate at the surface near the ide. Flat-band ondition: If the positive bias voltage i.e. V G > 0 is applied to the metal with respect to the p-ype semiconductor, the Fermi level of the metal is lowered by an amount qv G. This would cause the reduction the bend of conduction and valence bands. Further increase of gate voltage will eventually cause the conduction and valence bands aligned with the Fermi level. This is the flat-band condition illustrated in Fig. 3.(c). Depletion Mode: If the positive bias voltage i.e. V G > 0 is applied to the metal with respect to the p-type semiconductor, the Fermi level of the metal is lowered by an amount qv G. This would cause the valence band of the semiconductor to move away from the Fermi level of the metal. As a result, the hole depletes into the bulk as such that the hole concentration near the interface falls below the concentration value in the bulk semiconductor. Inversion Mode: If the positive bias voltage i.e. V G >> 0 is further increased, eventually the conduction band of the semiconductor comes closer to the Fermi level. As a result, electron density near the interface surface starts to increase. Further increase of bias voltage would cause the conduction band of the semiconductor to bend further and crosses the Fermi level of the metal. In this condition, the density of electron increases very high and the semiconductor at the interface is inverted into n-type semiconductor

8 (a) No voltage bias at gate (b) Negative voltage bias at gate accumulation mode (c) Flat-band condition

9 (d) Positive voltage bias at gate depletion mode (e) High positive voltage bias at gate - inversion mode Figure 3.: The energy band diagrams of three biased voltage conditions of an ideal p-type MO capacitor When the surface potential qф, which is potential difference of the intrinsic energy level at the interface with the intrinsic energy level in the bulk, is zero, it implies flat-band condition. For p-type MO, when qф is a positive, it implies depletion mode. When qф is a positive value and larger than q F then inversion occurs. When qф is a negative value, it implies accumulation. imilar explanation is applied to n-type MO device. The energy band diagram of the p-type MO device under inversion condition is shown in Fig

10 3.3. Notice that inversion occurred when the surface potential is twice the Fermi potential, which follows equation (3.1). q (inv) q (3.1) F Figure 3.3: The energy band diagram of p-type MO device at inversion condition The Fermi potential at the bulk q F is F kt N ln q ni A (3.) where N A is the acceptor doping concentration for p-type semiconductor, n i is the intrinsic carrier concentration and kt/q is the thermal voltage. ubstituting equation (3.) into equation (3.1) yields equation (3.3). kt N A (inv) ln = F (3.3) q ni 3.1. apacitance of MO apacitor The ideal MO capacitance mos can be represented as a series combination of the insulator capacitance and the capacitance of semiconductor layer shown in Fig

11 Figure 3.4: The equivalent circuit of an ideal MO capacitance The structures of the MO capacitor and pn junction capacitor are shown in Fig The MO capacitor unlike the reversed bias pn junction is independent of applied voltage because its lower plate is made of heavily doped material. (a) (b) Figure 3.5: (a) Integrated MO capacitor and (b) pn junction capacitor The pn junction capacitor is usually reversed-bias. The capacitance is not constant. It depends on (V bi +V R ) -1/, which is derived junction capacitance j equation for pn junction j q (Vbi N A V ) R 1/ The built-in potential is defined as kt N V bi = A N ln D. The series resistance is considerably higher than the MO q ni capacitor because of higher p-region resistivity. The equation for the MO capacitance mos is shown in equation (3.4).

12 mos (3.4) The capacitance of semiconductor is A dq (3.5) dv where Q is the surface charge of the semiconductor and V is the voltage across the semiconductor. For p-type MO, in accumulation mode, the holes accumulate at the surface. Owing to a small change in bias voltage, it causes a large change in surface charge Q and is much larger than. apacitance of MO mos per unit area shall be apprimately equal to as shown in Fig Thus, mos (3.6) d Figure 3.6: apacitance-voltage curve of p-type MO During depletion mode, the holes are depleted away and the depletion capacitance is equal to = s /W, where W is the thickness of depletion. The capacitance of MO is equal to

13 mos 1 d W (3.7) At inversion, the depletion width reaches its maximum value W max. At this point essential there is no free density. Thus, the capacitance mos reaches its minimum value. mos (min) 1 d W max (3.8) Thus, s << and as the consequence, the capacitor of MO is approaching the value of s. At flat-band position, the capacitance of semiconductor fb per unit area at flat-band is fb (3.9) kt q qn A ubstituting equation (3.9) into equation (3.7) and using = capacitance of MO at flat-band mos (fb) is / d, the mos ( fb ) (3.10) d s skt/ q qn A o far what has been discussed is applicable to the ideal MO capacitor. For the non-ideal MO capacitor, when the MO capacitor is in inversion and depletion modes, the capacitance of semiconductor has two major components. One is the capacitance due to depletion DEP and the other is due to inversion caused by accumulation of minority carrier M. Therefore, the capacitance of semiconductor shall have the relationship as specified in equation (3.11). = DEP + M (3.11) With inclusion of depletion capacitance and capacitance contributed by the minority carrier in inversion mode, an equivalent circuit of the MO capacitor is

14 shown in Fig. 3.7, whereby R is the resistance of semiconductor bulk layer and R GEN is the differential resistance which can be estimated as R GEN d di GEN (3.1) where the s is the surface potential and generation current I GEN is apprimately proportional to the volume of depletion region, which follows equation (3.13). I qn Ad i DEP GEN (3.13) GEN where GEN is an effective generation time constant. Figure 3.7: The equivalent circuit of the MO capacitor ubstituting equation (3.11) into equation (3.4), the MO capacitance mos becomes mos ( DEP M ) DEP M (3.14) In the high frequency ( f) mode whereby, the capacitance due to minority carrier will approach zero. Hence, the MO capacitance mos will become mos DEP DEP (3.15)

15 Likewise for low frequency mode whereby 0, the capacitance due to depletion is at minimum and the minority capacitance will approach the static capacitance of bulk semiconductor. Thus, the MO capacitance mos will follow equation (3.6). In strong inversion M >>, the MO capacitance will approach the capacitance of insulator. One also can say that the magnitude of the capacitances are such that M > > DEP at strong inversion. equal to The change of threshold voltage as the result of fixed charge density N T is d Vt N Tq. This shall mean that presence of positive fixed charge would shift the capacitance-voltage curve toward more negative region as shown in Fig Figure 3.8: V plot for the presence of fixed charge The interface charge has different effect on the capacitance-voltage V of the MO. In the ideal MO, there is no electron state in the band-gap. However, since the i-io interface is not ideal, a certain density of interface states is produced, which lie in the band-gap region. The interface states can be defined as acceptor like or donor like. The acceptor interface state is neutral when it is empty and the Fermi level is below it. If the acceptor is filled with electron, it becomes negatively charged. In this case the Fermi-level is moved above it. The donor interface state is occupied

16 with electron and it is below Fermi level. It becomes positively charge if it is empty and the Fermi level will move below it. Thus, Fermi level is altered by the presence of charge in the interface state. When the interface charge is positive, the V curve shifts toward negative voltage region. When it is negative, the curve shifts toward positive voltage region. The result is shown in Fig If the interface density is maintained below cm -, the effect of interface state on V curve is negligible. Figure 3.9: The effect of interface state on V plot of a MO Threshold Voltage of MO apacitor Threshold voltage V t is defined as the gate voltage V G needed to induce sufficient number of charge carrier in the channel for conduction. It is the minimum applied gate voltage to induce inversion of the channel for conduction. To find the threshold voltage V t, one needs to understand how the voltage is dropped across the MO capacitor. Fig shows the MO structure with a voltage V G applied to its gate. Applying Kirchhoff s voltage law, the gate voltage V G is V G = V + V s (3.16)

17 Figure 3.10: harge density, electric field, and electrostatic potential of MO in inversion mode Equation (3.16) is an ideal equation without considering the trapped charge within the ide that alters the electric field and the differences in the electrical characteristics of the gate and substrate materials. Thus, a term flat-band voltage is used to account these effects, which is 1 V fb = Q Q f (3.17) G where is the work function difference between gate and substrate and G is also apprimately equal to G kt N N A D,poly ln for an n-type q ni polysilicon gate with p-substrate. If the poly gate is a p-type, then the work function difference between gate and substrate is G kt N A,poly ln. The q N A kt N A work function is derived from ln for p-type material and q n i kt N D ln for n-type material. is a work function constant. q n i Q f is the fixed surface charge density at the ide-silicon interface and Q is the trapped charge within the ide. Re-writing equation (3.17), it becomes

18 V fb = kt N ln q A N n D,poly i Q f Q (3.18) Equation (3.16) shall then be modified to V G = V fb + V + V (3.19) The voltage drops across ide V is V = E.d. At semiconductor-ide interface, the surface charge Q is also equal to charge on ide Q, which is ε s E s = ε E. Q is also equal to Q = V = V = E d V. Re-writing equation (3.19), it becomes d. Thus, V is equal to V G = V fb + V + E (3.0) For charge balancing, Q = Q = Q dep, where depletion charge Q dep is equal to Q dep = qn A d dep. The depletion thickness d dep is equal to d dep = V qna 1/. At inversion, V G = V tn and V = F, d dep becomes maximum value. Thus, the maximum depletion charge Q depmax is equal to 4 qn 1/ A F and surface electric Qdepmax 4qN AF field E is E =. ubstituting expression 4 qn 1/ A F to replace ε E in equation (3.1), the threshold voltage equation becomes V tn V fb 4 qn / (3.1) F A F or V tn V fb Q / (3.) F If the substrate of the MO transistor is biased with a voltage V UB then the threshold voltage V tn is redefined as V tn V fb qn ( V ) / (3.3) F A F UB

19 The equation shows that the threshold voltage increases with positive V UB bias since the surface potential is increased by a value V UB. Under normal processing conditions, the flat-band voltage is negative and usually yields a negative threshold voltage. For MO switching circuits that use a positive power rail, a positive threshold voltage is needed. This is accomplished by performing a threshold adjustment ion implant with a dose giving the number of implanted ion. This modifies the equation for the value of the threshold voltage. Implanting acceptor ions into the substrate is equivalent to introducing additional bulk charge at the surface; the implant thus induces a positive shift. The equation to follow for the ion implant adjustment is V tn I V fb qn V / (3.4) F A F UB qd where D I is the dosage, the number implanted ion per unit area. If there is no substrate voltage V UB, in which sometime is called zero body bias then equation (3.3) becomes Vtno V fb F qna (F ) /, where V tno is the threshold voltage without the substrate voltage or body bias voltage. The equation (3.3) can be re-written in terms of V tno and substrate voltage as qna Vtn Vtno (F VUB ) F (3.5) OX qna The term is denoted as gamma, which is called bulk threshold OX parameter. Equation (3.5) clearly shows that as the V UB voltage increases the threshold voltage of the device increases. Rewriting equation (3.5), it becomes V t Vto (F VUB ) F (3.6) The positive sign is used to denote n-mo transistor and negative sign for p- MO transistor. In order to eliminate the effect of parasitic npn or pnp transistor of the n- MO transistor and p-mo transistor, the substrate of the p-mo transistor, which is an n-type semiconductor, is usually biased with V DD voltage, whilst the substrate of n-mo transistor, which is p-type semiconductor, is biased with V voltage i.e. zero volt.

20 By Kirchhoff s voltage law, the source voltage V and substrate voltage V UB relationship is V +V -UB +V UB = 0. Equation (3.6) therefore can be written as one equation for p-mo transistor and one for n-mo transistor. They are V V tp Vtpo (F V V UB ) (3.7) tn Vtno (F V V UB ) (3.8) With substrate of p-mo transistor biased with V DD, and source and substrate are tied together, the V UB- is equal to zero. Therefore, the threshold voltage of p-mo transistor is V tp Vtpo (F VDD) F (3.9) With the substrate of n-mo transistor biased with V and source and substrate are tied together, V -UB is equal to zero. Therefore, the threshold voltage of the n-mo transistor is F F V tn tno (F ) F Vtno V (3.30) One can see that V tp of p-mo transistor is lower than V tpo, whilst the V tn of n- MOFET is same as V tno for the substrate biased condition mentioned above. 3. MOFET A MOFET is a voltage control current device and is essentially consist of a MO capacitor and two diffused or implanted regions that serve as ohmic contacts to an inversion layer of free charge carriers with the semiconductorsilicon diide interface. The metal gate is essentially either p + or n + polysilicon type. There are two types of MOFET namely depletion-enhancement DE and enhancement E types. Figure 3.11 and 3.1 show the difference between the types. The DE type has a narrow channel adjacent to the gate connecting the drain and source of the transistor. It can operate in either depletion mode or enhancement mode. The mode of operation is like the JFET

21 The E type does not have a narrow connecting channel. It operates by forming a conducting channel of the same type like the source and drain. The channel is formed either by attracting electron or depleting away electron to form an n-channel or p-channel connecting the source and the drain. MOFET not only can be used to design amplification circuit. It can also be used as a capacitor and a resistor. This capability makes the VLI design simpler because there is no need to use other element for capacitor and resistor in the design. Figure 3.11: The structure of depletion-enhancement n-channel and p-channel MOFET Figure 3.1: The structure of enhancement n-channel and p-channel MOFET The four-terminal and three terminal symbol of both depletion-enhancement and enhancement MOFET types are shown in Fig and 3.14 respectively. Note that for most cases, by design the substrate is connected to the source. ymbols other then those symbols shown in Fig and 3.14 are used too. The reader needs to identify them careful during any circuit analysis

22 (a) n-channel (b) p-channel Figure 3.13: ymbol of depletion-enhancement MOFET (a) n-channel (b) p-channel Figure 3.14: ymbol of enhancement MOFET Figure 3.15 illustrates the -D structure of an n channel MOFET with detail voltage biasing. Figure 3.15: A -D structure of an n-mofet

23 Gradual hannel Apprimation Model and onstant Mobility Apprimation Model can be used to study the characteristics of MOFET. The model is used to study how the conduction channel of the MOFET is changed by the horizontal electric field generated by the drain to source voltage V D and how the conducting channel is modulated by the vertical electric field generated by the gate to source voltage V G. This is done by studying the drain to source current I D versus drain to source voltage V D characteristic for different applied gate to source voltage V G and the transconductance of the device, which is the study of I D current changes with the change of V G voltage. These two studies are connected with the physical studies of the linear and saturation regions of the drain to source characteristics with various gate-to-source voltage V G. Based on this understanding, one has to look at the two dimensional Poisson s equation in order to understand the actual conduction mechanism of current from drain to source via the inverted channel. There are two electric field components present in MOFET when it is in operation. These fields can be represented by the two dimensional Poisson s equation that has one horizontal field E X and one vertical field E Y. E X X E Y Y (3.31) Gradual hannel Apprimation Model is true only if X is very small and X constant so that the Poisson s equation can be apprimated as E E Y Y (3.3) The vertical electric potential of the conduction channel with thickness d is given as EY Y EY. d E Y Y s V d G V t kt / q (3.33) On the other hand, the variation of horizontal electric field can be apprimated as

24 E X X V D (3.34) L where L is the channel length and V D is the voltage between drain and source of the MO transistor. Here, it is assumed that the field strength changes gradually from a small value near the source to a value of the order V D /L near the drain. The mobilities of the electron and hole n, p of the MO transistor are not the same as the mobility in the semiconductor bulk moving into the crystal lattice. Knowing the electrons or holes are moving on the surface between the semiconductor and ide interface, their mobilities are very much depending on the surface impeding collision and ionized impurity scattering. However electrons and holes moving not closed to the interface would have a higher mobility. One also has to consider the influence of horizontal electric field resulted from drain to source voltage. Thus, there is an effective mobility for both hole and electron. If the drain-to-source voltage is small, the effective channel length and carrier charge will be more or less uniform from the source to drain and effective mobility will be essentially the same for all x values. However, one cannot ignore the effect of gate voltage on the mobility. As the gate-to-source voltage increases, the electron is moving closed to the interface. The effect of scattering will be more. Thus mobility decreases which can be observed from equation (3.35). n 0 1 (VG V t ) (3.35) where 0 is constant and is the mobility degradation parameter. It can be shown that the effective mobility n of electron is about 0.6 of the bulk mobility at (V G V t ) = 4V to about 0.5 for (V G V t ) = 13V urrent-voltage haracteristics The surface potential above threshold regime is equal to V s (x) = ( F V( x)), where V(x) is the channel potential at position x along the channel in the direction from source to drain. However, from Gradual hannel Apprimation Model, one can say that V(x) is equal to zero at the source side because the source and the substrate are normally shorted together and biased at V for an

25 n-mo transistor and biased at V DD for p-mo transistor. Thus, V(x) is equal to the drain-to-source voltage V D at the drain side. This shall mean that the gate voltage with respect to source V G is equal to V G Q s (x) V fb F V(x) (3.36) Q s (x) is the surface charge, which is consisting of free electron charge Q n (x) and fixed charge acceptors in the depletion region Q DEP (x). Therefore, the surface charge of is given by equation (3.38). Q s (x) = Q n (x) + Q DEP (x) (3.37) From onstant Mobility Apprimation Model, the electron mobility µ n is constant and there is only drift and negligible diffusion, the drain-to-source current I D can be calculated from current density J n = q n ne after ignoring the dn diffusion portion qd n. Indeed drift current is only required to be considered dx since the drain is reversed biased with respect to source. Using the channel geometry of the current flow shown in Fig. 3.16, drainto source-current I D is made of summation of all small rectangular current elements with surface area Wdy across the channel of thickness dx for the whole channel length L. Figure 3.16: hannel geometry showing the flow of current I D analysis Thus drain to source current can be calculated equation (3.38)

26 I D J ny dydw W y(x) 0 J ny dy y(x) dv(x) W q n (x, y)n s (x, y) dy dx 0 (3.38) where the second expression of equation (3.38) is equal to effective mobility of the electron n, which is equation (3.35). Knowing that the threshold voltage is V t = F +V fb + Q DEP and V G V fb V(x) V (x) V after inversion with F mobile ion density n s, the surface free charge density per unit area n s (x) in x- direction is N A V(x) F n(x) VG F Vfb V(x) (3.39) q q ubstituting equation (3.39) into I D dx = q n n s WdV(x) and integrating the equation with the boundary conditions for V( x) x0 = 0 and V( x) x L = V D and x = 0 to x = L, I D, it yields the drain to source equation (3.34). OX ns I D W n VG Vfb L qn 3 A F V D V D V 3 / D F 3 / F (3.40) At pinch-off condition where n = 0 and V( x) x L = V D = V DAT, equation (3.40) is equal zero for V(x) = V D. olving the quadratic equation for V D shall yield, V D qn V DAT VG F Vfb A 1 (VG Vfb ) 1 qn A (3.41) Beyond pinch-off, the drain current I D essentially remain constant but it may be complicated by channel modulation and other effects. 3.. Linear Region For very small drain to source voltage where V D << (V G -V fb - F ) and V D F, equation (3.40) can be simplified to equation (3.4) and expanding the Taylor s series for the second term

27 W n VD I D (VG V t )VD L (3.4) This is the equation for the linear region of the MOFET s characteristics aturation Region After pinch-off, I D is assumed to be constant. It is true only if the doping concentration is low and the ide thickness is thin. The term in equation (3.41) involving N A / can be ignored and terms involving NA / can be retained. This gives the shall mean that A V DAT = V V V V 1/ G qn fb F G fb (3.43) If the voltage drops across the ide is negligible, then at strong inversion the quantity (V G V fb ) is equal to V G V fb F. Based on the above assumption, equation (3.43) can be simplified as V DAT = V V (3.44) G t After substituting equation (3.43) into equation (3.43), I DAT W L V V n G fb qn 3 A F (V G (V V ) V V 3 / G t F t G 3 / F V ) t (3.45) ince the current does not change with V D in this equation, further simplification can be done once pinch-off occurred. i.e. NA / is small such that V t V fb + F. The equation (3.45) shall be simplified to I W (V n G t DAT VG Vt (3.46) L W n = (VG V t ) L V ) This is the equation for the saturation region of the MO transistor characteristics.

28 A typical ideal characteristic curve of an n-mo transistor is shown in Fig The curve shows three regions of the characteristic, which are the linear, saturation, and cut-off regions. The MO transistor device will be turned off if the V G voltage is less than the threshold voltage V t. Note also that the dotted line is a line denotes that V D = V G V t. This is a dividing line that determines the operational condition of the MO transistor. It is also the line showing the pinch-off the current. If the condition is V D < V G V t then the MO transistor is in linear region or at time it is referred as triode region. This is the region that the MO transistor device would work as a digital logic device. If the condition is such V D > V G V t then the MO transistor is in saturation region. This is the region that the MO transistor device works as an amplifier device. Figure 3.17: haracteristic curve of MOFET 3..4 Drain onductance and Transconductance Having defined the equations for linear and saturation regions of the MO transistor, the next two important parameters of MO transistor to be defined are the drain conductance and the transconductance. The drain conductance g D is defined as

29 g D I V D D V G ons tan t W n (VG V t ) (3.47) L Drain conductance is also equal to equation (3.4) if the term V D is moved to the left-hand side of the equation as denominator. The transconductance g m at saturation region is defined as g m I V DATT G V D constan t W n L (V G V ) t (3.48) 3..5 ut-off Frequency The cut-off frequency f max of the MO transistor is defined as the maximum operating frequency of the MO transistor when it is in saturation mode with the assumption that the mobility of the carrier is constant. Thus, the cut-off frequency for p-mo transistor is defined as f max g m G (3.49) where G is the gate to source capacitance, which estimated to be ide capacitance per unit area multiplies by area WL. Thus, the gate to source capacitance is WL G. g (V V ) m p G t f max (3.50) G L For the short channel device, the cut-off frequency is assumed to depend on the transit time t tr of the carrier in the channel. Thus, f max 1 t tr (3.51) where by t tr is also apprimately equal to the channel length L divided by carrier saturation velocity s. i.e. t rr = L/V s

30 3..6 MOFET Device cale Down There are four main generations of integrated circuit technologies: micron, submicron, deep submicron, and ultra deep submicron technology, as illustrated in Fig The submicron era started in 1990 with 0.8m technology. The deep submicron technology started in 1995 with the introduction of lithography thinner than 0.3m. Ultra deep submicron technology concerns with lithography below 0.1m. Figure 3.18 shows that research has always kept around five years ahead of mass production. It can also be seen that the trend towards smaller dimension has accelerated since In 007, the lithography was decreased to 65nm. The lithography expressed in µm corresponds to the smallest patterns that can be implemented on the surface of the integrated circuit. Today the actual implementation of the lithography has reached nm. Figure 3.18: Evolution of lithography As mentioned early, in order to achieve higher density logic integration, the approach is to develop sub-micron size device structures. Effects which are negligible in large MOFET become distinct and extremely important when the transistor dimensions are reduced. caling theory provides a general guide to make MOFET smaller. It is not possible or desirable to follow every aspects of the theory. However, it remains a useful metric for measuring progress in device - 1 -

31 physics especially the simulation or prediction of the behavior of the device with smaller dimension. caling theory deals with the question of how the device characteristics are changed as the dimensions of the device are reduced in an idealized welldefined manner. caling theory is ideal ignoring many small-device effects that govern the performance of MOFET. It is often desirable to adhere to the large device models for simplicity but modify the parameters to account for the more important changes in the transistor parameters. caling of the device to smaller dimension affects parameters such as threshold voltage and mobility. maller channel length decreases the threshold voltage. Narrower device increases threshold voltage. mall channel length increases horizontal electric field that causes the MOFET to operate with saturation velocity. This reduces the drain current of the device. High electric field means high energetic carrier that can enter the ide to become trapped charge and affects the threshold voltage of the MO transistor. The drain and source of the MOFET are usually much heavily doped than the bulk. ouple with high electric field, hot ion tunneling is unavoidable. This issue causes leakage. In order to resolve this problem, lightly doped drain LDD approach is adopted for the design of small dimension MO transistor. everal schemes can be constructed from scaling rules shown in Fig is the dimensional scaling factor and k is factor by which voltages are scaled. One of the earlier scaling methodologies is based on constant-field scaling, which keep electrical field constant. In this method, dimensional factor is made equal to k. This approach is theoretical viable that has increased the speed, reduction of voltage swing and capacitance. It is being used to scale down the device to 1.0µm. caling to 1.0µm is in fact closed to constant-voltage scaling, which is by making k = 1. In this approach voltage swing stays the same, but device current increases due to increase of ide capacitance. ince drive current increases roughly as the square of supply voltage, constant-voltage produces more speed improvement than constant-field scaling. Using constant-voltage approach and considering a MO transistor with a channel width W and a channel length L such that the channel area is A = LW and introducing the concept of a scaling factor >1, a new scaled device is created with reduced dimensions W and L where W W ' and L A A. L ' '. The reduced scaled area A is equal to

32 imilarly, the ide thickness is is ' d ' d Thus, the reduced ide capacitance. imilarly, the reduced process parameter K d K ' and ' ' device parameter is. Threshold voltage V t and drain-to-source voltage V are to be scaled. With all parameters being scaled down, the scaled down ' D drain current is ' I D I D. Parameters Variables caling Factor Dimensions W, L, d, x j 1/ Potentials V ds, V gs 1/k Doping concentration N A, N D /k Electric field E /k urrent I ds /k Gate delay t delay k/ 3.3 MO ircuits Figure 3.19: Generalized scaling theory for MO transistor In the MO circuit particularly the MO circuit, both p-mofet and n- MOFET are used as complimentary pair. In the normal operation, the n-mo transistor and p-mofet are alternatively switched-on and off. There is a circumstance that both n-mofet and p-mofet are in switch-off state. This is termed as tri-state. In this particular state, the output impedance of both transistors is very high. This state is particularly important because it helps to reduce the circuit connection routing by connecting the output of all devices to a common output bus. There is no real condition where both p-mofet and n- MOFET are in switched on state. This happens only in fraction of second during switching transition. For any MOFET, once its absolute gate-to-source voltage V G is greater than its absolute threshold voltage V t, the transistor is switched on. p-mofet is a logic 0 asserted high output device, which means that when p-mo transistor is switched on with logic 0 and its output is at logic 1. According to the biasing condition of p-mofet, the source voltage V should be larger than the drain voltage V D. This is necessary because it will enable the hole carrier to flow from source to drain of the transistor. Thus, the source of p- MOFET is usually connected to V DD power rail. ince it is a logic 0 asserted high device, a logic 0 at gate will create a condition that the absolute value of

33 gate-to-source voltage is greater than the absolute value of threshold voltage of the transistor. The p-mofet is switched on and its output will provide logic 1. The reason being, the V DD voltage is appearing at the drain of the device. n-mofet is a logic 1 asserted low output device. This shall mean that logic 1 is used to switch on n-mofet and the output is at logic 0. According to the biasing condition of n-mofet, drain voltage V D should be larger than the source voltage V. This is necessary for the electron carrier to flow from the source to drain. This shall mean that the source of the transistor should be connected to V rail. A logic 1 applied to the gate will create a condition that the absolute value of gate-to-source voltage is greater than the absolute value of threshold voltage of the transistor. Thus, the n-mofet is switched on with its output at logic 0. The reason being, the V voltage is appearing at the drain of the device. Figure 3.0 illustrates how the n-mofet and p-mofet should be connected and their output states with respect to input states. (a) n-mofet (b) p-mofet Figure 3.0: The connection of n-mofet and p-mofet and their output states with respect to input states If the input of the transistor shown in Fig. 3.0(a) is A, then the Boolean equation of the output is equal to Output = A 0 (3.5) If the input of the transistor shown in Fig. 3.0(b) is B, then the Boolean equation of the output is equal to Output = B 1 (3.53) p-mofet and n-mofet Logic Gates The design of logic gate using p-channel and n-channel depletion-enhancement and enhancement MOFET devices is shown in this sub-section. As you have

34 learnt in the fundamental electronics course, the transistor irrespective of the type, it can be connected as the load resistor to the n-channel pull down circuit to form the logic circuit. The n-mofet NOT gate designed using depletionenhancement n-channel and enhancement n-channel MOFET as load resistor are shown in Fig. 3.1 respectively. (a) (b) Figure 3.1: n-mofet NOT gate (a) using enhancement n-mofet as load resistor (b) using depletion-enhancement n-mofet as load resistor When the input voltage V in is greater than the threshold voltage V tn of the n- MOFET, which is logic 1, the n-mofet is switched-on, the output voltage V out shall be at apprimately 0.1V, which is a logic 0. When the input voltage V in is less than the threshold voltage V tn of the n-mofet, the n-mofet is switched-off and the voltage at output V out shall be at V DD, which is logic 1. The NOT gate, NAND gate, and NOR gate designed with p-mofet are shown in Fig. 3.. When V in voltage of p-mo NOT gate is less than the threshold voltage V tp of p-mo transistor, the MOFET will be switched-on and the output V out shall be at 0.1V, which is logic 0. When both input A and B of NAND gate are tied to voltage less than threshold voltage V tp of the p-mo transistor, which is logic 1, both p-mo transistors will be switched on. As the result the output voltage V out shall be - 0.1V, which is logic 0. When both input A and B of NOR gate are tied to a voltage greater than the threshold voltage V tp of p-mo transistor, which is logic 0, both p-mo

35 transistors would switched off. The output V out shall be at V DD, which is logic 1. (a) (b) (c) Figure 3.: (a) p-mofet NOT gate (b) p-mofet NOR gate, and (c) NAND gate designed using depletion-enhancement n-mofet as load resistor MO circuit contains a network of p-mofets with their sources connected to V DD connected in series a network of n-mofets in which their sources are connected to V and both of these networks have the common input. Figure 3.3 shows the block diagram of a generalized static MO circuit. Figure 3.3: Block diagram of a MO circuit

36 The MO circuit diagram of the NOT gate is shown in Fig The circuit is consists of a p-mofet connected in series with an n-mofet. Figure 3.4: MO circuit of a NOT gate The MO circuit of a NOR gate is shown in Fig It consists of two series p-mofets and two parallel connected n-mofets. Figure 3.5: MO circuit of a NOR gate

37 The logic function for a two-input OR gate can be written as f(a, B) = A B. This shall mean that the logic function can be implemented with a NOR gate connected to a NOT gate. Fig. 3.6 shows the circuit of the OR gate. Figure 3.6: MO circuit of an OR gate The circuit of a MO two-input NAND gate is shown in Fig It consists of two series connect n-mofets and two parallel connected p-mofets. Figure 3.7: MO circuit of a NAND gate

38 MO circuit of an two-input AND gate is shown in Fig The circuit consist of a NAND gate connected to a NOT gate. Figure 3.8: MO circuit of an AND gate One of the most powerful aspects of building logic circuit in MO is the ability to create a single circuit that provides several logic operations in the integrated manner. This is called complex or combinational logic gates. Let s consider the Boolean function f(a, B, ) = A (B ). Based on this function, one can see that the simplest way to design the function is one OR gate and one NAND gate. This shall mean that to design this function, a total of ten MO transistors are required. Owing to the design constraint on a VLI design, one ought to consider the performance and the number of MO transistor on the silicon chip. Thus, the traditional approach should not be used as the straight forward design. The AND-OR-NOT AOI and OR-AND-NOT OAI circuit approaches shall be used, which required utilizing the hannon s expansion of the Boolean function to determine the OAI circuits. Based on the logic function f(a, B, ) = A (B ), the circuit of the logic is shown in Fig

39 Figure 3.9: MO circuit of Boolean function f(a, B, ) = A (B ) 3.3. MOFET Flip-Flop ircuits Flip-flop is the primitive memory element, which is shown in Fig It contains two NOT gates where the outputs are fed to inputs of the opposite NOT gate. The MO circuit of the bi-stable element is shown in Fig Figure 3.30: A basic bi-stable element

40 When logic 1 is connected to input A, the output Q is at logic 0. The logic state is input to second NOT gate and its output Q will be at logic 1, which is the same state as the input A. In this manner, the output Q and Q would stay at its respective logic state even if the logic 1 at input A is removed. Figure 3.31: MO circuit of a bi-stable element When logic 0 is connected to input A, the output Q will be at logic 1. The logic state is input to second NOT gate and its output Q will be at logic 0, which is the same state as the input A. In this manner, the output Q and Q would remain at its respective logic state even if the logic 0 at input A is removed. ombining both conditions of logic states, the bi-stable element forms the basic memory bit. The bi-state element has two stable states and one unstable state. The unstable state occurs at the mid-point voltage. At this point all transistors are in saturation mode and also at the highest potential energy. The R flip-flop is shown in Fig The output Q is Q = LK Q and Q = R LK Q. Using DeMorgan s theorem, Q is also equal to Q = ( LK ) Q, which forms the p-mo transistor circuit of the output Q. Output Q is also equal to output Q. ( R LK) Q, which forms the p-mo transistor circuit of

41 Figure 3.3: R flip-flop The D flip-flop is shown in Fig The output Q is Q = the output Q is Q = Q D = Q D. D Q = D Q, whilst Figure 3.33: A D flip-flop The JK flip-flop is shown Fig The Boolean function of output Q is Q = Q JLK Q, which is also equal to ( Q J LK ) Q. The Boolean function of Q is Q = Q KLK Q, which is also equal to ( Q K LK ) Q. Figure 3.34: Logic circuit of a JK flip-flop

42 The T flip-flop is shown in Fig The Boolean function of output Q is Q = Q TLK Q = ( Q T LK = Q TLK Q = ( Q T LK ) Q and the Boolean function of output Q is Q ) Q. Figure 3.35: T flip-flop Random Access Memory Devices There are many methods to design the static and dynamic random access memory cells. In this section, three methods are presented. They are sixtransistor static memory cell, three-transistor dynamic memory cell, and onetransistor dynamic memory cell. We shall only discuss the six-transistor static memory cell and one transistor dynamic RAM cell. The six-transistor static memory cell is shown in Fig MO transistor M 1, M, M 3, and M 4 forms the bi-stable memory element, whilst n-mo transistor M 5 and M 6 are served as pass-transistors. During the write cycle, the desired logics are placed on bit line and BIT line. When the WORD line is asserted, the desired data will be latched into the bi-stable memory element. For an example, to write logic 1 into the memory, the BIT line is set at logic 1, whilst the BIT line is at logic

43 Figure 3.36: The six-transistor static RAM cell However, due to high pack density of the memory cell whereby many column memory cells are connected in the same bit line, the total drain-bulk capacitance of the pass-transistors is sufficiently large that the charging and discharging of the bit lines would take long time. Thus, during the read cycle, the BIT and BIT lines are pre-charged to the pre-defined level, which is usually 0.5 of V DD voltage level. These lines are then allowed to float. When the WORD line is asserted, the BIT line and BIT line begin to charge or discharge that reflect the logic level stored in memory cell. The small change in voltage level is passed to the sense amplifier for output user. The read cycle is a destructive cycle whereby the data stored in the memory can be erased. Therefore, it is necessary to refresh the memory. Other mean to prevent the bit data being erased is to design the pass-transistor to have large width and length. But this is not desired because in the modern design, scale down is necessary to save cost and fast access time. One-transistor dynamic RAM cell uses capacitor to temporarily store the charge on a memory capacitor M. A simple 1-bit dynamic RAM cell is shown in Fig During the write cycle, the logic level is placed on the BIT line. The WORD line is then asserted to charge or discharge the memory capacitor M. The capacitor is leaky and will not hold the charge for long time. Thus, it is necessary to refresh it periodically. During the read cycle, the BIT line is pre-charged and placed in tri-state mode. When the WORD line is asserted, the BIT capacitor BIT is either charging or discharging depending on the charge stored in memory capacitor

44 M. The sense amplifier is then used to detect small change in voltage level and output the appropriate logic level. Figure 3.37: A 1-bit dynamic RAM cell Read cycle is a destructive operation. Thus, the data must be re-written into the memory capacitor M. 3.4 Power Dissipation of MO ircuit There are two types of power dissipation associated with MO circuit. They are static power dissipation P D and dynamic power dissipation P dyn. When the circuit is not in operation the power dissipation is known as static power dissipation P D. When it is in operation, it is known as dynamic power dissipation P dyn. At static mode, the output of the logic gate is either at logic 1 or logic 0, whereby in both cases, one of the MO transistors is at cutoff mode. ince the p-mo transistor is connected in series with n-mo transistor, theoretically, there is no power dissipation at static condition. However, due to sub-threshold conduction and other leakage associated with the design, there is a small amount of current in pico-ampere per gate. This current is termed as quiescent leakage current I DDQ. Thus, static power dissipation is P D = V DD I DDQ. One has to take note that during the transition of the output voltage either changing from logic 1 to logic 0 or from logic 0 to logic 1, the maximum dc current consumption occurred when output voltage is equal to input voltage, which is the mid-point voltage. At this point, both p-mo and n-mo transistors are in saturation mode. It is obvious to say the maximum current drain occurred when the both n-mo and p-mo transistors are connected in series are in saturation mode. The dynamic power dissipation P dyn can be calculated with the charging and discharging figure shown in Fig

45 The output is charged to V DD during transition to logic 1 and discharged to logic 0 during transition to logic 0. The sum of charging and discharging time is considered as equal to the period T of the input frequency. Thus, the dynamic current i DD is equal to Q/T, where Q is the charge of output capacitor out, which is also equal to V DD out. The dynamic power P dyn is equal to Q P dyn = V DD i DD = V DD = out V f (3.54) T DD (a) Input voltage (b) harging output capacitance out (c) Discharging output capacitance out Figure 3.38: harging and discharging circuits of a NOT gate After adding the static power P D, the total power dissipation P D of the NOT gate is Exercises P D = V DD I DDQ + out V f (3.55) DD 3.1. alculate the Fermi potential of a silicon p-mo if the doping concentration of the p-type is.0x10 16 cm A pn + junction capacitor has N A equal to 1.0x10 15 cm -3 and N D = 1.0x10 17 cm -3. alculate the built-in potential of the capacitor and its junction capacitance when it is reverse biased with.0v The -V characteristic of a p-mo is shown in the Fig. below. Explain the reason why the low frequency capacitance of the MO is apprimately equal to the ide capacitance at inversion mode