GENERATION OF INTERFACE STATES DURING THE ELECTRICAL STRESSING OF MOS TRANSISTORS

Transcription

1 Philips J. Res. 42, , 1987 R 1172 GENERATION OF INTERFACE STATES DURING THE ELECTRICAL STRESSING OF MOS TRANSISTORS by A. BHATTACHARYYA* and S.N. SHABDE** Philips Research Laboratories Sunnyvale, Signetics Corporation, Sunnyvale, CA , USA Advanced Technology Development Sunnyvale, CA , USA Abstract We have investigated the generation of interface states and the fixed charges in the oxide leading to MOS device degradation under two different types of stress: a) constant-current stress applied between the gate and drain, and b) conventional hot-electron stress, i.e., Va =~VD (maximum substrate current condition). For both the constant-current and hotelectron stress, the transconductance of the transistor decreases monotonically 'with stress duration. From the change in the slope of the subthreshold characteristics we have calculated the change in the density of interface states (Di') as a function of stress duration. We observe that the value of (Di') increases monotonically with stress duration for both stresses. However, the behaviour of fixed charge generation is somewhat different for the two stress conditions. In the case of constant-current stress, the threshold voltage is found to decrease initially and then increase, implying an initial generation of positive charge and then negative charge. In the case of hot-electron stress, no evidence of hole generation and trapping is found. After applying both stresses, the subthreshold current is dependent on the drain voltage VD for VD> 3kTlq, which suggests a short channel behaviour. After applying the stress we have two transistors in series, the transistor near the drain being a shortchannel device with a higher threshold voltage due to fixed negative charge generated near the drain by electron trapping. Keywords: electric field effects, interface electron states, oxidation, metalinsulator-semiconductor devices, silicon. 1. Introduetion The technique of constant-current stress has been used in the past to study the breakdown phenomenon in gate oxides. It has been postulated 1) that the oxide breakdown is closely related to the generation of a very high density of defects in the stressed oxide. These defects act as efficient and stable electron traps. In contrast to the above argument, it has also been proposed 2) that oxide breakdown is due to localized field enhancement at the cathode interface due to hole trapping. These studies were performed using MOS capacitor structures.. Philips Journalof Research Vol. 42 No. 5/

2 A. Bhattacharyya and S.N. Shabde Using a technique of constant-current stress between the gate and drain of an MOS transistor, we have examined previously") the mechanism of degradation of the transistor characteristics. From the transistor characteristics, we proposed 3) that the device degradation is a combined effect of electron trapping and trapping of holes created by impact ionization due to the high electric field (> 8 MV/cm) across the oxide. In this present work, we have compared the generation of interface states and the fixed oxide charge under two types of stresses, a) the constant-current stress, and b) a conventional hot electron stress. During the hot-electron stress, the bias conditions used were VG = VD/2, i.e., the gate voltage is half of the drain voltage (maximum substrate current condition). We have monitored the degradation of the transconductance, threshold voltage and the change in the subthreshold slope as a function of stress duration. While the transconductance degratation is related to the interface state generation, the threshold voltage shift is affected by the generation of fixed charges. We have calculated changes in the interface state density Dit as a function of stress time for both type of stresses, by monitoring the changes in the subthreshold slope. Before applying the stress, the subthreshold slope is independent of VD for VD> 3 kt/q, as expected for a long channel device 4). However, after applying the stress we find that the subthreshold slope is different for different values of VD' namely 0.1,1.0, and 5V. Moreover, this difference becomes more pronounced with increase in the stress duration. This suggests, that after both type of stresses, short-channel effects are dominant 4) and we have two transistors in series. Near the drain region, due to the electron trapping, we have a short-channel transistor with a higher value of the threshold voltage 5). p p Substrate Substrate (a) Constant Current Stress (b) Hot Electron Stress Fig. 1. Cross-sectional view of an MOS transistor for a) the constant-current stress between the gate and drain and b) the hot-electron stress with VG = V 0/2 584 Phitips Journalof Research Vol. 42 No. 5/6 1987

3 Generation of interface states during the electrical stressing of M OS transistors 2. Experimental conditions N-channel MOSFETs were fabricated using conventional polysilicon gate technology with p-type 17 to 33 n cm <100> Si substrate. The devices used in this investigation had a channel length and width of 1.5 and 20 IJ.m, respectively. The gate oxide thickness was 250A and was grown at 950 oe in dry 02. The source and drain regions were implanted with As diffused to a final junction depth of 0.3IJ.m. The transconductance degradation, the subthreshold slope, and the threshold voltage before and after stressing were measured by using an HP4145 test system. For the constant current stress across the gate and drain, we used a programmable Keithley 220 current course. The gate was connected to the positive terminal with the drain being grounded. The source and substrate were kept floating. The voltage across the gate and drain was monitored with a high input impedance electrometer (Keithley 616) and was read with an HP3445A digital voltmeter. The HP9845B desk top computer and HP9885S flexible disk drive were used for storing and analysing the data. Figure 1 shows a cross-sectional view of an MOS transistor for the constant-current stress between the gate and drain, and the hot-electron stress with V G =Vo/2. 1ft-~-~-~-'--~-r--r--,--i11-r------, V GD (V) t 10 p 80 gm (!LU) 70 t o ~1-==250=-...J40 -t(s) Fig. 2. Variation of the voltage VOD across gate and drain vs. time t, and maximum transconductance gm vs. time t, for a constant current stress of IOnA for an MOS transistor with WIL = 20/1.5. Inset shows cross-sectional view of an MOS transistor for the constant-current stress across gate and drain. Philips Journalof Research Vol. 42 No. 5/

4 A. Bhattacharyya and S.N. Shabde- 3. Results and discussion Figure 2 shows a plot of gate voltage vs. time for a constant current stress of 10 na across the gate and drain of 'an n-channel MOS transistor with WIL = 20/1.5, and the degradation of the maximum value of the transconductance (gm) as a function of stress duration. The inset of fig. 2 shows a cross-sectional view of an MOS transistor for constant-current stress. For the constant-current stress of 10 na, the increase in gate voltage necessary to maintain the current is due to electron trapping in the gate oxide in the gate-to-drain overlap region 6). In addition, electron traps are believed to be generated as a result of high-field stress 7). This trap generation explains the non-saturating behaviour of the gate voltage versus time plot. The gate voltage increases with time until breakdown, at which point the gate voltage necessary to maintain a constant current drops suddenly to almost zero. From such experimental data, it is tempting to conclude that the oxide breakdown is a result of electron trapping I). From fig. 2, we note that the maximum value of transconductance of the device decreases monotionically with stress duration, with the rate of degradation more pronounced till = 150 s. The transconductance degradation is related to the generation of interface states. The mobility degradation as a function of interface states generation can be expressed by an empirical relationship"). (1) with ILo = g(N a ), and a = g(N a ), where Dit is the density of interface traps (cm- 2 ey-i), Na is the acceptor concentration (cm- 3 ) and ILo is the initial mobility (crrr'/vs). By taking the difference of the inverse of the transconductance after and before stressing, we have gm(o) - gm(t) gm(t) (2) Thus, the degradation of transconductance (Llg m ) of the transistor is directly related to the generated interface trap density (LlD it ), based on the empirical relationship of eq. (1) 8). 586 Philip. Journalor Research Vol. 42 'No. 5/6 1987

5 Generation of interface states during the electrical stressing of M OS transistors We have calculated the interface trap density as a function of stress duration time by monitoring the change in the subthreshold slope for VD = 0.1 and 5 V. The shift of the subthreshold slope is given by ref. 4. kt t 6.S = Set) - S(O) = (In 10)~IlDit' e eo (3) where 6.Dit is the change in the interface trap density and tox is the oxide thickness. Figure 3 show the subthreshold characteristics before and after a constant-current stress of 10 na for 150 s, for two values of the drain voltage, namely V D =O.l and 5V. For constant-current stress, fig. 4 shows plots of the subthreshold slope as a function of the stress duration calculated for two different values of VD' namely, 0.1 and 5V. We note that at time t= 0, the subthreshold slope is independent of VD. With increase in stress duration, the subthreshold slope increases and the difference for the two different values of VD becomes more pronounced. For constant-current stress, fig. 5 shows plots of the change in the interface trap density versus stress duration for the two different values of VD.. For any value of VD' the value of the interface states increases rapidly with stress till oxide breakdown ocç,urs.the difference between the value of Dit for the two values of VD' also increases with stress time. However, one should consider the value of Dit for small value of VD as more realistic, since it is unaffected by the short-channel effect. ID (A) t STRESS 10nA Time= VG(V) Fig. 3. Subthreshold ID, VG characteristics for values of VD = 0.1 and 5 V (constant-current stress). Solid line-before applying the stress, dashed line-after applying the stress. Philips Journalof Research Vol. 42 No. 5/

6 A. Bhattacharyya and S.N. Shabde s (mv/'300 decode) t ot. VD = 0.1V VD = 5.0V 100 0~-L~2~OO--~-4~0-0~--ro~0~L_-80LO~ _1(5) Fig. 4. Subthreshold 'current stress). slope S versus stress duration I for values of VD = 0.1 and 5 V (constant- Figure 6 shows the subthreshold characteristics before and after applying a hot-electron stress for 1 hr with VG = 3.5 V, VD = 7.0 V, for three different values of the drain voltage, namely VD = 0.1, 1.0, and 5 V. As before, from the subthreshold slope, we calculate the density of the interface states. Figure 7 shows the density of interface states as a function of hot electron stress duration calculated for different values of the drain voltage. Comparing figs. 5 and 7, we find that for both the constant-current stress and the hot-electron stress, the density of interface states increases rapidly with stress duration. Figure 8 shows an initial decrease in the value of the threshold voltage during the constant-current stress and then an eventual increase. In contrast to this, in the case of hot-electron stress, the threshold voltage increases monotonically with stress time. This difference in the behaviour can be explained as follows. During the constant-current stress, electrons are injected in the oxide from the drain region by the mechanism of Fowler-Nordheim tunnelling 9). Moreover, in the constant-current stress, there is a high electric field induced across the gate oxide. This leads to the generation of electron and hole pairs by 588 Philips Journalof Research Vol. 42 No. 5/6 1987

7 Generation of interface states during the electrical stressing of M OS transistors t 4 VD = 0.1 V VD = 5.0 V 10" 5 L:O--'''!:5:::-0---'2::-!5L,0''---=-3~50'''''''''-4,.150''' LO-''''65~O-''''7::-!50 - I(s) Fig. 5. Generated interface trap density t!. Di' versus stress duration t for values of VD = 0.1 and 5 V (constant-current stress). impact ionization in Si ). Thus, the electrons injected in the oxide can induce both positive and negative charges in the oxide. The positive charges are the holes that produce a negative shift in the threshold voltage. The neg- ID (A) t STRESS V D = 7V V G = 3.5V Time = 1 hr. Fig. 6. Subthreshold ID, VG characteristics for values of Vo=O.l, 1.0, an d 5V (hot-electron stress). Solid line-before applying the stress, dashed line-after applying the stress. Philips Journalof Research Vol. 42 No. 5/

8 A. Bhattacharyya and S.N. Shabde Vo'O.1 V o Vo=1 V.. Vo'5V STRESS: VD' 7V VG' 3.5V Dil X (cm-2 1 ev- I ) t 50 _ Hmin) Fig. 7. Generated interface trap density Dil versus stress duration t for values of VD = 0.1, 1.0 and 5 V (hot-electron stress). ative charges are the electrons that get trapped near the drain and produce a positive shift in threshold voltage. For the conventional hot-electron stress, the field across the oxide is not ~--'r--r--r "---r--,.----, ~-L~~~~~JL~;=~~~~=j40 o 200' t(s) gm versus stress du- Fig. 8. The shift in threshold voltage V T and maximum transconductance ration t for a constant-current stress of 10 na. 80 gm()lu) 70 t Philips Journalof Research Vol. 41 No. 5/6 1987

9 Generation of interface states during the electricalstressing of MOS transistors high enough for the hot electrons injected into the oxide to cause impact ionization. Consequently, during hot-electron stress we observe only positive shift in threshold voltage due to the trapping of the injected electrons in the gate oxide. From figs. 3 and 6 we note that after applying the constant-current or hotelectron stress, the subthreshold slope is dependent on VD' indicating a shortchannel effect 4.5). The electrons trapped in the gate oxide near the drain region effectively produce a short-channel transistor with a higher threshold voltage in series with the transistor constituted of the remainder of the channel in which the threshold voltage is unaffected. The difference between the subthreshold slopes for VD = 0.1 and 5 V, increases with stress duration, implying that the effect of the short-channel transistor also increases with stress duration. This occurs due to the fact that the short-channel transistor becomes more of a factor as the threshold voltage increases with stress duration. The two-transistor-model is discussed in detail in ref Conclusions We have monitored and calculated the generation of interface states during constant-current and hot-electron stress leading to device degradation. We observe a significant increase in the density of interface states as a function of stress duration for both type of stress. Thus in addition to electron trapping and hole trapping, producing fixed oxide charge, which are suggested as mechanisms for the threshold voltage shift, the generated interface states resulting in transconductance degradation should also be taken into account. In the case of constant-current stress, we find an initial positive charge buildup due to the hole trapping followed by negative charge buildup due to electron trapping; while in the case of hot-electron stress only electron trapping is observed. After applying the stress, we observe short-channel effects in the subthreshold characteristics due to electron trapping in the gate oxide in the gate to drain overlap region. Acknowledgements It is a pleasure to acknowledge B. Stacy and G. Simmans for encouragement. REFERENCES I) E. Harari, 2) I.C. Chen, J. Appl. Phys., 49, 2478 (1978). S.E. Holland, and C. Hu, IEEE J. Solid State Circuits, SC-20, 333 (1985). 3) A. B hattacharyya and S. N. Shabde, IEEE Trans. Electron Devices, ED-33, 1329 (1986). 4) S. M. Sze, 'Physics of Semiconductors Devices', 2nd Edition, John-Wiley and Sons New York, 1981, pp. 446, 470. Philips Journalof Research Vol. 42 No. 5/

10 A. Bhattacharyya and S.N. Shabde ') S.N. Shabde, A. Bhattacharyya, R.S. Kao, and R.S. Muller, 'Two Transistor Model for Hot-electron MOSFET Degradation', (submitted for publication to Solid State Electron.). 6) M.S. Liang and C. Hu, IEDM Technical Digest, 396 (1981). 7) A. Bhattacharyya, Solid State Electron., 27, 899 (1984). R) S.C. Sun and J.D. Plummer, IEEE Trans. Electron Devices, ED-27, 1497 (1980). 9) Z.A. Weinberg, Solid State Electron., 20,11 (1977). Ill) N. Klein and P. Solomon, Appl. Phys., (1976). Authors Anjan Bhattacharyya; B.Sc. (Honours Physics), Presidency College, University of Calcutta, India, 1972; B.A. (Honours Physics), Trinity College, University of Cambridge, England, 1976; M.S. (Physics), Ph. D. (Electrical Engineering), University of Illinois, Urbana- Champaign, U.S.A., 1979 and 1981; Philips Research Laboratories Sunnyvale, Signetics Corporation, U.S.A., His Ph.D. dissertation was titled 'Laser annealing of ion-implanted Silicon'. He has worked on EEPROM device physics and technology. His current research interests are in hot carrier effects and thin oxides for CMOS devices and in interpoly dielectrics in EPROM devices. He has published over 25 papers in refereed technical journals and presented 10 conference papers. He is a Senior Member of the IEEE (U.S.A.) and member of the American Physical Society and of the Electrochemical Society. Sunil N. Shabde; B.Sc., Nagpur University, India, 1959; B.E. (Electr. Comm. Eng.), Indian Institute of Science, India, 1962; M.S.E.E., Purdue University, Lafayette, Indiana, U.S.A., 1965; Ph.D. (E.E.), Rice University, Houston, Texas, U.S.A., 1967; Assistant Professor of Electrical Engineering, University of Michigan, U.S.A., ; Advanced Technology Development, Signetics Corporation, Sunnyvale, Since 1972 he has an extensive experience in the semiconductor industry in the area of process development of various MOS processes and also in the area of yield improvement/device engineering in manufacturing. His industrial experience also includes project and group management at companies such as Signetics, AMI and Fairchild. He is author or coauthor of 14 technical publications in the device physics area. Currently he is engaged in process development of the I urn CM OS process for high speed CMOS logic applications. 592 Philips Journalof Research Vol. 42 No. 5/6 1987