AVALANCHE-INJECTED CURRENT IN MNOS STRUCTURES

Transcription

1 Philips Res. Repts 26, , 1971 AVALANCHE-INJECTED CURRENT IN MNOS STRUCTURES Abstract 1. Introduetion by J. F. VERWEY The emission current through the dielectric due to electrons from an avalanching emitter-base junction of planar npn transistors was measured in a metal-nitride-oxide-silicon (MNOS) structure. The thicknesses of the nitride and of the oxide were each 0 1 urn. Trapping of the electrons occurred chiefly at the Si 3 N 4 -Si0 2 interface to a density of electrons per cm", The dimension of the trapping areain a direction perpendicular to the e-b junction has been derived. The behaviour of the steady-state value of the avalanche-injected current showed a deviation from the expected Poole-Frenkel mechanism. This was explained by a lateral diffusion of electrons in the oxide. Avalanche breakdown of the emitter-base junction of planar transistors causes the formation of recombination centres at the Si-Si02 interface 1.2). During the breakdown charge can also be trapped in the oxide. This effect has been studied in transistors with a field electrode (gate) on top of the oxide above the e-b junction. In these structures a current can be measured through the oxide during the breakdown of the e-b junction. A breakdown with a positive voltage on the gate gives a current of electrons through the oxide while negative charges 3), possibly electrons, are trapped in the oxide. Both phenomena, the charge trapping and the creation of interface states are homogeneous around the perimeter of the junction 4). It is possible to make an estimate 4) of the dimensions of the area where the interface states are created, in a direction perpendicular to the junction. This is not necessarily identical to the dimensions of the area where the charge is trapped because some lateral diffusion of charge in the oxide mayalso occur. This is illustrated in fig. 1. This figure shows schematically the situation during breakdown of the e-b junction with a positive voltage applied to the gate electrode. Av is the avalanche region. The arrows indicate the avalanche-injected electron current in the oxide. From fig. 1 it will be clear that the region where hot electrons bombard the interface and create interface states, and the region where the charge is trapped in the oxide need not be identical. This paper describes a method to determine the trapping area in the Si0 2 Part of the Si0 2 layer was replaced by a layer of silicon nitride Si 3 N 4 The current density J = I/A as a function of the field in the nitride is known 5.6). By measuring the current I through the insulating layer and assuming that the current is limited by the flow through the nitride layer one is able to calculate

2 AVALANCHE-INJECTED CURRENT IN MNOS STRUCTURES 383 the area A which takes part in the conduction of the electrons., The field in the nitride can be calculated from the gate voltage applied (sec. 2). A complication is the fact that a considerable amount of charge can be trapped at the Si 3 N 4 -Si0 2 interface, which fact is used in MNOS memory systems 7). However, the density of this charge can be determined experimentally and used in the calculation of the field. 2. Theoretical 2.1. Field in the nitride In this section a calculation is given first of the field in the nitride as a function of the voltage V gr applied to the gate during breakdown and the density Q- of the charge trapped at the Si 3 N 4 -Si0 2 interface. The model and some of the quantities used in the calculation are shown in fig. 2. The amount of trapping of charge in the insulator can be derived from the curves of the base current IH vs gate voltage Vg 3). This is shown schematically Q- Si0 2 éox dox,/;~i//;~~f// Fig.2. Fig. I. Fig. 1. Schematical representation of part of the cross-section of the emitter-base junction during avalanche breakdown with a positive voltage applied to the aluminium gate electrode. The arrows indicate the avalanche-injected electron current in the oxide. Av is the avalanche region. Fig. 2. Investigated double-layer structure with some of the quantities used in the calculation; Q- is the charge per cmê trapped at the Si 3 N 4 -Si0 2 interface, QSI is the charge per cm? in the silicon induced by the positive gate voltage, SN and Sox are the dielectric constants and d N and d ox are the thicknesses of the nitride and the oxide layers:respectively. Ie (A) t 10-9 I I :111,ti I 9 I I n I /, I---- /-~- _,I o V ge (1) V ge (2) -Vg. Fig. 3. Shift Lf Vge in the base-current plot, IB(V g ), after breakdown of the e-b junction under positive gate bias. The steep rise in the curve at V ge is due to the depletion of the base region below the gate. The drawn curve is before breakdown, the dashed curve after breakdown.

3 384 J.F. VERWEY in fig. 3. The steep rise iil'i B at positive gate voltages is due to depletion of the base region below the gate. Voe is defined as the gate voltage át which the base current reaches a value of 10-9 A (at V BE = 300 mv); V o l1) is before breakdown, Voe(2) is after breakdown. Generally where, Q- is the charge per unit area at the Si 3 N 4 -Si0 2 interface, QSI is the charge per unit area induced in the silicon and C N and Cl are the capacitances of the nitride and the total insulating layer, respectively. It is assumed that all the charge in the insulator is at the Si 3 N 4 -Si0 2 interface *) and that the workfunction differences and the voltage drop in the silicon may be neglected (the silicon is highly doped). For the shift of the curve in fig. 3 we arrive, assuming that Q- = 0 before breakdown, at One should note that zl Voe is measured with the e-b junction in forward condition. During breakdown' with the e-b junction reverse-biased the relation (3) similar to relation (1) holds: Vor = - Q- ICN - QsdCI> (3) where Vor is the gate voltage during dreakdown. Of course, the value of QSI is now different from that in relation (1). Combination of (3) and (2) gives : (1) (2) QSI = Cl ( - Vgr + Lt Voe)' Using Gauss' law the field in the nitride is given by EN = Q-IeN With eqs (2) and (4) this becomes Using the relation + QSdBN' LtVge Cl'. EN = (-Vor + LtVge). d N en 1Ic, = dnien + doxlbox, the field in the nitride then becomes Lt Vge en doxleox dn + Vgr E N =.. en doxleox + dn (4) (5) (6) (7) (8) 2.2. Conduction through the nitride. It is known that the conduction through the nitride takes place according *) This is justified in sec. 4.

4 AVALANCHE-INJECTED CURRENT IN MNOS STRUCTURES _-- to a Poole-Frenkel mechanism B). This means that the transport of electrons is determined by the field-assisted thermal emission from traps. The conductivity Ij can be written as a oc exp(-ujkt). (9) The activation energy consists of the trap depth cp minus a lowering IJcp by the field. In the case of a coulombic-potential-well model for the trapping centre L1cp can be written as 5.6) which gives for the current density J the following relation: CP - ({J EN)1/2)] J = een exp - kt. [ ( By plotting log J/EN vs EN 1/2 this should give a straight line. The constants in properly prepared nitride are 9) C = A/V cm, cp = 1 15 ev and (J = V cm. (10) (11) (12) 3. Experimental 3.1. Preparation of the samples The transistors investigated were obtained by the diffusion of boron and phosphorus into n-type silicon. The details of the preparation of the transistors have been described elsewhere 2). After the diffusion steps all the oxide was removed and a fresh layer of thermal oxide was grown with a thickness of 1000 A. Then a layer of nitride was grown from SiH 4 and NH 3 in H 2 as a carrier gas at 900 oe. The thickness was about 1000 A and the nitride covered the oxide completely. Then an aluminium metaiiization pattern was applied including a circular field electrode (gate) over the e-b junction Experimental results A breakdown of the e-b junction with a positive voltage applied to the gate causes the penetration of highly energetic electrons into the oxide. Many of these electrons are trapped and this results in a shift IJ Vge of the base-current plot (see fig. 3). The value of L1 Vge as a function of the time that a reverse current of 10-5 A has flown through the e-b junction is shown in fig. 4. It can be seen that for the gate voltages Vgr ~ 60 V the IJ Vge rapidly saturates as a function of time and attains a value of about 32 V. The current through the insulating layer was measured during the break-

5 386 J.F. VERWEY TOOr----r ,r r , V gr X80V.60V o 40V 1 TO _ t(s) TOO 1000 Fig. 4. Shift LIV ge of the base current as a function of time in three transistors of which the gate voltage Var during breakdown is indicated in the figure. down as a function of the time at several applied gate voltages Vgro The voltage V or was converted to the field in the nitride with eq. (8). The result is plotted in fig. 5 as Is/EN vs E N l/2. The slope of the theoretical curve from eq. (12) is also shown. The inset of the figure gives the definition of IS) the steady-state value of the avalanche-injected current Iav in the insulator. The decay of Iav is correlated with the trapping of charge in the insulator (see fig. 4). The temperature dependence of Is was also measured in the temperature range -65 oe to 125oe and a gate voltage of Vgr = 80 V (EN 1/2 = V1/2cm- 1/2 ). The result is plotted in fig. 6 as Is/ Vgr vs I/T. The straight line drawn through the measuring points corresponds to U = ev (eq. (9». 4. Discussion During avalanche breakdown ofthe emitter-basejunction an electron current is'flowing through the oxide and many electrons are trapped at the Si 3 N 4 -Si0 2 interface. In sec. 2.1 we made the essential assumption that all the charge was located at this interface and that the charge trapped elsewhere in the oxide could be ignored for the calculations. This is true because the amount of charge trapped, as derived from LIV ge in fig. 4 and eq. (2), is much larger than in cases where no nitride is present 2). The current through the insulating double layer is limited by the carrier transport through the nitride layer. This is because the steady-state value Is of the avalanche-injected current in identical transistors (but without nitride) at the same Eox was much higher than in the transistors described in this paper. This can be seen in fig. 7 which shows the results of the Is vs Eox in a transistor without nitride. More details about the avalanche-injected currents will be published elsewhere 10). The Is was about A at a relatively Iow field of Eox = V cm- l while the I.. in the MNOS structures reached A only at the highest value of Vgr in fig. 5, which corresponded to Eox = V cm-i.

6 AVALANCHE-INJECTED CURRENT IN MNOS STRUCTURES Vgr(V) I I i i I i A lav I ~ %- f 1O- 20LII--I------'-_---'---o.c---I '20 2' E]:2 (V I / 2 crii l / 2 ) Fig. 5. Variation of the steady-state value Is of the avalanche-injected current through the insulating layer as a function of the field EN in the nitride, plotted as Is/EN vs EN 1/2 Curve B is the slope of a Poole-Frenkel plot with the constant {3 (eq. (12)) taken from the literature 9). The inset shows the general behaviour of the avalanche-injected current as a function of time, to is the time at which a constant breakdown current was applied to the junction ' Is I1,r (~ ) Î 70-'3[- 7O"' L..!_..!_ -'-- '-- -l 3 5 J ~'5 ~ O _(WIJ_ T Fig. 6. Variation of Is with temperature measured in one transistor with gate voltage Vqr = 80V.

7 388 J.F. VERWEY 10-9r-----~------, 10 Is (A) L(IJ) t t ( I '. 1-5 I I,L:-----="=----:, , Eox (Vcm-? Fig. 7. Is is the steady-state avalanche-injected current as a function of the field Eox in a structure without nitride (d ox = 0 30 [J.m). The other curve is L (see fig. 8) as a function of Eox in the MNOS structures, calculated from the difference in curves A and B in fig. 5. From the temperature dependence of Is the U in eq. (9) was calculated. A value of U = ev was found. The gate voltage during these measurements was 80 V which gives with eq. (8) EN 1/2 = V1/2 cm-1/2. With the aid of eq. (12) and the experimental value 9) of fj = V cm we derive for the trap depth 4> in the nitride 4> = 1 03 ev. From the work of Frohman- Bentchkowsky 9) follows 4> = 1 15 ev and so a reasonable agreement with this value is obtained. The value found further justifies the assumptions made for the calculation of the field in the nitride (sec. 2.1). The temperature dependence of the current through the double layer gives a possibility to calculate the dimensions ofthe area A were the charge is trapped. We rewrite (12) as and since Is = A J, the area A is given by J = een exp(-u/kt), (13) Is A= een exp(-ujkt) For V gt = 80 V the value of Is/EN = A cm V-I (fig. 5). Substituting the value of U determined and the value of C from the literature 9) (see sec. 2.2) we calculate A = cm". The perimeter of the e-b junction was cm, therefore the dimension L of the trapping area in a direction perpendicular to the junction is L = 0 55 (lm for this gate voltage of V gt = 80 V. In this way we are able to construct a more detailed physical model for the trapping and this is given in fig. 8. One may see that a relatively large amount oflateral diffusion ofthe avalanche-injected charge carriers takes place (fig. 8 is drawn on scale). One should..note that the value of L contains.an uncertainty because. the, value of C in eq. (14) has been taken from the literature. Generally the constant (14)

8 r~ i t ~- t S & N, t t; '.:-:..:== =_-:_-_-_-_-_-:.:.= == == =:' AVALANCHE-INJECTED CURRENT IN MNOS STRUCTURES Emitter n-si Fig. 8. Schematical model for the avalanche-injected electron (e-) current through the MNOS structure. L is the dimension of the trapping area in a direction perpendicular to the e-b junction, Av is the avalanche region. C may vary considerably due to variations in the processing S). The value of C given in sec. 2.2 is for analogous nitride as in the transistors investigated. The variation of the avalanche-injected current with the field has been given in a Poole-Frenkel plot (fig. 5). The measuring points lie on a straight line but the slope of this line differs to some extent from the slope calculated (with (J = V cm)...' This difference occurs because the lateral diffusion in 'the oxide is a function of the applied voltage V gr This can be seen in the following way. The number of electrons which penetrates the oxide is a function of the field in the oxide. When the number of electrons increases due to a higher field'e ox then it is possible that a larger area A must be used to transport the electrons through the nitride. This means that A and thus L are functions of V gr According to this model L can be calculated from the difference between the two lines in fig. 5 according to (15) where I p _ F is the current which corresponds to curve B in fig. 5 and 0 55 is the value of Lat V gr = 80 V. The result of this calculation is plotted in fig. 7 as a function of the field in the oxide. One may see that L follows about the same dependence as the dependence of the number of avalanche-injected electrons in the oxide in analogous transistors with oxide only. Summarizing the results, at higher gate voltages the conduction through the nitride increases, but a larger area of the nitride also takes part in the conduction process. 5. Conclusions. Breakdown of the emitter-base junction of planar transistors with a positive voltage applied to the gate electrode on the Si 3 N 4 -Si0 2 insulating layer gives rise to a current through this layer. This is very probably a current of electrons'

9 390 J.F. VERWEY which are injected into the Si0 2 from the avalanche plasma in the silicon. These electrons are able to cross a relatively thick Si0 2 layer of 0 1 (J.mand many of them are trapped at the Si 3 N 4 -Si0 2 interface. The trapped-charge density can be as high as el. charges per cm", Due to the trapping the avalanche-injected current decreases to a steady-state value Is. The variation of Is with temperature, with the assumption that the current is limited by the conduction through the Si 3 N 4 layer, offers a possibility of calculating the dimensions of the trapping area. The dimension in a direction perpendicular to the e-b junction was 0 55 (J.mfor a gate voltage of 80 V. The variation of Is with the field in the nitride layer (0 1 (J.m) showed a deviation from the expected Poole-Frenkel mechanism which was explained by a lateral diffusion of charge carriers. This gives a trapping area dependent on the gate voltage applied. Acknowledgement The author thanks J. H. Aalberts and J. J. H. Schatorjé for the preparation of the transistors and B. J. de Maagt for the measurements. Eindhoven, May 1971 REFERENCES 1) B. McDonald, I.E.E.E. Trans. Electron Devices ED-I7, 871, ) Jó F. Verwey, Mier, EI. Reliability 9, 425, ) J. F. Verwey, Appl. Phys. Letters 15, 270, ) J. F. Verwey, to be published in Solid State Electron. S) G. A. Brown, W. C. Robinette and H. G. Carlson, J. electrochem. Soc. lis, 948, ) S. M. Sze, J. appl. Phys. 38, 295, ') D. Frohman-Bentchkowsky and M. LenzIinger, J. appl. Phys. 40, 3307, ) J. Frenkel, Phys. Rev. 54, 647, ) D. Frohman-Bentchkowsky, Proc. I.E.E.E. 58, 1207, ) J. F. Verwey and B. J. de Maagt, to be published.,,