CAPACITIVE ADIABATIC LOGIC: A NEW PARADIGM FOR LOW-POWER COMMUTATION. Microenergy, Gubbio, Italy Gaël Pillonnet July 2017

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1 CAPACITIVE ADIABATIC LOGIC: A NEW PARADIGM FOR LOW-POWER COMMUTATION Microenergy, Gubbio, Italy Gaël Pillonnet July 2017

2 ENERGY DISSIPATION IN DIGITAL ELECTRONICS CIRCUITS Power density issue CMOS-based digital circuit in nano-scaled technology consume <1kW/cm 2 * 10x higher than air cooling dissipation capability recent technologies offer billions of transistors but cannot be used at the same time! Energy issue Comparing to Landauer limits (3zJ@300k), one logic operation in deep CMOS technology node costs x10 5 more Why do we need to dissipate high amount of energy to code one logic state in current digital circuit using CMOS technology? * considering buffer gate on 10-2 µm 2 with 0.1fF gate capacitance operating at 1GHz ** considering 1 zetta flops and 50W 2

3 CMOS BASED LOGIC ROOT LIMITATION #1 Go back to the energy transfer basic in a elementary inverter logic gate V DC V DC V DC R OFF i R R ON Hyp: R ON C G R OFF ->+oo V CC 0 C G NOT gate U C U pulse ;U C V CC Energy provided by energy source to code one logic bit: E VDC = T OPUDC 2 xi DC = C G V CC t=0 NB: R ON value has not effect 0 I R T OP V CC /R ON 0.5xC G xv DC 2 0.5xC G xv DC 2 large current peak = too fast transition = irreversible transform = inescapable loss Classical digital circuits suffer from inherent dynamic loss (not device dependent) due to sharp transition between two logic states 3

4 CMOS BASED LOGIC ROOT LIMITATION #1 Is it really a serious problem? Quantify this inherent loss in the last node CMOS technology: {V CC ;C G* }={1V;0.1fF} E OP =0.1fJ >> 3zJ given by Landauer limit: k B.T.ln(2) Yes! we are x10 5 far from the minimal energy to code one bit! Does the CMOS scaling help? Move to the next lower node: C G /2 & V CC ~cst E OP /2 per node Does the subthreshold operation help? V CC ~0.3V E OP /10 and higher leakage (see later) Scaling or subthreshold cannot fill the huge gap * best case: interconnections cap is assumed equal to zero 4

5 WHAT S NEXT? The huge energy gap to fill needs a hardware revolution! Fortunately, the adiabatic technique has been introduced to avoid a hardware revolution V DC V PC Basic idea: only replace a DC-power supply V DC by a trapezoidal power-clock V PC 5

6 ADIABATIC ENERGY GAIN AND LIMITATION WITH FET Go back to the energy transfer basic, but with soft charging V PC U PC ~U C V CC Hyp: R OFF ->+oo V DC 0 R ON C G U C 0 I R T RAMP T OP V CC /R ~V CC /R x RC/T Energy go back to the voltage source E VPC = T OPUPC xi PC R ONC G C T G V CC RAMP t= V TH + C G V TH 2 C T RAMP R ON C G V TH G Controlled inherent dynamic loss in adiabatic Uncontrolled inherent dynamic loss due to the FET behavior 6

7 ADIABATIC ENERGY ROOT LIMITATION #1 It it really a serious problem? Quantify this uncontrolled loss in the last node CMOS technology: {V CC ;C G }={1V;0.1fF} {R ON ;T RAMP }={1kΩ,10ps} V TH =0.3V E OP =0.01fJ >> 3zJ Yes! we are 10 4 higher than the Landauer limit Why not reduced V TH? Because we are face to a hardware limitation E VPC R ONC G C T G V 2 2 CC V TH + C G V 2 TH + I OFF V CC T RAMP RAMP dynamic loss f V TH static loss f 1 V TH An inherent trade-off for any semiconductor device between its cut-off and on-state strength exits 7

8 WHAT S NEXT? Adiabatic technique is efficient but not using FET devices. We need a hardware revolution! Fortunately, the mechanical device has been (re)introduced* V PC V PC Basic idea: Use metal contact (or no contact) to have not I ON over I OFF compromise * in combination with adiabatic technique 8

9 HOW TO FABRICATE RELAYS? G V PC D S chassis ground slide link g l G k electrical isolation spring S e y D e x vertical motion g DS dy OFF position Simplified mechanical scheme G D C GS R OFF /R ON S Equivalent electrical model µ-relay fabricated * M. Spencer, Demonstration of Integrated Micro-ElectroMechanical Relay Circuits for VLSI Applications, JSSCC,

10 ENERGY DISSIPATION USING MEMS RELAYS E VPC = T OPUPC xi PC R ONC G C T G V CC RAMP t= V PO + C G V PO 2 C G V T RAMP R ON C PO G Controlled inherent dynamic loss in adiabatic Still uncontrolled inherent dynamic loss in adiabatic based on relay Quantify for nano-scale relay: {U PI ;U PO }={10mV;1mV} {V CC ;C G }={1V;100pF} {R ON ;T RAMP }={10kΩ,100µs} E OP =0.1fJ No, we are still 10 4 higher than the Landauer limit with x10 10 operating period and x10 6 size compared to MOS + technological limitation: mechanical reliability due to the bad electrical contact and chocks 10

11 WHAT S NEXT? Go back to our old MOS transistors or try another revolution to save energy? OR Fortunately, the capacitive adiabatic logic is introduced! [1] V PC V PC ON OFF Basic idea: use relay but in (electrical) contactless operation and adiabatic operation always OFF operation [1] G. Pillonnet, S. Houri and H. Fanet, Adiabatic Capacitive Logic: a paradigm for low-power logic, IEEE ISCAS,

12 HOW TO USE CONTACTLESS RELAYS? Relays become variable capacitors in CAL paradigm Buffer example V PC V PC OFF low 0 logic input 1 logic input V o = V PC ON R ON R OFF + R ON V PC ~0 ON OFF V o = high C L C H + C L V PC ~0 V PC high low Trade resistive divider for capacitive one V o = R OFF R OFF + R ON V PC ~V PC V o = C H C L + C H V PC ~V PC 12

13 WHO IS THE ELEMENTARY DEVICES IN CAL? Positive- and negative- variable capacitors (VC) are the elementary hardware device in CAL C DS MOS relay VC P-CV C(V) curve C H G B D U DS C L S U GB P-MOS P-CV N-MOS N-CV Analogy to transistor-, relay-based logic N-CV C(V) curve C H C DS C L U GB 13

14 HOW TO IMPLEMENT VC DEVICES How to change a capacitor value? C DS = ε 0 ε r w l g By changing surface (wxl), gap between plates (g) or permittivity (ε r ) l S D w g C DS changes by an isolated voltage U GB it is a four terminals device G B U DS D S Actuation could be : Thermal not very reversible Piezoelectric trade off between leakage and dynamic losses Electrodynamic current actuation Electrostatic small gap needed to have reasonable supply voltage 14

15 spring isolation PROPOSED HARDWARE SOLUTION* Well known MEMS topology ( excepted isolation) Electrostatic actuation using comb drive in both sides Purely contact-less (electrical & mechanical) Input electrodes Output electrodes G B D S * This is not the only hardware solution to implement a 4-terminal variable cap 15

16 DISPLACEMENT AGAINST INPUT VOLTAGE low position high position (V GB >0) G B S D G B S D isolation Simulation from Coventor, MEMS+ 16

17 15µm displacement ELECTROMECHANICAL CHARACTERISTICS The MEMS sizing is given by cascability logic constraints (see later) Displacement against input voltage Capacitance vs input voltage C DS C DS x3 C G D G B S C G C DS 2 caps mechanically coupled Simulation from Coventor, MEMS+ for 1mm 2 device (2µm gap) dv ( t) dc( x) dx i( t) C( x) V dt dx dt electrical part mechanical part 17

18 BUFFER BEHAVIOR: STEP BY STEP V PC1 V PC2 V PC3 V PC4 Buffer pipeline V out1 V out2 =V in3 V out3 PCs have a π/2 phase shift Waiting Evaluation Holding Recovery V in3 V PC3 PC3 wait the input C out3,high x 3 αc out3 C out3,low E mechanic V out3 C out3,h /(C out3,h +C in4 )xv PC3 i PC3 PC3 also recovers energy to VC 18

19 BUFFER BEHAVIOR: ENERGY TRANSFER [in green] loss controlled by the ramping time T E loss elec. energy from/to PC i loss from power supply resistive loss α I i 2 spring energy 1/2kx 2 loss inside material elec. energy from/to PC i-1 energy in the variable capacitor VC i elec. cap energy 1/2C in V in2 +1/2C out V out 2 loss from power supply* resistive loss α I i-1 2 viscosity loss α dx i /dt kinetic energy: 1/2mdx/dt 2 chock loss contactless * Power supply must be reversible and AC (literature has already proved high efficiency power supplies) 19

20 (OUR) "ADIABATIC LOSS DEFINITION E EL Energy, fj E C E D E M E LOSS Definition: loss scaling linearly with the ramping time Need low dissipation? Reduce the speed! 1 E KIN 0, Tf Here, our MEMS moving is always controlled by the power clock ramping time Gap closing MEMS is not suitable as motion is not controlled after the pull-in CONFIDENTIEL CEA Journée Annuelle Carnot 12janv

21 ENERGY ANALYSIS OF ELEMENTARY MOVING 1/T=100Hz Power clocks currents currents displacement E OP,min =1,2pJ pour 1mm 2 (vs 1fJ for nano-scale transistor) thanks to the controlled moving and energy back Electrical simulation using simplified model (VHDL-AMS) 21

22 LOGIC PROPAGATION THROUGH PIPELINE The biggest issue: find the right MEMS configuration (cap variation, C in vs C out ) to propagate the logic state gate by gate V in V PC1 V out1 V PC2 V out2 V PC3 V out3 V PC4 V out4 30V 12V 8V V PC V out gnd gnd gnd gnd 1 0 Cascability condition V PC1 V PC2 V PC3 V PC4 = have different voltage levels Occurred when 30V < V PC < 37V V out1 V out2 =V in3 V out3 22

23 LOGIC OPERATION: OR EXAMPLE V PC V in,1 V in,2 to the next gate All combination logic operation is possible with CVP and/or CVN devices 23

24 ROADMAP FOR DEEPER INTEGRATION Based on the current (first draft) MEMS Gap 1/k Linear sizes 1/k Mass 1/k 3 Spring constant Frequency Capacitance 1/k Actuation voltage 1/k E LOSS 1/k 3 k k E OP [J] S si [µm 2 ] F op [MHz] 1p 2µm 1f Landauer limit 2µm 200nm 200nm CMOS limit 1a 1z 20nm 20nm 2nm CMOS limit 10-2 CMOS limit (1000) 0,1 2µm 1 200nm 10 20nm 2nm 100 2nm Energy gain x10 5 techno. node Surface penality x10 4 techno. node Speed penality x10 techno. node Targeted application: low processing rate with high energy constraint (e.g. autonomous environmental sensors) 24

25 THANKS TO THE TEAM Hervé Fanet Gaël Pillonnet Louis Hutin Bruno Reig Full time researchers in Léti (Grenoble, France) Gregory Snider Prof. Univ. of Notre Dame Samer Houri Delft Tech.Univ. Ayrat Galisultanov post doc. Yann Perrin post doc. External partners Post PhD 25

26 CONCLUSION Actual CMOS logic is an energy heresy for logic operation The root of the problem is the elementary gate behavior New device / design style at the gate level has to be invented! Adiabatic design style is promising but we need a dedicated device, not FET variable capacitor (VR) seems to be adiabatic compatible This is preliminary results waiting the silicon device measurements Contact-less variable capacitors could be based on: well-known MEMS structures with already proved scalability and reliability abilities Other (reversible) actuation: to be defined! Beware: every solution has to be cascadable (propagate logic state to the next stage) It is not a crazy alternative to reduce the energy dissipation Open question: where is the energy limit using the proposed MEMS? Your feedbacks are more than welcome! 26

27 CAPACITIVE ADIABATIC LOGIC: A NEW PARADIGM FOR LOW-POWER COMMUTATION Microenergy, Gubbio, Italy Gaël Pillonnet July 2017