for Leading Edge CMOS and SiGe Technologies

Transcription

1 1 Reliability IBM Challenges Systems and Technology and Qualification Group - SRDC Methodology for Leading Edge CMOS and SiGe Technologies Fernando Guarín Ph.D IEEE Fellow Semiconductor Research & Development Center IBM Systems and Technology Group 2070 Route 52, Hopewell Junction, NY guarinf@us.ibm.com 2002 IBM Corporation

2 Overview IBM Systems and Technology Group - SRDC New Materials, Scaling and the Challenges they drive in the Reliability Qualification of leading edge technologies (FEOL) Reliability Mechanisms CMOS SiGe Reliability overview Qualification Methodology Conclusions 2

3 IBM has led the way in the introduction and qualification of new materials and technology elements C4 in 1960 s SiGe SOI Copper Interconnect / Low K Metal Gates High - κ Ge Channel High K Stress/strain edram efuse 3 Box Si Platform

4 The End of Traditional CMOS Scaling Voltage, V / α n+ source tox/α GATE WIRING n+ drain W/α L/α p substrate, doping α*na xd/α 11Å SCALING: Voltage: V/α Oxide: t ox /α Wire width: W/α Gate width: L/α Diffusion: x d /α Substrate: α N A R. H. Dennard et al., IEEE J. Solid State Circuits, (1974). RESULTS: Higher Density: ~α 2 Higher Speed: ~α Power/ckt: ~1/α 2 Power Density: ~Constant Approaching atomistic & quantum-mechanical boundaries Reliability Implications 4

5 High-Field Effects Limit CMOS Scaling Ideally, scaling is to be done at constant field In practice, scaling has been achieved by increasing electric fields Reliability Exposure High gate oxide field large gate tunneling current Solution: High-k gate insulator Solutions introduce new reliability challenges High-k PBTI 5

6 core gate oxide physical thickness (nm) technology node (nm) Limitations of Classical Scaling We have entered the regime of non-statistical material and device behaviors RELIABILITY IMPLICATIONS Oxide thickness is now measured in terms of atomic layers. Atomic level fluctuations have dramatic consequences SiO2 Oxynitride has impact on NBTI Dopant concentration fluctuations on the atomic scale are now meaningful Devices dimensions are so small as to preclude the use of statistics 6

7 Gate Oxide Scaling 5 Atoms Thick! Oxide Thickness (Å) nm A. Chou/M. Chudzik SiON 28 nm CMOS1S CMOS2S CMOS3S CMOS4S CMOS5S CMOS6S CMOS7S CMOS8S CMOS9S CMOS9S2 CMOS10S CMOS11S CMOS11S2 CMOS12S Reliability Impacts: TDDB, BTI, Hot Carriers 7

8 Trends in Minimum Feature / Wavelength Wmin/Wavelength 1000% 100% 10% Resolution = λ k1 NA where NA θ = nsin Year 10,000 1, # Atoms Controlling min device VT Tolerances of 8 atoms and 8% of light wavelength! Tim Brunner, Dave Frank IBM Research 8

9 Bias Temperature Instability NBTI - PBTI 9

10 What is NBTI? pfet degradation mechanism resulting in positive charge buildup oxide bulk charge and donor type interface states at the SiO2/Si interface under the influence of applied negative gate voltage Damage is related to cold holes no drain bias needed. Vg < 0 V Gate Oxide holes NBTI damage is Not associated with channel carrier transport Source Vs=Vd=Vnw = 0 V Inverted Channel Drain Not related to tunneling gate current in thin oxides Mechanism typically investigated in a capacitor configuration with channel inverted (symmetric damage) First reported by Deal in [B. Deal et al., J. Electrochem. Soc., 114, 266 (1967).] Not many papers on this subject until 1997 IRPS paper on 130nm [LaRosa,Rauch,Guarin.. ] 10

11 NBTI (Negative Bias Temperature Instability) is the degradation mechanism observed in PFET s when the devices are operated with negative gate bias at elevated temperature Negative Bias: Gate is negative to Source, Drain & Bulk. Temperature: NBTI is enhanced by high temperature Instability: Device parameters (V t, Gm, I d,sat, I d,lin, etc.) shift with stress time fresh device after NBT stress V g,stress = -2.5V T = 125 o C Id (A) Vd (V) 11

12 NBTI-Induced Vt Shifts at various Temperatures Temperature and Vg significantly influence the level of V t shift 12

13 NBTI Degradation Model Mean Shift Typical NBTI Models: VGS H 1. VT = A exp t TOX kt m n Power Law VGS H 2. VT = Aexp a exp t TOX kt n Exponential Law These equations describe the average or mean shift observed. Often A is higher for narrow PFETs, such as in an SRAM cell. Typical values: m ~ 3-4, H ~ ev, n ~

14 NBTI Implications NBTI s increased relevance due to: Can not be reduced by increasing Channel Length as in Hot Carrier Gate electric field has increased as a result of transistor scaling. Increased Nitrogen levels added into gate oxide. Chip operating temperature has increased. Surface p-channel MOSFETs has replaced buried p-channel MOSFETs. Schroder JAP Kimizuka et al, 2000

15 NBTI Recovery (Measurement Implications) NBTI measurement results are sensitive to the measurement time, due to the recovery during the measurement. Relaxation occurs during the measurement delay Power law time-dependence factor is affected 100 V stress = -2.6V V relax = 0V T = 125 o C V t (mv) 10 Delay 1 ms 1 s 8 s n = Recovery effect after releasing NBTI stress t eff (s) ΔVt recovery due to measurement delay. 15

16 NBTI Recovery 2 Components: -Hole trapping and detrapping (Recoverable) -Interface state trap creation (Permanent) G. La Rosa et al., IRPS 06, pp Huard et al 2007 IEDM 16

17 Charge Trapping in High-K Metal Gate n FET Interface Layer Defects Increase in V TH (mv) High-K Metal Gate Voltage of Operation = 1.7V e - e - e - e - e - e - e - e - Si Time of Operation (sec) HfO 2 contains pre-existing Defects (or traps) Electron injection from Si in nfets in On-State Traps trap electrons Trapped charge causes Threshold Voltage (V TH ) (Need V TH to be low) Performance Known as Positive Bias Temperature Instability (PBTI) or Charge Trapping Did not exist in SiON based technologies RELIABILITY IMPLICATIONS 17

18 Channel Hot Carriers 18

19 Channel Hot Carriers Channel carriers whose temperature (T hc ) is locally (near drain) larger than the lattice temperature. T hc is mainly determined by: Large lateral Electric Field in the pinch-off region. Energy exchange processes (e.g., phonon scattering, impact ionization, e-e scattering, etc.)» SLOWER CIRCUIT OPERATION 19

20 PFET HC Behavior Older Technology 3.3V Device: L eff =0.26 µm, t OX = 6.8 nm, Vdstr = -5.0 V Electron Trapping (log t) Hole Injection t n (n 0.5) Hole Injection and electron trapping of roughly equal strength. Note impact of VG stress + 20 t, sec

21 PFET HC Behavior (65nm technology) 1.2 V Device: L eff =0.07 µm, t OX = 1.6 nm, Vdstr = -1.9 V Hole Injection t n, n 0.25 Hole Injection completely dominant t, sec

22 PFET Hot Carrier Behavior Hi-K Technology 1.0V Device: 28nm PFET: L=30 nm, V DS = -1.7 V Weak ET (log t) & ISG (n ~ 0.5) Self Heating-NBTI n ~

23 PFET Hot Carrier Mechanism Evolution With scaling, PFET hot carrier has evolved: From - Strong electron trapping over the low to mid Vg range, and interface state generation at the higher Vg range To - Weak electron trapping at the low Vg range, weak interface state generation at mid Vg, and a dominant high Vg mechanism. This high Vg mechanism has these characteristics: 1. Time slope n ~ (with slow measurements) 2. More dependent on V GS than V DS 3. Positively thermally activated 23

24 E-E SCATTERING PHENOMENA In very short channel devices electrons can gain the supply energy qvds by travelling in the pinchoff region quasi balistically. E-E scattering There is a small probability that two high energy electrons undergo a scattering process so that one electron gains most of the total energy leading to a small electron population of carriers up to about twice qvds qvds 2qVds Scattering rate is proportional to n 2 or I s 2 EE scattering event 24

25 Validation of PFET Results (Data Points), and Predictions (Lines) (pure NBTI added to each quasi-static calculation) Data: EDHC (Mid-Vg) LSHAN (Hi-Vg) Courtesy S. Rauch 25

26 Universal Energy Driven Hot Carrier Mid Vg > 900 Devices V DS = V 6 Device Types Various L DES, V GS ( Mid Vg ) DR / I D 2, AU V EFF, V The Damage Rate, DR, follows a universal curve: DR(V EFF ) I D 2 S IT (q m EE V EFF ) irrespective of scaling, proving that the available energy, not electric field, is driving the damage rate. [S. Rauch] 26

27 Universal Energy Driven Hot Carrier PFET Mid Vg DR / I D 2, AU Note increased data scatter over NFET. E = 1.8qV EFF, ev PFET Mid Vg HC follows the same universal curve. [37] 27

28 Universal Energy Driven Hot Carrier SOI Model fit for SOI 28

29 Universal Energy Driven Hot Carrier Hi-K DR / I D 2, AU V EFF, V 29

30 Ring Oscillator Delay vs # 30 C Delay, A.U. At room temperature for a high # cycles NFET is dominant. but PFET contribution H.C + NBTI is not negligible # of Cycles 30

31 Ring Oscillator Delay vs # 125 C Delay, A.U. At high temperature for # cycles < 4x10 14 NBTI contribution from PFET is clearly dominant. # of Cycles 31

32 SiGe Reliability 32

33 SiGe HBT Performance Increases ft (GHz) E-04 1.E-03 1.E-02 I C (A) Scaling for increased performance SiGe HBT continues to increase performance through scaling Focus on optimizing device for performance and reliability providing insight into reliability scaling 33

34 Scaling: vertical and lateral concentration Increase Ge slope Narrow base Increase Coll ft Reduce transit time Kirk effect to higher current depth current density Reduce transit time, increase f T Kirk-effect extended to higher current density Vertical scaling with lateral scaling maintains constant current / device length for self-heating and current delivery Emitter shrink with increasing current density 34

35 Along with the SiGe HBT performance across several generations Current Density Jc increases 250 VCB = 1V IBM 8HP 5HP 6HP 7HP 8HP Litho [µm] Cutoff Frequency (GHz) IBM 7HP 50 IBM 5HP, 6HP 0 1E-4 1E-3 1E-2 Ic (A) f T [GHz] f max [GHz] * 285 Beta BV CEO [V] BV CBO [V] J T,peak [ma/µm 2 ] ~1.5 ~1.5 ~5.8 ~10 BEOL Al Al Al Cu 35

36 Pre and post stress Gummel plots InGaP HBT SiGe HBT β degrades mostly due to increase in base current for HBTs 36

37 Typical Degradation Evolution AlGaAs and InGaP InGaP/GaAs HBT Provides a significant reliability improvement over AlGaAs/GaAs HBT Ref. Livingston JPL Publication

38 Results for SiGe 8HP (130nm) SiGe 8HP exhibited negligible Beta degradation after 14,000 Hours of stress 38

39 Comparison of Mechanisms for III-V vs SiGe HBTs Stressed at highly accelerated J SiGe 2550 ka/cm 2, 27.8 hours InGaP 150 ka/cm 2, 20 hours 1.E-01 Ic, Ib [A] 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 T=140C Ic Ib 1.E-07 Before stress 1.E-08 After stress 1.E Vbe [V] SiGe stressed at 17X J InGaP No evidence of recombination enhanced degradation induced fails in SiGe 39

40 Degradation Evolution SiGe Typical patterns with A E =0.2x6.4µm 2, J C =25.5mA/µm 2 Gummel Plots Shifts vs stress time 1.E Ic, Ib [A] 1.E-02 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 1.E-08 T=140C Ic Ib Before stress After stress Ib, Ic, Gain % Change Vbe=0.7V Ic Ib β 1.E Vbe [V] E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 Stress Time [sec] Ic: increase for Vbe > 0.65V Ib: increase for entire Vbe range Ic: gradual increase Ib: increase followed by recovery 40

41 Packaged Devices Level Stress Results Fwd. Bias Modules stressed up to: 2900 POH at 140 C 800 POH at 225 C Gain change [%] Gain change [%] Tamb=140C (Tj=148C) Tamb=170C (Tj=180C) Dashed line is the Projected degradation from wafer level stress Good agreement with wafer-level stress β < 10% for any case No catastrophic failure observed Gain change [%] Gain change [%] Tamb=200C (Tj=210C) Tamb=225C (Tj=235C) Stress time [hr] 41

42 Junction Temperature Substantial increase of T J at elevated current levels Both thermal and electrical stress in effect Thermal Resistace [K/W] We=0.2um Measurement Model Junction Temperature [C] x0.64um2 0.2x1.28um2 0.2x2.56um2 0.2x6.4um2 1x 2x 3x 4x Emitter Length [um] Stress Current Levels R TH of SiGe HBTs T J for the stress conditions 42

43 Comparison of Thermal Characteristics III-V vs SiGe Thermal conductivity Self-heating Material K [W/cmK] Si 1.48 GaAs 0.45 InP 0.74 InGaAs* 0.05 Temperature Rise (C) InP HBT SiGe HBT All at 300K * Lattice matched to InP ft (GHz) InP Ref: S. Thomas III, IEEE Trans. On Device and Materials Reliability, vol. 1, no. 4, 2001, pp

44 Implications of self heating on Electromigration Temperature Rise (C) InP HBT SiGe HBT Electromigration limit Jmax scaling factor O SiGe O InP T [C] ft (GHz) for 175GHz operation Projections for T ambient = 85 C, HBTs running at f T = 175 GHz assuming T interconnect = T J (device junction temperature) Similar electromigration activation energies have been reported for Cu and Au E A = 0.85eV ref. Au: Ohta et al. Proceedings of 24 th International Symposium for Testing and Failure Analysis, pp (1998) Cu: Hu et al. Thin Solid Films, pp (1997) 44

45 Reliability Qualification Methodology Challenges and Future Technology Path 45

46 Qualification: Reliability Management Technology Qualification must cover all reliability mechanisms removing systematic and managing random defects Technology leadership: Reliability is a critical part of Technology development F a i l u r e Infant Mortality Useful Life Wearout R a t e Use Hours 46

47 Qualification & Sustaining Quality Wearout control focus...defect control focus TECHNOLOGY DEVELOPMENT PRODUCT REV. TO RELEASE TO MFG LAUNCH STABLE THROUGH MFG Qual. Activities Technology Feasibility (TO) Technology Evaluation (T1) Product Qualification (T2) - Reliability - Functionality - Application - Manufacturability Supplemental Qualifications - Process EC's - Additional Fabs (LQ) Early Product Evaluation (EPE) Tech Mfg Readiness (TMR) Qualification Complete Product Quality Levels P P Level assigned to first pre-t1 lot and any RTAT Processed that skips QA Checks/screens PQ Q 47

48 IBM s Reliability Management Strategy Reliability level is driven by: Level of defects introduced during the manufacturing process Effectiveness of reliability screens for the removal of defective components Wearout failure can be avoided by: Careful technology development and product design Effective process monitors during production. Reliability mechanism models developed and verified during technology qualification Field failure rates should be driven only by random defects 48

49 Reliability Mechanism Models Developed During Technology Qualification Phase Model device shifts as a function of device parameters (L poly, V T, t OX, etc.) and environment (V DD, T J ) Model circuit sensitivity (performance shift vs. device shift.) Model product performance before and after degradations, taking into account testing strategy. All device shifts must be considered together (BTI + HC.) Strive to generate physics based models A robust strategy for model validation must be in place Wafer In-line characterization of reliability during production phase ( hot carriers Vbd, BTI, etc.) 49

50 IBM Semiconductor Technology Qualification Approach Technology Stages T0 - Technology Feasibility Develop reliability models, evaluate new features, define reliability test structures Accelerated tests for potential wear-out mechanisms T1 - Process Qualification Assess manufacturability and reliability Define device models consistent with manufacturing tolerances Identify and mitigate systematic defect mechanisms Assure that wear-out is beyond intended End of Life Stress representative parts manufactured in the new technology Verify design ground rules, models, and basic design building blocks Manufacturing Process Qualification Readiness Verify that manufacturing facility is ready for product volume ramp-up of technology. Ensure that all documents, calibration, process controls, test specs, and proper procedures are checked and verified T2 Product Qualification (customer/design specific) 50

51 7HP SiGe Failure Rate De-rating vs Temperature Driven by random defects! 51

52 Conclusions As we continue to scale -» Reliability challenges become greater Oxide integrity, Bias Temperature Instabilities, Hot Carriers, electromigration new mechanisms? Reliability mechanisms must be taken into account for successful designs as technology scales and new materials are introduced Reliability Issues gate the viability of many new promising technologies The generation of physics based reliability models are an integral part increased reliability. Silicon based CMOS and SiGe technologies exhibit an outstanding reliability record 52

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54 Questions? 54