Interconnects and Reliability

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1 Interconnects and Reliability Sandip Tiwari Logic Interconnects SRAM: IBM J. R&D (1995) Insulators/Reliability 1 Prologue Global Middle Local 2

2 Interconnects Fringing & Coupling Capacitances Local obability Pro Global Wire Length (unit of die-size) Technology scaling occurs with increasing average interconnect length and routing density and increased interconnect aspect ratio Interconnects grow linearly with cells in ordered arrays (memories, e.g.) Interconnects grow as the square of the elements in random logic Local (intra-block) wires scale with block size, but global (inter-block) wires do not. Tiwari_12_2009_iWSG_Technology.pptx 3 Below the Interconnect D. Antoniadis IBM J R&D (2006) 4

3 Strip Line Capacitance Reducing line width will not reduce C 0 proportionally for small w/h 5 Clokc Skewing probe points on chip Clock signals in 400 MHz IBM Microprocessor (measured using e-beam prober) P. Restle (1998) Transmission line effects cause overshooting and non monotonic behavior 6

4 Time Scales of Pulse Propagation Scale of distances and delays (c/n): Board 20 cm 0.67 ns Chip 1 cm 33 ps Logic Units 0.1 cm 3.3 ps Short Interconnects: Capacitive (lumped), Cross-talk & Noise Long Interconnects: Transmission lines, cross-talk & noise, ground loops Interconnects that need to maintain precise timing and match in jitter: Clocks 7 Short Transmission Lines Open Short e.g., if 8

5 Transmission Line Implication Scale of distances and delays (c/n): Board 20 cm 0.67 ns Chip 1 cm 33 ps Logic Units 01cm ps 3.3 Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is quite smaller than the time-of-flight of the transmission line (t flight ) t r (t f ) << 2.5 t flight Transmission line effects increasingly important when the total resistance of the wire is limited: R < 5 Z 0 The transmission line treatable as lossless when the total resistance is substantially smaller than the characteristic impedance: R < Z 0 /2 9 Matching Z 0 Z 0 Z L Series Source Termination Z S Z 0 Z 0 Parallel Destination Termination 10

6 Lossless Transmission Line Pulse impedance: For a load,, reflection coefficient i Open: Short: 11 On Chip Transmission Line On chip, usually, 12

7 Capacitively Coupled Noise Active Floating 13 Loosely Coupled Transmission Lines From Odd and Even mode analysis: Inductive Coupling, Short line: Inductively coupled component is negligible for most on-chip conditions 14

8 Crossing Lines on Chip Non Transverse EM (non TEM) Slow wave structure Strong coupling between parallel lines Source of ground loop problems 15 Lossy Lines For low loss: Vlt Voltage doubling at tline end compensates for loss, but may cause problems at intermediate points 1 st 2 nd For high loss: ns μm 2 Ω ps 0.2 5x x

9 Skin Effect Skin Depth On chip TEM line Assume delay is limited by wire resistance Then, Narrow line Wide line Skin effect is unimportant for usual case of on-chip propagation. But, if size becomes too small, scattering effects from surfaces would contribute 17 Using Bypass for Resistive Lines WL Driver Polysilicon word line Metal word line Driving a word line from both sides Metal bypass WL K cells Polysilicon word line Using a metal bypass 18

10 Long Lines: Reducing RC Delay Repeater 19 L di/dt V DD L i(t) Vin L V DD V out C L GND Impact of inductance on supply voltages: Change in current induces a change in voltage Longer supply lines have larger L Critical to design power lines for low inductance 20

11 Segmenting Matched Line Drivers In VDD Z 0 s 0 s 1 s 2 s n Z L c 1 c 2 c n GND 21 V DD L = 2.5 nh Output Driver Terminations Clamping Diodes V DD 120 V in L = 2.5 nh V s Z 0 = 50 Ω V d 275 C L= 5 pf C L 4 V d L= 2.5 nh 3 V in 2 V s Initial design V d V in 2 V s time (sec) Revised design with matched driver impedance 22

12 Parallel Terminations: Using Resistance from Transistors V bb V dd M r Out V dd M rp M rn V dd M r Out Out V PMOS with-1v bias NMOS only PMOS only NMOS-PMOS V R (Volt) 23 Electromigration 24

13 A Cross-Section Insulators Interconnects Transistors Tiwari_12_2009_iWSG_Technology.pptx 25 Maxwell s Equations Original Scaled Scaling Factors 26

14 27 Low κ Oxide Density (g/cm 3 ) Dielectric constant (κ) ~ Modulus (GPa) ~ Hardness (GPa) ~ cte (ppm/k) ~ Porosity ~35-65% none Average Pore < nm none Thermal Conductivity (W/m.K) 28

15 Damascene (111) (100) (110) 1.2 μm 29 30

16 Metal Resistivity At <200 nm, Cu Resistance starts to rise Grain boundaries and interface scattering with Ta based barriers 31 Voids and accumulation caused by flux divergence, accelerated by stress and temperature 32

17 Interconnects Passivated Cu: 350 nm, width 600 nm Stress temperature: 230 C Current densities increased up to 10 7 A/cm2 during ~17 hrs Sneider, Fut Fab Vol19 33 Electromigration Technology & Reliability Issues e - Hillocks Nucleation on defects (111) Metal Voids (100) 300 nm 300 nm Before After 34

e - Technology & Reliability Issues Voids!

(111) Metal Voids Dielectric cracking! Porosity!

in the direction of electron flow caused by

alloying with Cu and conductive barrier/liner

Effective charge Diffusivity Electromigration

18 e - Technology & Reliability Issues Voids! Electromigration Low k Diffusion Barrier! (111) Metal Voids Dielectric cracking! Porosity! 300 nm 300 nm 35 Electromigration Drift of atoms in the direction of electron flow caused by fields: electron wind Aluminum: mitigated by alloying with Cu and conductive barrier/liner layers Nernst Equation: Atom drift velocity Effective charge Diffusivity Electromigration driving force Intrinsic atom mobility Field ed resistivity s Current density 36

19 Reliability of Insulators In transistors: thick and thin oxides and consequences of high κ with particular emphasis on NBTI Implications for circuits In Flash Memories implications of relatively thick oxides 37 Gate Dielectric: Nitrided Oxide with polysi Leaky, difficult to control, B penetration, SILC, soft breakdowns, NBTI, PBTI, 38

20 Metal Gates and High κ 39 Plasma Damage Linder, P2ID(1948) Thin Oxides (scaled devices) reduced damage Thick Oxides (IO devices) damage persists New effects at small dimensions: i new dielectrics, i different BEOL dielectrics i and processing techniques (UV cure?) and heavy dose implants 40

21 Old: Charge to Breakdown Defect generation to Breakdown DiMaria, APL(1997) 41 Bias Dependence of Breakdown Growth From 0 to 100 μa breakdown leakage in 300 years of continuous operation J. Stathis (2008) 42

22 Charge to Breakdown Percolation Stathis, IRPS(2001) and JAP (1999) 43 Stress Induced Leakage Current SILC 44

23 Oxides and Transport in Insulators Oid Oxides: The properties of SiO 2 change to bulk like over a length scale of about 2 monolayers. Direct tunneling is certainly quite significant at sizes below about 1.5 nm. What does electron transport do when biases are applied in oxides? Energy losses in the insulator breaking bonds and trapping carriers (so charge in oxides, and sites in oxides through which electron transport can take place (e.g. by percolation) Energy losses at interfaces breaking bonds, releasing ionized species that can then move in applied fields Magnitudes of various effects depend on how thick oxides are, bias conditions and multiple phenomena may be important simultaneously. Effects may be hard, i.e. abrupt or soft, i.e. a gentle degradation 45 Dielectric Reliability: Nitridation Hardening Bulk properties lost below 2 monolayers Below 32 nm, SiON required for appropriate EOT (electrical thickness) is very high in N Power law mechanisms may involve the release of H 0 and dh + from poly-sion interface E. Wu, IEDM(2000) P. Nicollian IRPS (2003) & IEDM(2005) 46

Outline Ultra-thin oxide breakdown Progressive

Temperature Instability (NBTI) Role of Nitrogen New

Progressive Breakdown Hard Breakdown doesn t happen

over a measurable time scale Degradation rate is

24 Outline Ultra-thin oxide breakdown Progressive breakdown Circuit it implications Negative Bias Temperature Instability (NBTI) Role of Nitrogen New materials Comments for thick Oxides (NVRAMs) 47 Progressive Breakdown Hard Breakdown doesn t happen suddenly as a catastrophic process Happens gradually over a measurable time scale Degradation rate is slower for lower stress voltages Log time scale Hosoi, IEDM(2002) 48

T. Hosoi, SSDM(2002) 49 Interface State Distribution Mid-gap

25 What does it Mean? Thick Oxide High Voltage Stress Ultra-Thin Oxide Low Voltage Stress T. Hosoi, SSDM(2002) 49 Interface State Distribution Mid-gap defects with gated diode peak Conduction band edge defects with flat- band gate leakage (LV-SILC) Stathis, INFOS(2005) 50

Interpretation All breakdown is progressive

Progressive BD can be stopped at intermediate

circuit dependent 51 Negative Bias Positive

Charge exchange: Hole trapping or electron

26 Interpretation All breakdown is progressive Continuum of rates of post-bd current growth Progressive BD can be stopped at intermediate current level Operational definitions are circuit dependent 51 Negative Bias Positive bias shifts away from the SiO2/Si interface Charge exchange: Hole trapping or electron detrapping increases the net positive charge at the Si/SiO 2 interface 52

27 NBTI: A Serious Reliability Issue pmos threshold shift (drain current reduction) Interface states and positive oxide charge Serious concern for low V DD new technologies Nitridation worsens NBTI 53 Channel Hot Carrier Issues with Scaling Decreasing lifetime L g shrinking while V DD scaling limited Increased use of well bias => additional stress JW McPherson, IEDM(2005) 54

28 NBTI Reddy, IRPS(2002) Lower Thermal budget Ox thick. scaling Nitridation SOC Ox thick. scaling BEOL Power dissipation 55 NBTI: Negative Bias Temperature Instability Negative Bias Temperature Instability pfet on-state (holes involved) Thermal activation: ~0.2 ev Miura & Matukura, JJAP(1966) Power law dependence of t n with n ~ Source believed to be electrochemical reaction with a hydrogen related species in the oxide Reaction/diffusion i 56

29 NBTI: Dispersive Transport Zafar, JAP(2005) Hydrogen density calculated from kinetics (is statistical) Creation of interfacial and oxide traps Interfacial and oxide traps have charged and neutral states t Charge state densities follow Fermi function Correct treatment of the drift/diffusion of [H] including dispersive nature of process in amorphous medium Dispersive transport arises when mobile species experiences a broad distribution of barrier heights leading to an exponentially broad distribution of hopping times Causes stretched exponential This reduces to power law form and accounts for saturation at long times at short times, 57 Process Influence Nitridation of gate oxide enhances NBTI Deuterium some publications show improvement Fluorinated gate oxide reduces NBTI Improvement diminishes with nitridation Oxidation conditions and tooling BEOL charging enhances NBTI effect Composition of contact etch stop layer and stress films 58

30 Circuit Implications 59 SRAM Increasing asymmetry from NBTI and PBTI PBTI more sensitive to T inv SRAM cell itself more sensitive to NBTI Read affected more than Write A. Bansal, Micro Rel (2009) 60

31 Implications of Progressive Breakdown Many characteristics are not strongly perturbed by oxide breakdown e.g. transconductance (gm) and threshold voltage (V T ) Strongest implication is in an increase in off current in gate-drain or gate-source leakage Include power law equation from breakdown curves 61 Inverter Transfer Characteristics Loads output of 1 st inverter by breakdown in 2 nd Logic may tolerate high breakdown leakage (~10 μa)with reduced noise margin (is another source of variability) 62

32 SRAM Static Noise Margin At breakdown current > 50 μa, SNM reduced by 50% Worst case: n-source breakdown Pulls down voltage at opposite node Loads a weaker pfet Rodriguez, EDL(2002) 63 Circuit Failure Distribution Follows from Weibull ebu distribution ds of oxide BD times (β=1 for t ox < 2 nm): Assumed exponential distribution of post BD times (Δt): E. Wu, IEDM(2003) 64

33 Circuit Failure Distribution Example: For 100 ppm failure (F=10-4 ) A 100x increase in lifetime 65 High κ 66

34 HfSiON: SiO 2 Shanware, IEDM(2003) 2-3 orders of reduced leakage over SiO2 Carrier mobility is ~20% below universal curve at high fields Thermal stability to 1100 C 67 High κ Breakdown Breakdown strength decreases with κ Field/voltage acceleration g increases with κ (useful in burn-in and stress testing) 68

35 NBTI in High κ Similar to SiO 2 Interface dominated Power law time dependence Saturation Relaxation Dependence on temperature & field Zafar, EDL(2005) 69 High κ Stability Shanware, IEDM(2003) Some of the high κ dielectrics are quite unstable under stress Lower breakdown strength will affect thickness scaling 70

HfO 2 /SiO 2 Stack Stressing Two time constants (others have observed three) At the

) Then, degradation due to stressing A third one, depending on thicknesses, due to

Amat, Microelectron Rel (2007) 71 Recovery: Metal Gate with high κ Recovery and

36 HfO 2 /SiO 2 Stack Stressing Two time constants (others have observed three) At the beginning: due to preexisting traps(?) Then, degradation due to stressing A third one, depending on thicknesses, due to hard breakdown E. Amat, Microelectron Rel (2007) 71 Recovery: Metal Gate with high κ Recovery and recovery rate after stressing Interface properties affect ΔV T, but little effect on recovery Stressing field, rather than stressing voltage, influences NBTI recovery in pmosfet M. Wang, Micro Eng (2009) 72

37 Metal Gate 73 FUSI: fully silicided Metal Gates Higher dielectric leakage and reduced breakdown strength with metal gates (FUSI) Electric stressing show higher V T shifts in metal gates Metal gates: Stability of interface under NBTI and PBTI Process impact of charging, breakdown, TDDB Workfunction variability 74

Metal Gate Breakdown Transients Fast breakdown transients t (i.e. hard breakdown) observed in metal gates FETs in the voltage range where polysi gate show progressive breakdwon Advantage of

38 Metal Gate Breakdown Transients Fast breakdown transients t (i.e. hard breakdown) observed in metal gates FETs in the voltage range where polysi gate show progressive breakdwon Advantage of progressive breakdown lost for metal gates Palumbo, IRPS(2004) 75 Metal Gate with High κ At <1 μa, progressive breakdown before catastrophic breakdown The increase in stress current just before hard breakdown is progressive breakdown since independent of device area and localized in the same position as final hard breakdown S. Lombardo, ISAGST(2006) 76

39 Charge Trapping Dependence on Gate Metal gates are better Silicide is similar to polysi polysi/high κ interactions appear to be prime suspect for charge trapping instabilities in polysi and FUSI devices PBTI has a stretched exponential dependence similar to NBTI Gusev, IEDM(2004) 77 Summary For polysi gates: Hard breakdown is a slow ( progressive ) process : Breakdown criterion is circuit-dependent Circuit failure will be later than initial oxide breakdown For metal gates: Progressive breakdown is less apparent V T stability is a concern for oxynitride and new dielectrics/gates 78

40 Back Up 79 80

41 Clock Span Increasing f clk and speed Reduced logic span Higher electromagnetic coupling: capacitive coupling inductive bounce Source: Saraswat Tiwari_12_2009_iWSG_Technology.pptx 81 Transmission Line V in l l l l r r r x r V out g c g c g c g c The Wave Equation 82

42 Taking the repeater loading into account Repeaters For a given technology and a given interconnect layer, there exists an optimal length of the wire segments between repeaters. The delay of these wire segments is independent of the routing layer: 83 Inductance in Supply Lines ut (V) V ou i L (A) x 10-9 Without inductors With inductors decoupled x x x V L (V) time (nsec) x 10-9 time (nsec) x Input rise/fall time: 50 psec Input rise/fall time: 800 psec 84

Mitigating Inductive Effects Separation of power

ground pins Careful positioning of the power and

fall times of the off-chip signals to the maximum

transitions Improved packaging Add decoupling

Minimum voltage of SRAM affected by combination of

43 Mitigating Inductive Effects Separation of power pins for I/O pads and core Multiple power and ground pins Careful positioning of the power and ground pins on the package Increase the rise and fall times of the off-chip signals to the maximum extent allowable Schedule current-consuming transitions Improved packaging Add decoupling capacitance 85 SRAM cell Flip Failure Envelope Minimum voltage of SRAM affected by combination of NBTI (pfet VT shift) And Oxide progressive breakdown Mueller, IRPS(2004) 86

44 Metal Gate High κ Major issue Mobility degradation Threshold h voltage control For high κ, electron trapping under positive bias (PBTI in nfet) is a new concern 87

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation