EE141-Spring 2007 Digital Integrated Circuits. Administrative Stuff. Last Lecture. Wires. Interconnect Impact on Chip. The Wire

Transcription

1 EE141-Spring 2007 Digital Integrated Circuits ecture 10 Administrative Stuff No ab this week Midterm 1 on Tu! HW5 to be posted by next Friday Due Fr. March 2 5pm Introduction to wires 1 2 ast ecture ast lecture CMOS scaling Today s lecture Introduction to wires Wires 3 4 The Wire Interconnect Impact on Chip tra nsmitte rs receivers schematics physical 5 6

2 Wire Models All-inclusive model Capacitance-only Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive 7 8 Nature of Interconnect INTERCONNECT ocal Interconnect Pentium Pro (R) Pentium(R) II Pentium (MMX) Pentium (R) Pentium (R) II No of nets (og Scale) S ocal = S Technology Global Interconnect S Global = S Die Source: Intel ,000 10, ,000 ength (u) 9 10 Capacitance of Wire Interconnect Capacitance: The Parallel Plate Model V DD V DD M2 C db2 C g4 M4 Curre nt flow V in C gd12 2 W Electrical-field lines M1 C db1 C w Interconnect C g3 M3 H t di Dielectric Fanout Substrate Simplified Model V in C 11 c int ε di = W t di S Cwire S 1 = = S S S 12

3 Permittivity Fringing Capacitance (a) H W - H/2 + (b) Fringing versus Parallel Plate Interwire Capacitance frin ging pa rallel (from [Bakoglu89]) Impact of Interwire Capacitance Wiring Capacitances (0.25 µm m CMOS) (from [Bakoglu89]) 17 18

4 INTERCONNECT Wire Resistance R = ρ H W H Sheet Resistance R o W R 1 R Interconnect Resistance Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length e.g. copper, silicides More Interconnect ayers reduce average wire-length Polycide Gate MOSFET Sheet Resistance Silicide PolySilicon SiO 2 n + n + p Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly 23 24

5 Modern Interconnect Example: Intel 0.25 micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric Modern Interconnect Interconnect 90nm process The umped Model The Distributed RC ine Driver c wire Rdriver Vin Clumpe d 29 30

6 Step-response of RC wire as a function of time and space The Elmore Delay RC Chain x= /10 voltage (V) x = /4 x = /2 x= time (nsec) Wire Model RC Models Assume: Wire modeled by N equal-length segments For large values of N: The umped RC-Model The Elmore Delay Driving an RC-line Rs (r w,c w,) Vout V in 35 36

7 Design Rules of Thumb INTERCONNECT rc delays should only be considered when t prc >> t pgate of the driving gate crit >> t pgate /0.38rc rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line t rise < RC when not met, the change in the signal is slower than the propagation delay of the wire MJIrwin, PSU, Common Wire Cross-Sections Inductance of package pins Bonding Wire Chip Mounting Cavity Coaxial Cable Triplate Strip ine MicroStrip Wire above Ground Plane ead Frame 2πε c = log r2 r1 µ l = log 2π r2 r1 ε c = h W h l = µ W cl = εµ c - capacitance/length l - inductance/length 39 Pin Make Rise- and Fall Times as slow as possible 40 The Transmission ine ossless Transmission ine - Parameters V in r l r l r l x r l speed of light in vacuum g c g c g c g c The Wave Equation 41 42

8 Wave Propagation Speed Wave Reflection for Different Terminations Transmission ine Response (R = ) attice Diagram VSource VDest V V R S = 5Z 0 R S = Z 0 (a) (b) V Dest VSource t V V V V V V V V V /ν 2.0 R S = Z 0/ t (in t lightf) (c) 45 V at each end = V last + V incident + V reflected 46 Critical ine engths versus Rise Times Design Rules of Thumb Transmission line effects should be considered when the rise or fall time of the input signal (t r, t f ) is smaller than the time-of-flight of the transmission line (t flight ). crit ~ 1cm ps today (1990, Bakoglu) t r (t f ) << 2.5 t flight Transmission line effects should only be considered when the total resistance of the wire is limited: R < 5 Z 0 The transmission line is considered lossless when the total resistance is substantially smaller than the characteristic impedance, R < Z 0 /

9 Should we be worried? Next ecture CMOS ogic Transmission line effects cause overshooting and nonmonotonic behavior Clock signals in 400 MHz IBM Microprocessor (measured using e-beam prober) [Restle98] 49 50