The Physics of Soft-Breakdown and its Implications for Integrated Circuits

Transcription

1 The Physics of Soft-Breakdown and its Implications for Integrated Circuits Muhammad Ashraful Alam in collaboration with B. Weir, P. Silverman, and R. K. Smith Agere Systems, PA 18109

2 What is Soft-Breakdown SOURCE GATE DRAIN J GATE (A/cm 2 ) HBD SBD before V GATE (Volts) localized increase in current through the gate observed mainly in thinner oxides at lower voltages SBD conduction is non-ohmic retains insulating property, while post-hbd conduction is ohmic.

3 Oxide Degradation and Soft-Breakdown Gate Current HBD ln (time) SBD Gate current stable after each soft-breakdown event. May extend operating lifetime for an integrated circuit

4 Outline 1. A short history of soft-breakdown research 2. Device functionality after soft-breakdown 3. The digital divide between soft and hard breakdown 4. Lifetime enhancement due to multiple soft-breakdown 5. Implications for circuit functionality 6. Conclusion

5 SBD as an Interesting Phenomenon ( ) Papers: 1. K. Okada, Proc. of SSDM, 1994, p S.-H. Lee et al., IEDM 1994, p M. Depas et al., ITED 1996, vol. 43, p Topics Discussed: (a) Localized ( and anomalous) increase in gate current (b) Detection of SBD - by current jump in small area capacitors - by noise increase in large area capacitors (c) Implied that this stage is a precursor to hard breakdown

6 SBD vs. NMOS Reliability ( ) Papers with NMOS TDDB Concerns: 1. R. Degraeve et al., ITED 1998, p Weibull slope decreases with oxide thickness 2. J. Stathis and D. DiMaria, IEDM 1998, p trap generation rate reduces exponentially with voltage with a constant voltage acceleration factor SBD Papers: 1. B. Weir et al., IEDM 1997, p E. Wu et al., IEDM 1998, p. 187 Topics Discussed: (a) dependence of soft-breakdown on operating voltage, oxide area, and thickness. (b) influence of soft-breakdown on transistor characteristics

7 Bonnie Weir presented first systematic study of SBD, IEDM V start 5.5nm -5-4 thickness dependence Gate Voltage nm 2.8nm 2.4nm V postbd Stress Time (sec.) V postbd nm 4.0nm 5.0nm 6.5nm Stress at -1mA/cm V postbd mA/cm 2-1mA/cm nm oxide -10mA/cm 2-100mA/cm V start stress dependence Postbd Voltage V start area dependence 1E-5 1E-4 1E Capacitor Area (cm 2 )

8 SBD Irrelevant for NMOS Transistors 3.0 V op, V safe NMOS ITRS oxide thickness (nm)., because the NMOS degradation reduces faster than anticipated

9 SBD Papers (circuit): SBD and Circuit Reliability (1999- ): A study without a cause? 1. B. Kaczer et al., IEDM 2000, p. 553 (ring oscillator) 2. Rodriguez et al., EDL 2002, p. 559 (SRAM Cell) SBD Papers (statistics): 1. J. Sune and E. Wu, IEDM 2002, p M. Alam et al., Nature, 6914, p. 378, Topics Discussed: (a) Performance of circuit functionality after soft-breakdown (b) Total power dissipation and lifetime of ICs with multiple breakdown events.

10 .. not really: PMOS unreliable with std. definition 3.0 V op, V safe NMOS ITRS PMOS oxide thickness (nm) Q. Is the p-mos reliability a real issue? Q. If so, will soft-breakdown help?

11 Anode-Hole Injection Model T BD OXIDE = e NBDx N k k n Anode h J 1 αt J e a T p J e - Electron current density a - Impact Ionization Rate (probability that a hole will be created by an incoming electron) T p - Transmission Rate (probability that the hole will travel through the oxide layer) k - Trap Generation Efficiency (probability that the hole will create a percolation defect) Cathode N BD - Density of percolation defects at breakdown

12 NMOS was the biggest concern J GATE (Amps/cm 2 ) T BD = N k BD NMOS in inversion Positive voltage 3.5nm oxide 25 C n J p V GATE (Volts) e 1 αt PMOS in inversion Negative voltage J NMOS > J PMOS All other factors being equal, T BD for NMOS would be ~100x shorter than T BD for PMOS. NMOS reliability was the limiting factor.

13 .but, all other factors are not equal αt p or I HOLE /I ELEC Negative Voltage V GATE PMOS Positive Voltage T BD = N k n BD 1 JeαT Hole generation efficiency predicted to be much higher for PMOS (at negative voltage) due to minority ionization. Minority ionization occurs when the valence band of the anode contains empty states. NMOS p p+-poly Gate n+ poly Gate p-well n-well Bude(IEDM98) Alam(IRPS00) Palestri(SISC00)

14 PMOS less Reliable than NMOS below 2 nm T BD ~ 1/J h with J h = J e <at h > NMOS PMOS J e J e J h gate gate J h For oxide < 2 nm: J h PMOS > J h NMOS, so T BD PMOS < T BD NMOS Bude, IEDM98 Alam, IRPS00 Weir, ECS02

15 Voltage Acceleration Factors Compared Median T BD (sec.) dec./v (low voltage region) 6 dec./v (all data) PMOS decs./v decs./v T BD from SILC 10-3 TDDB Gate Voltage 7.9 dec./v (low voltage region) 6.7 dec./v (all data) 5.9 dec./v 5.2 dec./v NMOS ~ 4.5 volts or more: PMOS and NMOS acceleration comparable ~ V: PMOS voltage acceleration lower than NMOS < 2.5 volts: PMOS and NMOS acceleration comparable

16 Power-law would not fit PMOS data Median T BD (sec.) deviates from power law nmos (scaled data) pmos (scaled data) Gate Voltage Power-law is a graphical aid

17 Motivation: PMOS unreliable with standard definition 3.0 V op, V safe NMOS ITRS PMOS oxide thickness (nm) A conservative estimate; non-linearity in trap generation below 2.0 volts may increase Vsafe somewhat.

18 Outline 1. A short history of soft-breakdown 2. Device functionality after soft-breakdown Drive current and trans-conductance Off-current Threshold voltage shift 3. The digital divide between soft and hard breakdown 4. Lifetime enhancement due to Multiple soft-breakdown 5. Implications for circuit functionality 6. Conclusion SOURCE SOURCE before after GATE GATE DRAIN DRAIN

19 Drive Current and Trans-conductance Before Stress After SBD I d gm (ms/mm) I d gm (ms/mm) V g V g Before and after SBD, changes in drive current and trans-conductance are insignificant Weir et al. IEDM-97

20 Off-Current Current (A) 1E-3 1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 1E-14 Ig Id Is Ib Vgate 1.7nm. Vg=3.8V (stress), Vd=1.2V (meas) No GIDL (drain to body current) observed

21 Off-Current Increase Small at All Positions 1E-8 measurement simulation I g,off (A) 1E-9 1E-10 1E Source Drain Relative Position (equispaced) Source Drain Actual Position (sim.) Weir, INFOS01

22 Threshold Voltage: Small at All Positions Threshold Voltage Shift (mv) Source Drain Relative Position (Equispaced) Threshold Voltage Shift (mv) nm oxide -3.8V stress VT measurement: Vd=0.1V Id=0.1µAxW/L Time to Breakdown (sec.) Mean threshold voltage shift is small: more on this later

23 Drain and Gate Noise Gate Current Noise Drain Current Noise Post Breakdown Post Breakdown Noise (A 2 /Hz) Pre-Breakdown Frequency (Hz) Noise (A 2 /Hz) Pre-Breakdown V gate =2.5V, V drain =0.1V Frequency (Hz) For low input-impedance circuits, soft breakdown does not degrade I DS noise.

24 Outline 1. A short history of soft-breakdown 2. Device functionality after soft-breakdown 3. The digital divide between soft and hard breakdown A theory of hard and hard breakdown Area, thickness, and voltage dependence 4. Lifetime enhancement due to Multiple soft-breakdown 5. Implications for circuit functionality 6. Conclusion How do we show that the excellent properties of few soft-broken transistors just discussed will apply to hundreds of millions of transistors in an IC?

25 Will soft-breakdown increase the safe-op voltage 3.0 V op, V safe NMOS? PMOS ITRS oxide thickness (nm)

26 A Simple Model for SBD and HBD (IEDM02, p. 232) (a) t < TBD, only tunneling J s A C ox R t Gp (b) t = TBD, BD current initiates J s A C ox R t Gp P(t) (c) t > TBD, transient heating P(t) T Θ(ox) 1 T 2 Θ(Si) If P(t) exceeds certain threshold, HBD is possible

27 A Simple Model for SBD and HBD J s A C ox R t Gp P(t) AC ox ( dv/dt ) + Aa exp(-b/v) + {g 0 }V d = AJ I G (A) 15A V G (V) 65A log[ Ipost(mA) ] Post-BD V G (V) Pre-BD Probability From Meas. And Perc. Theory 5x10-7 1x10-6 Conductivity (Siemens) Alam, ITED 2002, p. 232

28 Why is the voltage dependence: Iperc ~ V δ? 1. Quantum point-contact (Sune, IRPS01) - focuses on voltage dependence Ballistic transport through defect chain Trap config. potential - voltage dependence from Fermi-functions 2. Coulomb blockade (Nigam,IRPS03) - focuses on temp. dependence Hopping through the defect chain - voltage dependence from charging of small area capacitors

29 Configuration and Conductance Occurences Conductivity (Arb. Units)

30 Statistical distribution of Gp Probability a 0 2.2a 0 2 nm 1.7 nm 2a nm 5x10-7 1x10-6 Conductivity (Siemens) Sim. (arb. units) Meas Sample 1 Sample 2 Sample n Weakly thickness dependent G max /G min = 5-10

31 Gp is known, how to determine P THER? V Cox R T Gp PDF SBD Gp,crit (V1) HBD P = G p V 2 PDF Gp,crit (V2) Gpcrit = P THER /V 2 SBD HBD By analyzing the ratio of soft to hard- broken transistors at V 1 and V 2, determine the value of P THER. Then, we can determine Vsafe. PDF SBD Gp Gp,crit (Vsafe) HBD

32 Gp Distribution, Power Threshold P = V stress I perc I postbd (1.5V) (Amps) HARD SOFT V g (Volts) Increasing number of HBD with stress voltage Sharp transition: V increase converts all BD from soft to hard

33 PTHER from Stress Current Dependence J s A C ox R t V(t) Gp Power V(t) VpostBD time V postbd (Volts) SOFT HARD I Stress (Amps/cm 2 ) Power (W) 10-5 SOFT BIMODAL I Stress (Amps/cm 2 ) HARD PTHER ~ 20 µw Alam, IEDM99, p. 449 Sune, IEDM01, p. 117

34 PTHER from Thickness Dependence J s A C ox R t V(t) Gp Power V(t) VpostBD time -5 V postbd SOFT HARD Power (W) 10-4 HARD HARD BIMODAL 10-5 SOFT SOFT V Start Oxide Thickness (nm) PTHER ~ 20 µw

35 Breakdown always soft at 1.0V PDF Gp,crit (Vsafe) SBD Gp HBD P crit =20 µw G crit = P crit /V 2 = 20 ms ( V=1.0 volt ) G p can be experimentally determined => Prob( Gp > Gcrit ) << 1.0e-12

36 Outline 1. A short history of soft-breakdown 2. Device functionality after soft-breakdown 3. The digital divide between soft and hard breakdown 4. Lifetime enhancement due to Multiple soft-breakdown Understanding spatial and temporal correlation Techniques of making projections 5. Implications for circuit functionality 6. Conclusion

37 Physical Reason for Lifetime Improvement new reliability definition Std. reliability definition Uncorrelated Many BD in IC before 2 nd BD in the same transistor? Correlated Few BD in IC before 2 nd BD in the same transistor

38 Spatial and Temporal Correlation Defined spatially and temporally uncorrelated spatially correlated SOURCE GATE DRAIN temporally correlated

39 How to Determine the Statistics of Trap Generation I s SOURCE GATE I d DRAIN Gate Current (ma) st SBD 3 rd SBD 2 nd SBD Loc of a breakdown spot: x = I d / ( I s + I d ) Time of breakdown: log (Time) T 1, T 2, T 3, etc. Degraeve, IRPS01

40 Theory of the Measurement Technique The relationship is linear in the channel because the dominant carrier transport mechanism is diffusion in accumulation I s SOURCE GATE I d DRAIN dn J = D + neµ dx J = 0 2 d n D = 0 2 dx n = Ax + B J J s s = D J + d J d n x perc perc = x L perc gate Common misconception: technique only works in accumulation!

41 Spatial Correlation: Measurements Location of 2 nd SBD spot Location of 1 st SBD spot

42 Spatial Correlation: Theory X P 1 [x 1 < x ] = x uncorrelated trap generation random loc. for 1 st BD x P 2 [ x 1 - x 2 < x ] = 2x - x 2 x 1 x 2 uncorrelated trap generation random loc. for 1 st and 2 nd BD

43 Spatial Correlation: Analysis Cumulative PDF P 1 = x P 2 = 2x - x 2 Cumulative PDF loc of 1 st SBD distance bet n 1 st and 2 nd SBD Trap generation is spatially uncorrelated (essentially)!

44 Temporal Correlation: Times to n-sbd Gate Current (ma) rd SBD 2 nd SBD 1 st SBD log (Time) W n = ln (-ln (1-F)) st 2 nd 3 rd 4 th ln (time to n-breakdown)

45 Temporally Independent Trap Generation: Theory M N Prob. of a filled column: p = q M Prob. of filled cell: q=(at α /NM) Prob. of exactly n-sbd Prob. of >= n SBD P n = N C n [p n ] [(1-p) (N-n) ] P n = (χ n /n!) exp( χ) with χ=(t/η) β and β=mα n-1 F n (χ)= 1 - Σ P k (χ) k=0 measured data: W n = ln [ -ln (1-F n ) ]

46 Temporal Independence Confirmed n-1 F n (χ)= 1 - Σ P k (χ) k=0 W n = ln (-ln (1-F)) st 2 nd 3 rd 4 th F n (χ) > F 1 (χ) W n scaled Temporal Correlation ξ < 10% rd (scaled) 2 nd (scaled) 1 st 4 th (scaled) ln ( time to n-breakdown)

47 n- SBD Weibull Distribution Lifetime Improvement percentile area n=1 n=2 n= log ( projected breakdown times (sec)) 100 million Transistors 1 part per 10 4 failure

48 Lifetime Improvement (T n (ξ=0) /T 1 ) β = (n/e)(2πn) 1/2n /F n (1-1/n) 4 Relative Improvement log10 (Tn/T1) β n=3 n=2 n=1 n=4 Theory log10 [Failure Fraction]

49 Robustness of the Lifetime Improvement (T n (ξ)/t 1 ) β = [1/(1+nξ/2) (1-1/n) ] (T n (ξ=0) /T 1 ) β 2 Weibull Distribution n= χ= (t/η) β n=2 (0%) (50%) (100%) (300%) Even with 300% increase in trap generation after SBD, the reduction in lifetime improvement is small Alam, IRPS03

50 Physical Reason for Lifetime Improvement Std. reliability definition new reliability definition Area of the transistor matters more than the area of the IC. Scaling may help reliability!

51 Uncorrelated BD Increases Safe Op. Voltage W n Accelerated test n=2 n= log ( TBD (sec)) No SBD Allowed: V safe small Enhanced lifetime can be traded for higher speed! One SBD Allowed: V safe larger

52 Maximum safe operating voltage 3.0 PMOS 2.5 V op, V safe nd SBD ITRS 01 SBD Threshold st SBD oxide thickness (nm) Assumption violated: soft breakdown threshold exceeded Vsafe = min Vmax, Vcrit

53 Determination of Vcrit Gate Current HBD ln (time) P crit SBD V P = V 2 /{R perc } < P crit Soft BD Prob < 1 V crit Soft BD Prob = 1 Exact V crit depends on reliability specifications and compliance Alam,IEDM99 Sune, IEDM01

54 V op, V safe (volts) New Reliability Limits Multiple SBD PMOS ITRS SBD Threshold 1 st SBD oxide thickness (nm) 130 nm technology: ~ 1 SBD per transistor expected 90/65 nm technology: ~ 2 or 3 SBD per transistor

55 Outline 1. A short history of soft-breakdown 2. Device functionality after soft-breakdown 3. The digital divide between soft and hard breakdown 4. Lifetime enhancement due to Multiple soft breakdown 5. Implications for circuit functionality Leakage current Threshold voltage shift Static Circuits Dynamic Circuits 6. Conclusions

56 Analysis of Leakage Current with multiple SBD I o = current per SBD N T = # of transistors Gate Current (I leak ) We analyzed the early stage with few SBD ln (time) Others focus on later stage with many SBD Theory Meas. (I leak /N T I o ) = Σ np n = (t/η) β, so that ln [I leak ]=β[ln(t)+ γ V (V-V 0 ) + γ T (T-T 0 ) - ln(η 0 ) +const] Alam, IEDM2002; Nafria, JAP(73), 1993

57 Predicted Time dependent Leakage Current ln [I leak ]=β[ln(t)+ γ V (V-V 0 ) + γ T (T-T 0 ) - ln(η 0 )+const.] Hosoi, IEDM02 Monsieur, IRPS02 β= slope β indicates statistically-independent soft-breakdown 2. If β ~ 1, I leak can be plotted linearly with time (Linder, IRPS03)

58 Predicted Voltage Dependence of Delay Time ln( Ileak) 350 µm V1 V2 Monsieur, IRPS02 ln (Time) Fitting Formula: t 350um =η 1 exp(αt ox + γ V V) but the fitting formula is easily derived from theory ln [I leak =350 µm]=β [ln(t 350 )+ γ V (V-V 0 ) - ln(η o ) +const] so that t 350 = η 1 exp(αt ox + γ V V) γ V ~ /V for 2.0 nm NMOS at 4.0 volts!

59 Voltage-Dependent Leakage: B. Linder, IRPS 2003 Fit function: ln(i leak /t) = 11.5 V + const. Linear degradation rate again this formula is anticipated from theory ln [I leak ]=β[ln(t)+ γ V (V-V 0 ) - ln(η 0 ) + const.] for thin 1.0 nm oxide, assume β ~ 1, so that ln(i leak /t) = γ V V + constant γ V ~ /V for 2.0 nm PMOS at ~ 3.0 volts!

60 SBD current smaller than Gate Leakage Current Normalized log10(ioff) Ioff(S-D) Igate I SBD Statistically independent soft-breakdown current for IC with 1.7 nm oxide is negligible compared to other components of off-current

61 W n log [V T (volts)] Threshold Voltage Shift negligible n=1 n=2 1 mv log ( time (sec)) n=3 10 µv Threshold voltage shift is important for multiple SBD must not exceed NBTI or HCI threshold 10% or ~ 5 mv

62 Change in Circuit Speed: negligible with SBD Shapira, 2002 Kaczer, IEDM00 Fast delay (ps) delay with SBD(ps) Nominal With SBD < 10-2 % change in speed With HBD < 15 % change in speed

63 Summary hard breakdown soft breakdown Lifetime improves because soft breakdown events are statistically uncorrelated (T n /T 1 ) β = (n/e)(2πn) 1/2n /F n (1-1/n)

64 Summary PDF PDF PDF Gp,crit (V1) HBD SBD Gp,crit (V2) HBD SBD Gp,crit (Vsafe) 1. Low enough voltage always guarantees soft breakdown. 2. When reading literature, it is important to check if the stress voltage was low enough to ensure soft breakdown. SBD HBD Gp

65 Summary 1E-8 measurement simulation I g,off (A) 1E-9 1E-10 1E Source Drain Relative Position (equispaced) Source Drain Actual Position (sim.) Breakdown near drain increases leakage current, but when stressed at low operating voltage, the increase is still acceptable.

66 Summary (a) (b) (c) T=0 T < TBD T = TBD No sudden changes in threshold voltage and gm are expected due to the soft-breakdown event itself, because total number of traps just before (b) and after (c) breakdown remain almost the same. (d) T > TBD

67 W n log [V T (volts)] log ( time (sec)) Summary n=1 n=2 n=3. 1 mv 10 µv Mean threshold voltage shift and gm are misleading indicators of the usefulness of the devices after SBD, especially for small area transistors. Should look for low percentile values of these parameters

68 Summary Gate Current (I leak ) ln (time) Leakage at large SBD limit All the results reported in the literature for SBD leakage current appear to be different manifestations of the same uncorrelated soft-breakdown events described by this equation: (I leak /N T I o ) =(t/η) β

69 Summary Impossible to check SBD integrity of all the different types of circuits, however, one does not need to.. Memory block Digital block analog block If memory and digital blocks occupy most of the IC and are insensitive to one SBD, then even without knowing the sensitivity of the circuits in the analog block or in the critical path, it is possible to ensure that the acceptable failure fraction is never exceeded.

70 Conclusions Study of soft-breakdown was curiosity-driven, but it may end up saving Moore s law! Soft breakdown does not perturb transistor function significantly and the fraction of soft-broken transistors in a given IC can be increased by reducing the operating voltage. If a transistor can sustain even one soft breakdown, the lifetime of the IC increases geometrically. Therefore, transistor scaling helps reliability! Soft breakdown currents are plotted in many different forms - the underlying physical phenomenon appears to be identical. Excess reliability can be traded for higher circuit speed. Oxide reliability, in the traditional sense, may no longer be a reliability concern. However, leakage limit (Power/EM) or threshold voltage limits (HCI/NBTI) must still be considered carefully.