The drive to make devices smaller and faster

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Parametric Measurement Issues with 100 nm CMOS LARRY DANGREMOND, Cascade Microtech, Inc., Beaverton, OR, USA A BSTRACT The drive to make devices smaller and faster continues.

1 Parametric Measurement Issues with 100 nm CMOS LARRY DANGREMOND, Cascade Microtech, Inc., Beaverton, OR, USA A BSTRACT The drive to make devices smaller and faster continues. CMOS geometries are driving towards 100 nm, presenting a major challenge to those responsible for ensuring accurate modelling and reliable processes. Modern instruments have the accuracy and resolution for the task but achieving high-accuracy parametric measurements on-wafer is the challenge. Any capacitance in the measurement path is a major roadblock to speedy, accurate low-level testing. Over-temperature testing (not addressed in this article) aggravates this even further, and additional problems occur when trying to make multi-pin probe card measurements. Solutions are possible, as this article suggests. INTRODUCTION Sub-micron CMOS processes have allowed the production of integrated circuits with millions of transistors. The push towards 0.1 micron scaling makes accurate parametric measurement and modelling essential. Also, an understanding of parameters previously viewed as second order is now critical for high-reliability designs. Deep sub-micron MOS technology has made it necessary to quantify a number of low-level device currents. Monitoring and control of MOS device off-state leakage currents (Id off ) is now important. Other areas of growing interest include gate oxide tunnelling currents, gate-induced drain leakage (GIDL), hot-carrier-induced gate currents and draininduced barrier leakage (DIBL). Further, additional metal layers in the process, which increase capacitance and limit operating speed, have resulted in more emphasis on low-level capacitance measurements. Both DC and CV measurements are necessary in assessing the performance and reliability of submicron devices. Figure 1 Cascade Microtech s Summit probe station TAP TECHNOLOGY 39

Figure 2 (right) Schematic of guarded MicroChamber Figure 3 (below) AttoGuard s fast recovery time Figure 4 (bottom) MicroChamber enclosure OXIDE RELIABILITY AND LEAKAGE CURRENT Insulating gate

Characterisation and evaluation of these ultra-thin gate oxides is important in ensuring the reliability and predicted lifetime-in-use of MOS VLSI technology.

2 Figure 2 (right) Schematic of guarded MicroChamber Figure 3 (below) AttoGuard s fast recovery time Figure 4 (bottom) MicroChamber enclosure OXIDE RELIABILITY AND LEAKAGE CURRENT Insulating gate oxides are necessarily very thin to control short-channel CMOS devices. Characterisation and evaluation of these ultra-thin gate oxides is important in ensuring the reliability and predicted lifetime-in-use of MOS VLSI technology. Two commonly used evaluation techniques are the voltage ramp (V RAMP ) test and the time-dependent dielectric breakdown (TDDB) test. In the V RAMP test, a voltage stress ramp is applied until the gate oxide reaches its catastrophic breakdown and at this point the current is recorded. In addition to the breakdown voltage (V BD ), the charge to breakdown (Q BD ) and/or the breakdown field (F BR ) is calculated. The breakdown voltage is recorded and the breakdown field is calculated at the critical breakdown voltage. The TDDB test uses a constant voltage to stress the gate oxide until the oxide ruptures, and the breakdown time is measured at the applied voltage. Using these techniques, the definition of an oxide failure is a large, fast and catastrophic increase in current at the critical breakdown point. Although these measurements are easy to make, these techniques may not account for low-field degradation that can occur following high-field stress. For example, in flash EEPROM applications, leakage current causes charge loss and memory failure. Stress-induced leakage current (SILC) becomes the dominating factor and ultimately limits the reduction of oxide thickness. From a device application standpoint, it is important to determine the onset of critical sub-breakdown oxide leakage. Applying a high electric field to the gate dielectric produces a stressinduced leakage current. Low-field leakage may be detected by applying a lower voltage but it may only begin to reveal itself after repeated stress tests. In addition to flash memory, other memory devices, such as DRAMs, cannot tolerate much leakage, owing to their extensively parallel architecture. These devices fail when gate oxides become sufficiently leaky and it is important to be able to measure this leakage. DRAINF LEAKAGE CURRENT Reduced device scaling has yielded integrated circuits with millions of transistors. In the quest for faster switching speeds and lower power dissipation, drain voltage (V ds ) and threshold voltage (V th ) have dropped. But a reduction in V th causes the standby current to increase. Such devices depend critically on characterisation and on the control of the off-state drain leakage (Id off ). With shorter channels and falling threshold voltage, this has become more of a challenge. Gateinduced drain current or leakage can also be induced in the high-field area where the gate overlaps the drain. This is greatest when the device is off, at which time the field is the highest. The larger the area of gatedrain overlap, the higher the current. 40 TAP TECHNOLOGY

LOW-CAPACITANCE REQUIREMENTS Characterisation of sub-micron devices requires measurement of low capacitance values also. Often, oxide thickness is determined by measuring a test oxide capacitor.

3 LOW-CAPACITANCE REQUIREMENTS Characterisation of sub-micron devices requires measurement of low capacitance values also. Often, oxide thickness is determined by measuring a test oxide capacitor. Small capacitor areas are desired to preserve area on the wafer, resulting in small capacitance values. As MOS gate lengths decrease, the gate overlap and fringing capacitance increases in importance relative to the bulk drain and bulk source capacitance. These values could be as small as several tens of femtofarads (ff), which also need to be measured at wafer level. The increasing number of metal layers is making precision capacitance measurements much more important. MAKING LOW-LEVEL PARAMETRIC MEASUREMENTS Modern analytical parametric test equipment, such as the HP 4156B Semiconductor Parameter Analyzer and the Keithley 4200 Semiconductor Characterization System, allows analysis of currents below 1 fa. However, actually making these low-level, high-resolution measurements on a wafer is impossible without proper attention to the entire measurement path. Wafer probers, such as Cascade Microtech s Summit (Figure 1), are designed to take advantage of the performance of modern parametric instruments. These probers incorporate a patented MicroChamber and a specially guarded low-capacitance chuck that allow users to make measurements at the full resolution of the instrument. One of the problems is that the capacitance or dielectric absorption in the measurement path is a major roadblock to improved low-level testing. Current is required to charge this stray capacitance to the voltage being set, and this causes an error current that limits the measurement accuracy. Of course, a wait time can be allowed, but settling time is critical when a swept or pulsed bias voltage is used prior to a leakage measurement. If insufficient settling time is used, the measurement may be swamped by capacitive charges in the measurement path. Reducing system capacitance is necessary in order to take advantage of the low levels measurable with today s parameter analysers. These analysers incorporate a guard amplifier and a triaxial output with a guard shield. By forcing the guard shield to track the voltage on the centre conductor, these analysers reduce the capacitive effects between the two. This same concept must be extended throughout the entire measurement environment, including guarded probes and a guarded wafer chuck (Figure 2). Another difficulty in detecting changes in oxide leakage at very low current levels is dealing with electromagnetic and electrostatic noise, which is picked up in the measurement area. This is especially important where a voltage source may be used on the top side, but substrate current is measured through the chuck. Unshielded and unguarded chucks are not suitable for measuring low leakage currents in gate oxides. ACHIEVING HIGH-ACCURACY CAPACITANCE MEASUREMENTS With smaller device geometries, the characterisation of extrinsic device capacitance has taken on increased significance. Accurate on-wafer measurement techniques are critical for accurate capacitance characterisations. While the gate capacitance of sub-micron devices may be as low as several tens of femtofarads, the parasitic capacitance of test device pads is typically several hundred ff. Further, undesired internal capacitance paths may exist in the test device. And finally, the residual capacitance could be 100 pf or more in a conventional probe station, probes and cables. So how can one reduce the residual capacitance in the system? LCR meters function in such a way that they ignore stray capacitance to their own shield or common return. The key to reducing system residual capacitance lies in using the LCR-meter common return path or shield wisely. Four areas deserve special attention: Figure 5 HP instruments, switch matrix and Cascade Microtech prober TAP TECHNOLOGY 41

4 guarded probes low-noise triaxial cables a low-capacitance chuck a small environmental enclosure. A coaxial probe, with the metal body shield reaching nearly to the probe tip, is the key to reducing top-side capacitance. These probes allow an outer-conductor connection to the LCR meter shield or common, which is connected to the probe body, thereby greatly reducing top-side stray and interprobe capacitance. By using low-noise triaxial cables, the probe shielding reaches as far as the probe tip, and stray capacitance paths are greatly reduced. Guarded chucks allow the LCR meter shield to be applied below the wafer chuck, thereby reducing residual substrate capacitance. If the requirement is to eliminate substrate capacitance itself, then the wafer chuck can be directly connected to the LCR meter common/shield. The residual capacitance of Cascade s AttoGuard chuck is 1 pf, allowing a very fast recovery time from a 100 volt step (see Figure 3). Lastly, a small, localised metal shield enclosure, such as the MicroChamber on a Cascade Microtech probe station (Figure 4), can be connected to the LCR meter common. This eliminates all potential stray capacitances to other prober features and results in reliable CV measurements unhindered by residual system capacitance. These localised enclosures, which enclose only the measurement area, offer additional benefits: the probes, wafer stage and microscope can be adjusted from outside while maintaining a fully shielded environment. MULTI-PIN PROBE CARD MEASUREMENTS The need to contact many points on the wafer at once often arises. Good parametric performance is just as important when using a multi-pin probe card as when using individual probes. The addition of the 48-channel HP E5250A low-leakage switch matrix to the HP 4156C Precision Semiconductor Parameter Analyzer (see Figure 5) provides an instrumentation solution capable of making low-level measurements. A typical probe card, made from a high-leakage material such as glass epoxy or FR4, cannot provide the required performance to match the instrumentation. The only solution to this problem is a low-leakage, low-capacitance system similar to that developed by Cascade Microtech (Figure 6). In this system, a probe needle mounted on a ceramic blade is connected to a triaxial cable to provide high isolation and low capacitance. A metal guard is plated on the reverse side of the blade to provide crosstalk isolation from adjacent signals. This guard is connected to the triaxial-cable guard through the circuit board. This design completely eliminates the effects of leakage through the board material itself because the blade sits on top of a driven guard. The triaxial shield layer terminates at the probe system s metal shield enclosure. Up to 48 probes can be mounted in a standard 4.5 inch rectangular card format, and the complete assembly is further shielded by a metal box to protect the integrity of the signal. With this low-leakage probe card system, measurements can be made with the same precision as with individual probe needles. Leakage is less than 5 fa and the probe card does not degrade the performance of the Figure 6 Low-leakage probe card 42 TAP TECHNOLOGY

5 parametric analyser. The probe tip capacitance is ultralow, with reduced instrument settling time and accurate low-capacitance measurement. Typical measurements such as the MOSFET transfer characteristics can be performed down to femtoamp levels. SUMMARY When probing sub-micron CMOS geometries, understanding the effects of capacitance and leakage in the measuring circuit is critical for making low-current and low-capacitance measurements. Armed with the right knowledge and the correct equipment, current measurements down to the femtoamp level are possible even when using multi-pin probe cards. ABOUT THE AUTHOR Larry Dangremond has spent over twenty years in the semiconductor test and measurement industry. Since 1993, he has been the Marketing Manager of the Probing Systems Business Unit at Cascade Microtech, based in Beaverton, OR, USA. Prior to joining Cascade, he was a product marketing manager for benchtop semiconductor test instruments at Tektronix Inc. IF YOU HAVE ANY ENQUIRIES REGARDING THE CONTENT OF THIS ARTICLE, PLEASE CONTACT: Irene Stewart Cascade Microtech Europe 3 Somerville Court Banbury Business Park Adderbury Oxon. OX17 3SN UK Tel: +44 (0) Fax: +44 (0) irenes@cmicro.com TAP TECHNOLOGY 43

MOSFET: Introduction

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