EPC2107 Enhancement-Mode GaN Power Transistor Half-Bridge with Integrated Synchronous Bootstrap

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1 Enhancement-Mode GaN Power Transistor Half-Bridge with Integrated Synchronous Bootstrap V DSS, V R DS(on), 9 mω I D,.7 A EFFICIENT POWER CONVERSION HAL Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 6 years. GaN s exceptionally high electron mobility and low temperature coefficient allows very low R DS(on), while its lateral device structure and majority carrier diode provide exceptionally low Q G and zero Q RR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. Maximum Ratings DEVICE PARAMETER VALUE UNIT Q & Q Q V DS Drain-to-Source Voltage (up to, 5 ms pulses at 5 C) Drain-to-Source Voltage (Continuous) Continuous (T A = 5 C, R θja = 6 C/W).7 I D Pulsed (5 C, T PULSE = µs).8 V GS Gate-to-Source Voltage Gate-to-Source Voltage 6 T J Operating Temperature to 5 T STG Storage Temperature to 5 V DS Drain-to-Source Voltage (up to, 5 ms pulses at 5 C) Drain-to-Source Voltage (Continuous) Continuous (T A = 5 C, R θja = C/W).5 I D Pulsed (5 C, T PULSE = µs).5 V GS Operating Temperature to 5 Gate-to-Source Voltage 6 T J Storage Temperature to 5 T STG Storage Temperature to 5 V A V C V A V C egan ICs are supplied only in passivated die form with solder bumps Die Size:.5 mm x.5 mm Applications High Frequency DC-DC Conversion Class-D Audio Wireless Power (Highly Resonant and Inductive) Benefits Ultra High Efficiency Ultra Low RDS(on) Ultra Low QG Ultra Small Footprint D BTST G upper Positive 6 7 Thermal Characteristics PARAMETER TYP UNIT R JC Thermal Resistance, Junction-to-Case 6 R JB Thermal Resistance, Junction-to-Board C/W S BTST 9 D Grev Q Q 5 Out Out R JA Thermal Resistance, Junction-to-Ambient (Note ) 8 Note : R θja is determined with the device mounted on one square inch of copper pad, single layer oz copper on FR board. See for details G BTST Q G lower 8 Ground Detailed Schematic EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8

2 Static Characteristics (T J = 5 C unless otherwise stated) DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BV DSS Drain-to-Source Voltage V GS = V, I D =. ma V Q & Q Q I DSS Drain-Source Leakage V DS = 8 V, V GS = V.5.5 ma I GSS Gate-to-Source Forward Leakage V GS = 5 V. ma Gate-to-Source Reverse Leakage V GS = - V.5.5 ma V GS(TH) Gate Threshold Voltage V DS = V GS, I D =. ma V R DS(on) Drain-Source On Resistance V GS = 5 V, I D = A 5 9 mω V SD Source-Drain Forward Voltage I S =.5 A, V GS = V.5 V BV DSS Drain-to-Source Voltage V GS = V, I D =.5 ma V I DSS Drain-Source Leakage V DS = 8 V, V GS = V.. ma I GSS Gate-to-Source Forward Leakage V GS = 5 V. ma V F Source-Gate Forward Voltage I F =. ma, V DS = V.7 V V GS(TH) Gate Threshold Voltage V DS = V GS, I D =. ma V R DS(on) Drain-Source On Resistance V GS = 5 V, I D =.5 A mω V SD Source-Drain Forward Voltage I S =. A, V GS = V.9 V Dynamic Characteristics (T J = 5 C unless otherwise stated) DEVICE PARAMETER TEST CONDITIONS MIN TYP MAX UNIT C ISS Input Capacitance 5 C RSS Reverse Transfer Capacitance V DS = 5 V, V GS = V. C OSS Output Capacitance 9. pf C OSS(ER) Effective Output Capacitance, Energy Related (Note ) V DS = to 5 V, V GS = V C OSS(TR) Effective Output Capacitance, Time Related (Note ) 8 Q Q Q R G Gate Resistance.7 Ω Q G Total Gate Charge V DS = 5 V, V GS = 5 V, I D = A 9 Q GS Gate to Source Charge 77 Q GD Gate to Drain Charge V DS = 5 V, I D = A Q G(TH) Gate Charge at Threshold 9 pc Q OSS Output Charge V DS = 5 V, V GS = V 9 5 Q RR Source-Drain Recovery Charge C ISS Input Capacitance 5 C RSS Reverse Transfer Capacitance V DS = 5 V, V GS = V. C OSS Output Capacitance pf C OSS(ER) Effective Output Capacitance, Energy Related (Note ) 9 V DS = to 5 V, V GS = V C OSS(TR) Effective Output Capacitance, Time Related (Note ) 5 R G Gate Resistance.7 Ω Q G Total Gate Charge V DS = 5 V, V GS = 5 V, I D = A 9 Q GS Gate to Source Charge 77 Q GD Gate to Drain Charge V DS = 5 V, I D = A Q G(TH) Gate Charge at Threshold 9 pc Q OSS Output Charge V DS = 5 V, V GS = V Q RR Source-Drain Recovery Charge C ISS Input Capacitance 7 8. C RSS Reverse Transfer Capacitance V DS = 5 V, V GS = V. C OSS Output Capacitance.6. pf C OSS(ER) Effective Output Capacitance, Energy Related (Note ). V DS = to 5 V, V GS = V C OSS(TR) Effective Output Capacitance, Time Related (Note ).7 R G Gate Resistance.8 Ω Q G Total Gate Charge V DS = 5 V, V GS = 5 V, I D =.5 A 55 Q GS Gate to Source Charge Q GD Gate to Drain Charge V DS = 5 V, I D =.5 A Q G(TH) Gate Charge at Threshold 8 pc Q OSS Output Charge V DS = 5 V, V GS = V Q RR Source-Drain Recovery Charge Note : C OSS(ER) is a fixed capacitance that gives the same stored energy as C OSS while V DS is rising from to 5% BV DSS. Note : C OSS(ER) is a fixed capacitance that gives the same charging time as C OSS while V DS is rising from to 5% BV DSS. EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8

3 Figure a (Q & Q): Typical Output Characteristics at 5 C.5 Figure b (Q): Typical Output Characteristics at 5 C V GS = 5 V I D Drain Current (A) V GS = V V GS = V V GS = V I D Drain Current (A).... V GS = 5 V V GS = V V GS = V V GS = V Figure a (Q & Q): Transfer Characteristics.5 Figure b (Q): Transfer Characteristics 5 C 5 C. 5 C 5 C I D Drain Current (A) V DS = V I D Drain Current (A).. V DS = V R DS(on) Drain-to-Source Resistance (mω) Figure a (Q & Q): R DS(on) vs. V GS for Various Drain Currents I D =. A I D =.5 A I D =. A I D =.5 A R DS(on) Drain-to-Source Resistance (mω) 8 6 Figure b (Q): R DS(on) vs. V GS for Various Drain Currents I D =.5 A I D =. A I D =.5 A I D =. A EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8

4 Figure a (Q & Q): R DS(on) vs. V GS for Various Temperatures 8 Figure b (Q): R DS(on) vs. V GS for Various Temperatures R DS(on) Drain-to-Source Resistance (mω) C 5 C I D = A R DS(on) Drain-to-Source Resistance (mω) 6 5 C 5 C I D =.5 A Figure 5a (Q): Capacitance (Linear Scale) Figure 5b (Q): Capacitance (Log Scale) Figure 5c (Q): Capacitance (Linear Scale) Figure 5d (Q): Capacitance (Log Scale) EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8

5 8 Figure 5e (Q): Capacitance (Linear Scale) Figure 5f (Q): Capacitance (Log Scale) Figure 6a: (Q): Output Output Charge Charge and Cand OSS Stored C OSS Stored Energy Energy 5. Figure 6a: 6b (Q): Output Output Charge Charge and Cand OSS Stored C OSS Stored Energy Energy 7 Q OSS Output Charge (nc) E OSS C OSS Stored Energy (μj) Q OSS Output Charge (nc) E OSS C OSS Stored Energy (μj) Figure 6a: 6c (Q): Output Output Charge Charge and and C OSS Stored C OSS Stored Energy Energy Q OSS Output Charge (nc) E OSS C OSS Stored Energy (μj). 6 8 EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8 5

6 5 Figure 7a (Q & Q): Gate Charge 5 Figure 7b (Q): Gate Charge I D = A V DS = 5 V I D =.5 A V DS = 5 V 5 5 Q G Gate Charge (pc) 5 Q G Gate Charge (pc) Figure 8a (Q & Q): Reverse Drain-Source Characteristics.5 Figure 8b (Q): Reverse Drain-Source Characteristics I SD Source-to-Drain Current (A) 5 C 5 C V DS GS = V I SD Source-to-Drain Current (A) C 5 C V DS GS = V V SD Source-to-Drain Voltage (V) V SD Source-to-Drain Voltage (V). Figure 9a (Q & Q): Normalized On-State Resistance vs. Temperature. Figure 9b (Q): Normalized On-State Resistance vs. Temperature Normalized On-State Resistance R DS(on) I D = A V GS = 5 V Normalized On-State Resistance R DS(on) I D =.5 A V GS = 5 V T J Junction Temperature ( C) T J Junction Temperature ( C) EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8 6

7 .. Figure a (Q & Q): Normalized Threshold Voltage vs. Temperature.. Figure b (Q): Normalized Threshold Voltage vs. Temperature Normalized Threshold Voltage I D =. ma Normalized Threshold Voltage I D =. ma T J Junction Temperature ( C) T J Junction Temperature ( C) Figure a Transient Thermal Response Curves ZθJB, Normalized Thermal Impedance Duty Cycle: Single Pulse (Q/Q/Q) Junction-to-Board t p, Rectangular Pulse Duration, seconds P DM t t Notes: Duty Factor: Single D = Pulse t /t Peak T J = P DM x Z θjb x R θjb + T B Figure b Transient Thermal Response Curves ZθJC, Normalized Thermal Impedance Duty Cycle: (Q/Q/Q) Junction-to-Case t p, Rectangular Pulse Duration, seconds P DM t. Single Pulse Notes: Duty Factor: D = t /t Peak T J = P DM x Z θjc x R θjc + T C t EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8 7

8 I D Drain Current (A) Figure (Q & Q): Safe Operating Area Limited by R DS(on) Pulse Width ms ms µs ms 5 µs µs 5 µs.. V DS Drain-Source Voltage (V) T J = Max Rated, T C = +5 C, Single Pulse I G Gate Current (ma) Figure (Q): Gate-Source Characteristics 5 C 5 C Figure : Typical Application Circuit 5 V Q Q Level Shift Output C Bus Q Gate Driver EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8 8

9 TAPE AND REEL CONFIGURATION mm pitch, 8mm wide tape on 7 reel d e f g Loaded Tape Feed Direction 7 reel a b c 7 YYYY ZZZZ Die orientation dot Pin is under this corner (note ) Dimension (mm) target min max a b c (see note) d..9. e..9. f (see note) g Die is placed into pocket solder bump side down (face side down) Note : MSL (moisture sensitivity level ) classified according to IPC/JEDEC industry standard. Note : Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole. DIE MARKINGS Die orientation dot Pin is under this corner 7 YYYY Part Number Part # Marking Line Laser Markings Lot_Date Code Marking Line Lot_Date Code Marking Line ZZZZ 7 YYYY ZZZZ EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8 9

10 DIE OUTLINE Solder Bump View A Micrometers B d c c d c c Pad is Gate (Q) Pad is Gate (Q) Pad is Gate (Q) Pad 7 is Drain (Q) Pad 5 is Drain (Q) Pad 6 is Drain (Q) Pad is Source (Q) Pad 8 is Source (Q) Pad 9 is Source (Q) DIM MIN Nominal MAX A 5 8 B 5 8 c d 5 e Side View (65) 85 Max Seating Plane 65 +/- 7 RECOMMENDED LAND PATTERN (measurements in µm) + / - (*) X9 5 7 The land pattern is solder mask defined Solder mask is μm smaller per side than bump * minimum RECOMMENDED STENCIL DRAWING (measurements in µm) 5 5 R6 Recommended stencil should be mil ( µm) thick, must be laser cut, openings per drawing Intended for use with SAC5 Type solder, reference 88.5% metals content. Additional assembly resources available at Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. egan is a registered trademark of Efficient Power Conversion Corporation. EPC Patent Listing: epc-co.com/epc/aboutepc/patents.aspx Information subject to change without notice. Revised June, 8 EPC EFFICIENT POWER CONVERSION CORPORATION COPYRIGHT 8