DATASHEET CD4073BMS, CD4081BMS, CD4082BMS. Features. Pinout. Description. CMOS AND Gate. FN3324 Rev 1.00 Page 1 of 11. October FN3324 Rev 1.

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1 TST 0MS, 0MS, 0MS MOS N ate eatures igh-voltage Tyes (0V Ratig) 0MS Trile -Iut N ate (No loger available or suorted) 0MS Quad -Iut N ate 0MS ual -Iut N ate (No loger available or suorted) Medium Seed Oeratio: - tpl, tpl = 0s (ty) at = V 0% Tested for Quiescet urret at 0V Maximum Iut urret of at V Over ull Package Temerature Rage; 0 at V ad + o Noise Margi (Over ull Package Temerature Rage): - V at = V - V at = V -.V at = V Stadardized Symmetrical Outut haracteristics V, V ad V Parametric Ratigs Meets ll Requiremets of Tetative Stadard No., Stadard Secificatios for escritio of Series MOS evices escritio 0MS, 0MS ad 0MS N gates rovide the system desiger with direct imlemetatio of the N fuctio ad sulemet the existig family of MOS gates. The 0MS, 0MS ad 0MS are sulied i these lead outlie ackages: raze Seal IP Q rit Seal IP eramic latack W 0, 0 0 Piout K = 0MS TOP VIW 0MS TOP VIW 0MS TOP VIW I L = I = NO LONR VILL OR SUPPORT = K = = N M = L = NO LONR VILL OR SUPPORT N Rev.00 K = N N = NO ONNTION N Rev.00 Page of

2 0MS, 0MS, 0MS uctioal iagram I K L 0MS K L M 0MS K 0MS N Rev.00 Page of

3 0MS, 0MS, 0MS bsolute Maximum Ratigs Suly Voltage Rage, () V to +0V (Voltage Refereced to Termials) Iut Voltage Rage, ll Iuts V to +0.V Iut urret, y Oe Iut m Oeratig Temerature Rage o to + o Package Tyes,, K, Storage Temerature Rage (TST) o to +0 o Lead Temerature (urig Solderig) o t istace / / Ich (.mm 0.mm) from case for s Maximum Reliability Iformatio Thermal Resistace ja jc eramic IP ad RIT Package o /W 0 o /W latack Package o /W 0 o /W Maximum Package Power issiatio (P) at + o or T = - o to +0 o (Package Tye,, K) mW or T = +0 o to + o (Package Tye,, K)..... erate Liearity at mw/ o to 00mW evice issiatio er Outut Trasistor mW or T = ull Package Temerature Rage (ll Package Tyes) uctio Temerature o TL. LTRIL PRORMN RTRISTIS ROUP LIMITS PRMTR SYMOL ONITIONS (NOT ) SUROUPS TMPRTUR MIN MX UNITS Suly urret I = 0V, VIN = or N + o -. + o - 0 = V, VIN = or N - o -. Iut Leakage urret IIL VIN = or N = 0 + o o = V - o -0 - Iut Leakage urret II VIN = or N = 0 + o o - 00 = V - o - 0 Outut Voltage VOL = V, No Load,, + o, + o, - o - 0 mv Outut Voltage VO = V, No Load (Note ),, + o, + o, - o. - V Outut urret (Sik) IOL = V, VOUT = 0.V + o 0. - m Outut urret (Sik) IOL = V, VOUT = 0.V + o. - m Outut urret (Sik) IOL = V, VOUT =.V + o. - m Outut urret (Source) IO = V, VOUT =.V + o m Outut urret (Source) IO = V, VOUT =.V + o - -. m Outut urret (Source) IO = V, VOUT =.V + o - -. m Outut urret (Source) IO = V, VOUT =.V + o - -. m N Threshold Voltage VNT = V, ISS = - + o V P Threshold Voltage VPT = 0V, I = + o 0.. V uctioal =.V, VIN = or N + o VO > VOL < V = 0V, VIN = or N + o / / = V, VIN = or N + o = V, VIN = or N - o Iut Voltage Low VIL = V, VO >.V, VOL < 0.V,, + o, + o, - o -. V (Note ) Iut Voltage igh (Note ) VI = V, VO >.V, VOL < 0.V,, + o, + o, - o. - V Iut Voltage Low (Note ) Iut Voltage igh (Note ) NOTS: VIL VI = V, VO >.V, VOL <.V = V, VO >.V, VOL <.V. ll voltages refereced to device N, 0% testig beig imlemeted.. o/no o test with limits alied to iuts.,, + o, + o, - o - V,, + o, + o, - o - V. or accuracy, voltage is measured differetially to. Limit is 0.00V max. N Rev.00 Page of

4 0MS, 0MS, 0MS TL. LTRIL PRORMN RTRISTIS ROUP LIMITS PRMTR SYMOL ONITIONS (NOTS, ) SUROUPS TMPRTUR MIN MX UNITS Proagatio elay TPL = V, VIN = or N + o - 0 s TPL, + o, - o - s Trasitio Time TTL = V, VIN = or N + o - 00 s TTL, + o, - o - 0 s NOTS:. L = 0, RL = 00K, Iut TR, T < 0s.. - o ad + o limits guarateed, 0% testig beig imlemeted. TL. LTRIL PRORMN RTRISTIS LIMITS PRMTR SYMOL ONITIONS NOTS TMPRTUR MIN MX UNITS Suly urret I = V, VIN = or N, - o, + o -. + o -. = V, VIN = or N, - o, + o -. + o - = V, VIN = or N, - o, + o -. + o - 0 Outut Voltage VOL = V, No Load, + o, + o, mv o Outut Voltage VOL = V, No Load, + o, + o, - o Outut Voltage VO = V, No Load, + o, + o, - o Outut Voltage VO = V, No Load, + o, + o, - o - 0 mv. - V. - V Outut urret (Sik) IOL = V, VOUT = 0.V, + o 0. - m - o 0. - m Outut urret (Sik) IOL = V, VOUT = 0.V, + o 0. - m - o. - m Outut urret (Sik) IOL = V, VOUT =.V, + o. - m - o. - m Outut urret (Source) IO = V, VOUT =.V, + o m - o m Outut urret (Source) IO = V, VOUT =.V, + o - -. m - o m Outut urret (Source) IO = V, VOUT =.V, + o m - o - -. m Outut urret (Source) IO =V, VOUT =.V, + o - -. m - o - -. m Iut Voltage Low VIL = V, VO > V, VOL < V, + o, + o, - o - V Iut Voltage igh VI = V, VO > V, VOL < V, + o, + o, - o Proagatio elay TPL TPL - V = V,, + o - 0 s = V,, + o - 0 s N Rev.00 Page of

5 0MS, 0MS, 0MS TL. LTRIL PRORMN RTRISTIS (otiued) PRMTR SYMOL ONITIONS NOTS TMPRTUR Trasitio Time TTL = V,, + o - 0 s TTL = V,, + o - 0 s Iut aacitace IN y Iut, + o -. NOTS:. ll voltages refereced to device N.. The arameters listed o Table are cotrolled via desig or rocess ad are ot directly tested. These arameters are characterized o iitial desig release ad uo desig chages which would affect these characteristics.. L = 0, RL = 00K, Iut TR, T < 0s. MIN LIMITS MX UNITS TL. POST IRRITION LTRIL PRORMN RTRISTIS LIMITS PRMTR SYMOL ONITIONS NOTS TMPRTUR MIN MX UNITS Suly urret I = 0V, VIN = or N, + o -. N Threshold Voltage VNT = V, ISS = -, + o V N Threshold Voltage VTN = V, ISS = -, + o - V elta P Threshold Voltage VTP = 0V, I =, + o 0.. V P Threshold Voltage VTP = 0V, I =, + o - V elta uctioal = V, VIN = or N = V, VIN = or N + o VO > / Proagatio elay Time TPL TPL NOTS:. ll voltages refereced to device N.. L = 0, RL = 00K, Iut TR, T < 0s. VOL < / = V,,, + o -. x + o Limit. See Table for + o limit.. Read ad Record V s TL. URN-IN N LI TST LT PRMTRS + O PRMTR SYMOL LT LIMIT Suly urret - SSI I 0. Outut urret (Sik) IOL 0% x Pre-Test Readig Outut urret (Source) IO 0% x Pre-Test Readig TL. PPLIL SUROUPS ONORMN ROUP MIL-ST- MTO ROUP SUROUPS R N ROR Iitial Test (Pre ur-i) 0% 00,, I, IOL, IO Iterim Test (Post ur-i) 0% 00,, I, IOL, IO Iterim Test (Post ur-i) 0% 00,, I, IOL, IO P (Note ) 0% 00,,, eltas Iterim Test (Post ur-i) 0% 00,, I, IOL, IO P (Note ) 0% 00,,, eltas ial Test 0% 00,,,,, rou Samle 00,,,,,,,, N Rev.00 Page of

6 0MS, 0MS, 0MS ONORMN ROUP TL. PPLIL SUROUPS (otiued) MIL-ST- MTO ROUP SUROUPS R N ROR rou Subgrou - Samle 00,,,,,,,,, eltas Subgrous,,,,, Subgrou - Samle 00,, rou Samle 00,,,,, Subgrous, NOT:. % Parameteric, % uctioal; umulative for Static ad. TL. TOTL OS IRRITION MIL-ST- TST R N ROR ONORMN ROUPS MTO PR-IRR POST-IRR PR-IRR POST-IRR rou Subgrou 00,, Table, Table TL. URN-IN N IRRITION TST ONNTIONS UNTION OPN ROUN V -0.V PRT NUMR 0MS Static ur-i,, -,,, - Note Static ur-i Note yamic ur- I Note Irradiatio Note PRT NUMR Static ur-i Note Static ur-i Note yamic ur- I Note Irradiatio Note PRT NUMR Static ur-i Note Static ur-i Note yamic ur- I Note Irradiatio Note,, -,, - -,,,,, -,, -,, - 0MS,,,,, -,,,,,,,,,,, - -,,,,,,,,,,,,,,,,,,, - 0MS,,, -,, -,,, -, -,,, -, -,,, -, -, OSILLTOR 0kz kz NOT:. ach i excet ad N will have a series resistor of K %, = V 0.V. ach i excet ad N will have a series resistor of K %; rou, Subgrou, samle size is dice/wafer, 0 failures, = V 0.V N Rev.00 Page of

7 0MS, 0MS, 0MS (, ) (, ) (, ) (, ) LL INPUTS PROTT Y MOS PROTTION NTWORK IUR. SMTI IRM OR 0MS ( O INTIL TS) (, ) (, ) (, ) (, ) IUR. LOI IRM OR 0MS ( O INTIL TS) (,, ) (,, ) (,, ) LL INPUTS PROTT Y MOS PROTTION NTWORK IUR. SMTI IRM OR 0MS ( O INTIL TS) N Rev.00 Page of

8 0MS, 0MS, 0MS (,, ) (,, ) (,, ) IUR. LOI IRM OR 0MS ( O INTIL TS) () () () () LL INPUTS PROTT Y MOS PROTTION NTWORK IUR. SMTI IRM OR 0MS ( O INTIL TS) () () () () () IUR. LOI IRM OR 0MS ( O INTIL TS) N Rev.00 Page of

9 0MS, 0MS, 0MS Tyical Performace haracteristics OUTPUT VOLT (VO) (V) 0 MINT TMPRTUR (T ) = + o SUPPLY VOLT () = V V V PROPTION LY TIM (TPL, TL) (s) MINT TMPRTUR (T ) = + o SUPPLY VOLT () = V V V 0 0 INPUT VOLT (VIN) (V) IUR. TYPIL VOLT TRNSR RTRISTIS LO PITN (L) () IUR. TYPIL PROPTION LY TIM S UNTION O LO PITN OUTPUT LOW (SINK) URRNT (IOL) (m) 0 0 MINT TMPRTUR (T ) = + o T-TO-SOUR VOLT (VS) = V V V OUTPUT LOW (SINK) URRNT (IOL) (m) MINT TMPRTUR (T ) = + o T-TO-SOUR VOLT (VS) = V V V 0 RIN-TO-SOUR VOLT (VS) (V) IUR. TYPIL OUTPUT LOW (SINK) URRNT RTRISTIS 0 RIN-TO-SOUR VOLT (VS) (V) IUR. MINIMUM OUTPUT LOW (SINK) URRNT RTRISTIS RIN-TO-SOUR VOLT (VS) (V) MINT TMPRTUR (T ) = + o T-TO-SOUR VOLT (VS) = -V -V -V OUTPUT I (SOUR) URRNT (IO) (m) RIN-TO-SOUR VOLT (VS) (V) MINT TMPRTUR (T ) = + o T-TO-SOUR VOLT (VS) = -V -V -V OUTPUT I (SOUR) URRNT (IO) (m) IUR. TYPIL OUTPUT I (SOUR) URRNT RTRISTIS IUR. MINIMUM OUTPUT I (SOUR) URRNT RTRISTIS N Rev.00 Page of

10 0MS, 0MS, 0MS Tyical Performace haracteristics (otiued) TRNSITION TIM (ttl, ttl) (s) MINT TMPRTUR (T ) = + o SUPPLY VOLT () = V LO PITN (L) () V V IUR. TYPIL TRNSITION TIM S UNTION O LO PITN MINT TMPRTUR (T ) = + o SUPPLY VOLT () = V V V V L = 0 L = INPUT RQUNY (fi) (kz) IUR. TYPIL YNMI POWR ISSIPTIONPR T S UNTION O RQUNY POWR ISSIPTION PR T (P) ( W) hi imesios ad Pad Layouts 0MS 0MS N Rev.00 Page of

11 0MS, 0MS, 0MS hi imesios ad Pad Layouts 0MS imesios i aretheses are i millimeters ad are derived from the basic ich dimesios as idicated. rid graduatios are i mils ( - ich) MTLLIZTION: Thickess: kå kå, L. PSSIVTION:.kÅ -.kå, Silae ON PS: 0.00 iches X 0.00 iches MIN I TIKNSS: 0.0 iches iches oyright Itersil mericas LL -0. ll Rights Reserved. ll trademarks ad registered trademarks are the roerty of their resective owers. or additioal roducts, see Itersil roducts are maufactured, assembled ad tested utilizig ISO00 quality systems as oted i the quality certificatios foud at Itersil roducts are sold by descritio oly. Itersil may modify the circuit desig ad/or secificatios of roducts at ay time without otice, rovided that such modificatio does ot, i Itersil's sole judgmet, affect the form, fit or fuctio of the roduct. ccordigly, the reader is cautioed to verify that datasheets are curret before lacig orders. Iformatio furished by Itersil is believed to be accurate ad reliable. owever, o resosibility is assumed by Itersil or its subsidiaries for its use; or for ay ifrigemets of atets or other rights of third arties which may result from its use. No licese is grated by imlicatio or otherwise uder ay atet or atet rights of Itersil or its subsidiaries. or iformatio regardig Itersil ororatio ad its roducts, see N Rev.00 Page of

CD4071, CD4072 CD4075

CD4071, CD4072 CD4075 , MOS OR ate eatures igh-voltage Tyes (V Ratig) MS Quad -Iut OR ate MS ual -Iut OR ate MS Trile -Iut OR ate Medium Seed Oeratio: - tpl, tpl = s (ty) at V % Tested for Quiescet urret at V Maximum Iut urret