DATASHEET CD4049UBMS. Features. Applications. Pinout. Functional Diagram. Schematic. CMOS Hex Buffer/Converter. FN3315 Rev 1.

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1 DTSHEET CD09UBMS CMOS Hex Buffer/Converter The CD09UBMS is an inverting hex buffer and features logic level conversion using only one supply (voltage (VCC). The input signal high level (VIH) can exceed the VCC supply voltage when this device is used for logic level conversions. This device is intended for use as CMOS to DTL/TTL converters and can drive directly two DTL/TTL loads. (VCC = 5V, VOL 0.V, and IOL 3.3m. The CD09UBMS is designated as replacement for CD009UB. Because the CD09UBMS requires only one power supply, it is preferred over the CD009UB and CD0B and should be used in place of the CD009UB in all inverter, current driver, or logic level conversion applications. In these applications the CD09UBMS is pin compatible with the CD009UB, and can be substituted for this device in existing as well as in new designs. Terminal No. 1 is not connected internally on the CD09UBMS, therefore, connection to this terminal is of no consequence to circuit operation. For applications not requiring high sink current or voltage conversion, the CD09UB Hex Inverter is recommended. The CD09UBMS is supplied in these 1 lead outline packages: Braze Seal DIP Frit Seal DIP HS H1E Ceramic Flatpack H3X Features High Voltage Type (0V Rating) Inverting Type High Sink Current for Driving TTL Loads High-to-Low Level Logic Conversion 0% Tested for Quiescent Current at 0V FN3315 Rev 1.00 Maximum Input Current of 1m at 1V Over Full Package Temperature Range; 0n at 1V and +5 C 5V, V and 15V Parametric Ratings pplications CMOS to DTL/TTL Hex Converter CMOS Current Sink or Source Driver CMOS High-to-Low Logic Level Converter Pinout VCC G = H = B 1 3 CD09UBMS TOP VIEW NC L = F F NC Functional Diagram B I = C K = E E 3 G = C VSS 7 9 J = D D B C 5 7 H = B I = C Schematic VCC D 9 J = D VCC VSS NC = 13 NC = 1 1 E F K = E L = F IN R P N OUT VSS FIGURE 1. SCHEMTIC DIGRM, 1 OF IDENTICL FN3315 Rev 1.00 Page 1 of 11

2 Ordering Information PRT NUMBER PRT MRKING TEMP. RNGE ( C) PCKGE CD09UBDMSR Q 59R9 301VEC -55 to Ld SBDIP, Solder Seal D1.3 CD09UBKMSR Q 59R9 301VXC -55 to Ld Flatpack, Solder Seal K1. CD09UBKNSR Q 59R9 30VXC -55 to Ld Flatpack, Solder Seal K1. PKG. DWG. # FN3315 Rev 1.00 Page of 11

3 bsolute Maximum Ratings DC Supply Voltage Range, (V DD ) V to +0V (Voltage Referenced to VSS Terminals) Input Voltage Range, ll Inputs V to 0.5V DC Input Current, ny One Input m Operating Temperature Range C to +15 C Package Types D, F, K, H Storage Temperature Range (TSTG) C to +150 C Lead Temperature (During Soldering) C t Distance 1/1 1/3 Inch (1.59mm 0.79mm) from case for s Maximum Thermal Information Thermal Resistance (Typical) J ( C/W) JC ( C/W) Ceramic DIP and FRIT Package Flatpack Package Maximum Package Power Dissipation (PD) at +15 C For T = -55 C to +0 C (Package Type D, F, K) mW For T = +0 C to +15 C (Package Type D, F, K)..... Derate Linearity at 1mW/ C to 00mW Device Dissipation per Output Transistor mW For T = Full Package Temperature Range (ll Package Types) Junction Temperature C DC Electrical Specifications PRMETER SYMBOL CONDITIONS (Note 1) GROUP SUBGROUPS TEMP ( C) MX Supply Current I DD V DD = 0V, V IN = V DD or GND V DD = 1V, V IN = V DD or GND Input Leakage Current I IL V IN = V DD or GND V DD = n n V DD = 1V n Input Leakage Current I IH V IN = VDD or GND V DD = n n V DD = 1V n Output Voltage V OL15 V DD = 15V, No Load 1,, 3 +5, +15, mv Output Voltage V OH15 V DD = 15V, No Load (Note 3) 1,, 3 +5, +15, V (Sink) (Sink) (Sink) (Sink) (Source) (Source) (Source) (Source) I OL V DD =.5V, V OUT = 0.V m I OL5 V DD = 5V, V OUT = 0.V m I OL V DD = V, V OUT = 0.5V m I OL15 V DD = 15V, V OUT = 1.5V m I OH5 V DD = 5V, V OUT =.V m I OH5B V DD = 5V, V OUT =.5V m I OH V DD = V, V OUT = 9.5V m I OH15 V DD = 15V, V OUT = 13.5V m N Threshold Voltage V NTH V DD = V, I SS = V P Threshold Voltage V PTH V SS = 0V, I DD = V Functional F V DD =.V, V IN = V DD or GND 7 +5 VOH > VDD/ VOL < VDD/ V V DD = 0V, V IN = V DD or GND 7 +5 V DD = 1V, V IN = V DD or GND +15 V DD = 3V, V IN = V DD or GND B -55 FN3315 Rev 1.00 Page 3 of 11

4 DC Electrical Specifications PRMETER SYMBOL CONDITIONS (Note 1) GROUP SUBGROUPS TEMP ( C) MX Input Voltage Low (Note ) Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) V IL V DD = 5V, V OH >.5V, V OL < 0.5V 1,, 3 +5, +15, V V IH V DD = 5V, V OH >.5V, V OL < 0.5V 1,, 3 +5, +15, V V IL V DD = 15V, V OH > 13.5V, V OL < 1.5V 1,, 3 +5, +15, V V IH V DD = 15V, V OH > 13.5V, V OL < 1.5V 1,, 3 +5, +15, V 1. ll voltages referenced to device GND, 0% testing being implemented.. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to V DD. Limit is 0.050V max. C Electrical Specifications PRMETER SYMBOL CONDITIONS (Notes, 5) GROUP SUBGROUPS TEMP ( C) MX Propagation Delay t PHL V DD = 5V, V IN = V DD or GND ns, , ns Propagation Delay t PLH V DD = 5V, V IN = V DD or GND ns, , ns Transition Time t THL V DD = 5V, V IN = V DD or GND ns, , ns Transition Time t TLH V DD = 5V, V IN = V DD or GND ns, , ns. C L = 50pF, R L = 00k, Input t R, t F < 0ns C and +15 C limits guaranteed, 0% testing being implemented. Post Irradiation Electrical Performance Characteristics PRMETER SYMBOL CONDITIONS NOTES TEMP ( C) MX Supply Current I DD V DD = 5V, V IN = V DD or GND, 7-55, V DD = V, V IN = V DD or GND, 7-55, V DD = 15V, V IN = V DD or GND, 7-55, Output Voltage V OL V DD = 5V, No Load, 7 +5, +15, mv Output Voltage V OL V DD = V, No Load, 7 +5, +15, mv Output Voltage V OH V DD = 5V, No Load, 7 +5, +15, V Output Voltage V OH V DD = V, No Load, 7 +5, +15, V FN3315 Rev 1.00 Page of 11

5 Post Irradiation Electrical Performance Characteristics PRMETER SYMBOL CONDITIONS NOTES TEMP ( C) MX (Sink) I OL V DD =.5V, V OUT = 0.V, m m (Sink) I OL5 V DD = 5V, V OUT = 0.V, m m (Sink) I OL V DD = V, V OUT = 0.5V, m m (Sink) I OL15 V DD = 15V, V OUT = 1.5V, m m (Source) I OH5 V DD = 5V, V OUT =.V, m m (Source) I OH5B V DD = 5V, V OUT =.5V, m m (Source) I OH V DD = V, V OUT = 9.5V, m m (Source) I OH15 V DD =15V, V OUT = 13.5V, m m Input Voltage Low V IL V DD = V, V OH > 9V, V OL < 1V, 7 +5, +15, V Input Voltage High V IH V DD = V, V OH > 9V, V OL < 1V, 7 +5, +15, V Propagation Delay t PHL V IN = V, V DD = 5V, 7, ns V IN = V, V DD = V, 7, +5-0 ns Propagation Delay t PLH V IN = V, V DD = 5V, 7, ns V IN = V, V DD = V, 7, +5-5 ns Propagation Delay t PHL V IN = 15V, V DD = 5V, 7, +5-0 ns V IN = 15V, V DD = 15V, 7, ns Propagation Delay t PLH V IN = 15V, V DD = 5V, 7, ns V IN = 15V, V DD = 15V, 7, ns Transition Time t THL V DD = V, V IN = V DD OR GND, 7, +5-0 ns V DD = 15V, V IN = V DD OR GND, 7, ns Transition Time t TLH V DD = V, V IN = V DD OR GND, 7, +5-0 ns V DD = 15V, V IN = V DD OR GND, 7, +5-0 ns Input Capacitance C IN ny Input, pf. ll voltages referenced to device GND. 7. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.. C L = 50pF, R L = 00k, Input t R, t F < 0ns. FN3315 Rev 1.00 Page 5 of 11

6 Post Irradiation Electrical Performance Characteristics PRMETER SYMBOL CONDITIONS NOTES TEMP ( C) MX Supply Current I DD V DD = 0V, V IN = V DD or GND 9, N Threshold Voltage V NTH V DD = V, I SS = - 9, V N Threshold Voltage Delta V TND V DD = V, I SS = - 9, V P Threshold Voltage V TP V SS = 0V, I DD = 9, V P Threshold Voltage Delta V TPD V SS = 0V, I DD = 9, V Functional F VDD = 1V, VIN = VDD or GND 9 +5 VOH > VDD/ VOL < VDD/ V VDD = 3V, VIN = VDD or GND Propagation Delay Time t PHL V DD = 5V 9,, 11, x +5 t PLH Limit ns 9. ll voltages referenced to device GND.. C L = 50pF, R L = 00k, Input t R, t F < 0ns. 11. See Table for +5 C limit. 1. Read and Record TBLE 1. BURN-IN ND LIFE TEST DELT PRMETERS +5 C PRMETER SYMBOL DELT LIMIT Supply Current - MSI-1 I DD 0. (Sink) I OL5 0% x Pre-Test Reading (Source) I OH5 0% x Pre-Test Reading TBLE. PPLICBLE SUBGROUPS CONFORMNCE GROUP MIL-STD-3 METHOD GROUP SUBGROUPS RED ND RECORD Initial Test (Pre Burn-In) 0% 500 1, 7, 9 IDD, IOL5, IOH5 Interim Test 1 (Post Burn-In) 0% 500 1, 7, 9 IDD, IOL5, IOH5 Interim Test (Post Burn-In) 0% 500 1, 7, 9 IDD, IOL5, IOH5 PD (Note 13) 0% 500 1, 7, 9, Deltas Interim Test 3 (Post Burn-In) 0% 500 1, 7, 9 IDD, IOL5, IOH5 PD (Note 13) 0% 500 1, 7, 9, Deltas Final Test 0% 500, 3,, B,, 11 Group Sample ,, 3, 7,, B, 9,, 11 Group B Subgroup B-5 Sample ,, 3, 7,, B, 9,, 11, Deltas Subgroups 1,, 3, 9,, 11 Subgroup B- Sample , 7, 9 Group D Sample ,, 3,, B, 9 Subgroups 1, % Parameteric, 3% Functional; Cumulative for Static 1 and. FN3315 Rev 1.00 Page of 11

7 TBLE 3. TOTL DOSE IRRDITION CONFORMNCE GROUPS MIL-STD-3 METHOD TEST RED ND RECORD PRE-IRRD POST-IRRD PRE-IRRD POST-IRRD Group E Subgroup , 7, 9 Table 1, 9 Table TBLE. BURN-IN ND IRRDITION TEST CONNECTIONS OSCILLTOR FUNCTION OPEN GROUND VDD 9V -0.5V Static Burn-In 1 (Note 1),,,, 1, 13, 15 3, 5, 7-9, , 1 Static Burn-In (Note 1),,,, 1, 13, 15 1, 3, 5, 7, 9, 11, 1, 1 50kHz 5kHz Dynamic Burn-In (Note 1) 13 1, 1,,,, 1, 15 3, 5, 7, 9, 11, 1 Irradiation (Note 15),,,, 1, 13, 15, 1 1, 3, 5, 7, 9, 11, 1 1. Each pin except pin 1, pin 1, and GND will have a series resistor of k 5%, V DD = 1V 0.5V 15. Each pin except pin 1, pin 1, and GND will have a series resistor of 7k 5%; Group E, Subgroup, sample size is dice/wafer, 0 failures, V DD = V 0.5V 1. Each pin except pin 1, pin 1, and GND will have a series resistor of.75k 5%, V DD = 1V 0.5V Typical Performance Characteristics OUTPUT VOLTGE (V O ) (V) 5 3 MBIENT TEMPERTURE (T ) = +5 C SUPPLY VOLTGE (V CC ) = 5V IMUM MXIMUM OUTPUT LOW (SINK) CURRENT (I OL ) (m) MBIENT TEMPERTURE (T ) = +5 C 15V V GTE-TO-SOURCE VOLTGE (V GS ) = 5V INPUT VOLTGE (VI) (V) FIGURE. IMUM ND MXIMUM VOLTGE TRNSFER CHRCTERISTICS DRIN-TO-SOURCE VOLTGE (V DS ) (V) FIGURE 3. TYPICL OUTPUT LOW (SINK) CURRENT CHRCTERISTICS FN3315 Rev 1.00 Page 7 of 11

8 Typical Performance Characteristics (Continued) DRIN-TO-SOURCE VOLTGE (V DS ) (V) OUTPUT LOW (SINK) CURRENT (I OL ) (m) MBIENT TEMPERTURE (T ) = +5 C 15V V GTE-TO-SOURCE VOLTGE (V GS ) = 5V MBIENT TEMPERTURE (T ) = +5 C GTE-TO-SOURCE VOLTGE (V GS ) = 5V -V -15V OUTPUT HIGH (SINK) CURRENT (I OH ) (m) DRIN-TO-SOURCE VOLTGE (V DS ) (V) FIGURE. IMUM OUTPUT LOW (SINK) CURRENT DRIN CHRCTERISTICS FIGURE 5. TYPICL OUTPUT HIGH (SOURCE) CURRENT CHRCTERISTICS - DRIN-TO-SOURCE VOLTGE (V DS ) (V) MBIENT TEMPERTURE (T ) = +5 C GTE-TO-SOURCE VOLTGE (V GS ) = 5V -V -15V OUTPUT HIGH (SINK) CURRENT (I OH ) (m) OUTPUT VOLTGE (V O ) (V) SUPPLY VOLTGE (V CC ) = V MBIENT TEMPERTURE (T ) = -55 C +15 C V CC = 5V -55 C +15 C INPUT VOLTGE (V I ) (V) FIGURE. IMUM OUTPUT HIGH (SOURCE) CURRENT CHRCTERISTICS FIGURE 7. TYPICL VOLTGE TRNSFER CHRCTERISTICS S FUNCTION OF TEMPERTURE FN3315 Rev 1.00 Page of 11

9 Typical Performance Characteristics (Continued) POWER DISSIPTION PER INVERTER (mw) 5 3 MBIENT TEMPERTURE (T ) = +5 o C SUPPLY VOLTGE (VDD) = 15V FIGURE. TYPICL POWER DISSIPTION vs FREQUENCY CHRCTERISTICS 5V V V LOD CPCITNCE (CL) = 50pF (11pF FIXTURE + 39pF EXT) CL = 15pF (11pF FIXTURE + pf EXT 3 5 INPUT FREQUENCY (f) (khz) POWER DISSIPTION PER INVERTER (PD) ( W) MBIENT TEMPERTURE (T ) = +5 o C V; 1KHz SUPPLY VOLTGE (VCC) = 5V FREQUENCY (f) = KHz 15V; 0KHz V; 0KHz 15V; KHz V; KHz 15V; 1MHz INPUT RISE ND FLL TIME (tr, tf) (ns) FIGURE 9. TYPICL POWER DISSIPTION vs INPUT RISE ND FLL TIMES PER INVERTER Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( -3 inch). METLLIZTION: Thickness: 11kÅ 1kÅ, L. PSSIVTION: BOND PDS:.kÅ - 15.kÅ, Silane 0.00 inches X 0.00 inches DIE THICKNESS: inches inches FN3315 Rev 1.00 Page 9 of 11

10 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) BSE PLNE SETING PLNE S1 b ccc M bbb S b C - B S C - B D e D S S D S 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (1, N, N/, and N/+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b. 5. Dimension Q shall be measured from the seating plane to the base plane.. Measure dimension S1 at all four corners. 7. Measure dimension S from the top of the ceramic body to the nearest metallization or lead.. N is the maximum number of terminal positions. 9. Braze fillets shall be concave.. Dimensioning and tolerancing per NSI Y1.5M Controlling dimension: INCH. E M c1 L e/ LED FINISH BSE METL b1 M (b) SECTION - -D- -- S Q -C- e -Baaa M C - B S D S c (c) D1.3 MIL-STD-135 CDIP-T1 (D-, CONFIGURTION C) 1 LED CERMIC DUL-IN-LINE METL SEL PCKGE INCHES MILLIMETERS SYMBOL MX MX NOTES b b b b c c D E e 0.0 BSC.5 BSC - e BSC 7. BSC - e/ BSC 3.1 BSC - L Q S S o 5 o 90 o 5 o - aaa bbb ccc M N 1 1 Rev. 0 /9 Copyright Intersil mericas LLC ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3315 Rev 1.00 Page of 11

11 Ceramic Metal Seal Flatpack Packages (Flatpack) -Hb e M H - B Q SETING ND BSE PLNE L M c1 S E3 D S PIN NO. 1 ID RE E1 E E LED FINISH BSE METL b1 (b) 0.03 M H - B SECTION - 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. lternately, a tab (dimension k) may be used to identify pin one.. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions.. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads.. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by inch (0.03mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per NSI Y1.5M Controlling dimension: INCH M E3 (c) L S1 C S D S -D- -C- -B- D K1. MIL-STD-135 CDFP-F1 (F-5, CONFIGURTION B) 1 LED CERMIC METL SEL FLTPCK PCKGE INCHES MILLIMETERS SYMBOL MX MX NOTES b b c c D E E E E e BSC 1.7 BSC - k L Q S M N Rev FN3315 Rev 1.00 Page 11 of 11

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