TRUTH TABLE ENABLE INPUTS INPUTS OUTPUTS E1 C B A Q0 Q1 Q2 Q3 Q5 Q6 Q7 H H H H H H H H H L H H H H H H H H H H L H H H H H H H H H H H H H H

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1 M0 inary to 8 ecoder (ow) escription The M0 provides parallel decoding of a three bit binary word to one of eight lines. The M0 is useful in high speed multiplexer/demultiplexer applications. The M0 is designed to decode a three bit input word to one of eight output lines. The M0 output will be low when selected while all other output are high. The enable inputs, when either or both are high, force all outputs high. The M0 is a true parallel decoder. This eliminates unequal parallel path delay times found in other decoder designs. These devices are ideally suited for multiplexer/demultiplexer applications. Features Propagation elay,.0 ns Typical Power issipation, 35 mw Typical (same as M 0K ) Improved Noise Margin 50 mv (Over Operating Voltage and Temperature Range) Voltage ompensated M 0K ompatible Pb Free Packages are vailable* IP PIN SSIGNMNT IP SUFFI S 620 PIP P SUFFI S 648 MRKING IGRMS* M0 WYYWW M0P WYYWWG V 0 Q3 Q2 Q Q0 V 0Н2 Н5 V = Pin V 2 = Pin V = Pin 8 Н7 Н V 2 Q4 Q5 Q6 Q7 OGI IGRM Pin assignment is for ual in ine Package. For P pin assignment, see the Pin onversion Tables on page 8 of the ON Semiconductor M ata ook (22/). 6НQ0 5НQ 4НQ2 3НQ3 3НQ4 2НQ5 НQ6 TRUT T N INPUTS INPUTS OUTPUTS Q0 Q Q2 Q3 Q5 Q6 Q7 0 Q4 SOIJ S 66 P 20 FN SUFFI S YWG G WYYWW = ssembly ocation W, = Wafer ot YY, Y = Year WW, W = Work Week G = Pb Free Package Н4 0НQ7 *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SORRM/. *For additional marking information, refer to pplication Note N8002/. ORRING INFORMTION See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. Semiconductor omponents Industries,, 2006 February, 2006 Rev. 7 Publication Order Number: M0/

2 M0 Table. MIMUM RTINGS Symbol haracteristic Rating Unit V Power Supply (V = 0) 8.0 to 0 Vdc V I Input Voltage (V = 0) 0 to V Vdc I out Output urrent ontinuous Surge T Operating Temperature Range 0 to +75 T stg Storage Temperature Range Plastic eramic to to +5 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. m Table 2. TRI RTRISTIS (V = 5.2 V ±5%) (Note ) Symbol haracteristic Min Max Min Max Min Max Unit I Power Supply urrent m I in Input urrent igh I in Input urrent ow V O igh Output Voltage Vdc V O ow Output Voltage Vdc V I igh Input Voltage Vdc V I ow Input Voltage Vdc. ach M 0 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 resistor to 2.0 V. Table 3. PRMTRS Symbol haracteristic Min Max Min Max Min Max Unit t pd Propagation elay ata nable t r Rise Time ns t f Fall Time ns NOT: evice will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. lectrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. evice specification limit values are applied individually under normal operating conditions and not valid simultaneously ns 2

3 M0 ontrol Selection TYPI PPITIONS IG SP IT MUTIPR/MUTIPR S0 S M036 R M04 0 M04 0 S0 S S0 S M036 R R Start/Stop 0 M0 0 M OF 64 IN MUTIPR M04 M04 M MS S M0 Q7 Q6 Q5 Q4 Q3 Q2 Q Q0 M04 M04 M04 The it chosen is dependent on six bit code present on inputs 7,, 4 of the M0 and the,, inputs of the M04. M04 M04 3

4 M0 ORRING INFORMTION evice Package Shipping M0FN P Units / Rail M0FNG P Units / Rail M0FNR2 P / Tape & Reel M0FNR2G P / Tape & Reel M0 IP 25 Unit / Rail M0M SOIJ 50 Unit / Rail M0MG SOIJ 50 Unit / Rail M0M SOIJ 2000 / Tape & Reel M0MG SOIJ 2000 / Tape & Reel M0P PIP 25 Unit / Rail M0PG PIP 25 Unit / Rail For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications rochure, R80/. 4

5 M0 PKG IMNSIONS 20 P S ISSU (0.80) M T M S N S N Y RK U (0.80) M T M S N S M Z W 20 G 0.00 (0.250) S T M S N S V VIW (0.80) M T M S N S Z R (0.80) M T M S N S (0.80) M T M S N S G G 0.00 (0.250) S T M S N S (0.00) J T STING PN VIW S K K VIW S NOTS:. IMNSIONS N TORNING PR NSI Y4.5M, IMNSIONS IN INS. 3. TUMS, M, N N TRMIN WR TOP OF SOUR ITS PSTI OY T MO PRTING IN. 4. IMNSION G, TRU POSITION TO MSUR T TUM T, STING PN. 5. IMNSIONS R N U O NOT INU MO FS. OW MO FS IS 0.00 (0.250) PR SI. 6. IMNSIONS IN T PKG TOP MY SMR TN T PKG OTTOM Y UP TO 0.02 (0.300). IMNSIONS R N U R TRMIN T T OUTRMOST TRMS OF T PSTI OY USIV OF MO FS, TI R URRS, GT URRS N INTR FS, UT INUING NY MISMT TWN T TOP N OTTOM OF T PSTI OY. 7. IMNSION OS NOT INU MR PROTRUSION OR INTRUSION. T MR PROTRUSION(S) S NOT US T IMNSION TO GRTR TN (0.40). T MR INTRUSION(S) S NOT US T IMNSION TO SMR TN (0.635). F (0.80) M T M S N S INS MIIMTRS IM MIN M MIN M F G S.27 S J K R U V W Y Z G K

6 M0 PKG IMNSIONS e Z b 0.3 (0.005) M 0.0 (0.004) 8 F VIW P 8 M SOIJ S 66 0 ISSU Q TI P IP SUFFI RMI IP PKG S ISSU O c M J 0.25 (0.00) M T NOTS:. IMNSIONING N TORNING PR NSI Y4.5M, ONTROING IMNSION: MIIMTR. 3. IMNSIONS N O NOT INU MO FS OR PROTRUSIONS N R MSUR T T PRTING IN. MO FS OR PROTRUSIONS S NOT 0.5 (0.006) PR SI. 4. TRMIN NUMRS R SOWN FOR RFRN ONY. 5. T WIT IMNSION (b) OS NOT INU MR PROTRUSION. OW MR PROTRUSION S 0.08 (0.003) TOT IN SS OF T WIT IMNSION T MIMUM MTRI ONITION. MR NNOT OT ON T OWR RIUS OR T FOOT. MINIMUM SP TWN PROTRUSIONS N JNT TO 0.46 ( 0.08). MIIMTRS INS IM MIN M MIN M b c e.27 S S M Q Z NOTS:. IMNSIONING N TORNING PR SM Y4.5M, ONTROING IMNSION: IN. 3. IMNSION TO NTR OF WN FORM PR. 4. IMNSION F MY NRROW TO 0.76 (0.030) WR T NTRS T RMI OY. 5 TIS RWING RPS OSOT S OUTIN INS MIIMTRS IM MIN M MIN M S.27 S F G 0.00 S 2.54 S K S 7.62 S M N K N G T STING PN 0.25 (0.00) M T 6

7 M0 PKG IMNSIONS 8 G F P S K 0.25 (0.00) M T STING T PN M PIP P SUFFI PSTI IP PKG S ISSU R J M NOTS:. IMNSIONING N TORNING PR NSI Y4.5M, ONTROING IMNSION: IN. 3. IMNSION TO NTR OF S WN FORM PR. 4. IMNSION OS NOT INU MO FS. 5. ROUN ORNRS OPTION. INS MIIMTRS IM MIN M MIN M F G 0.00 S 2.54 S S.27 S J K M S M 0 and M 0K are trademarks of Motorola, Inc. ON Semiconductor and are registered trademarks of Semiconductor omponents Industries, (SI). SI reserves the right to make changes without further notice to any products herein. SI makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SI assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SI data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SI does not convey any license under its patent rights nor the rights of others. SI products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SI product could create a situation where personal injury or death may occur. Should uyer purchase or use SI products for any such unintended or unauthorized application, uyer shall indemnify and hold SI and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SI was negligent regarding the design or manufacture of the part. SI is an qual Opportunity/ffirmative ction mployer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUITION ORRING INFORMTION ITRTUR FUFIMNT: iterature istribution enter for ON Semiconductor P.O. ox 632, Phoenix, rizona US Phone: or Toll Free US/anada Fax: or Toll Free US/anada mail: orderlit@onsemi.com N. merican Technical Support: Toll Free US/anada Japan: ON Semiconductor, Japan ustomer Focus enter 2 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative. M0/