Quad SPST CMOS Analog Switch

Transcription

1 Quad PT CMO Analog witch HI-201/883 The HI-201/883 is a monolithic device comprised of four independently selectable PT switchers which feature fast switching speeds (185ns typical) combined with low power dissipation (15mW typical at +25 C). Each switch provides low ON resistance operation for input signal voltages up to the supply rails and for signal currents up to 25mA continuous. Rugged I construction eliminates latchup and substrate CR failure modes. All devices provide break-before-make switching and are TTL and CMO compatible for maximum application versatility. The HI-201/883 is an ideal component for use in high frequency analog switching. Typical applications include signal path switching, sample and hold circuits, digital filters, and op amp gain switching networks. HI-201/883 is available in a 16 Ld CerIP package. Features This Circuit is Processed in Accordance to MIL-T-883 and is Fully Conformant Under the Provisions of Paragraph Low On Release Ω Max Wide Analog ignal Range ±15V TTL/CMO Compatible (Logic 1 ) Turn-On Time ns Analog Current Range (Continuous) mA No Latch-Up Replaces G201 Applications High Frequency Analog witching ample and Hold Circuits igital Filters Op Amp Gain witching Networks Pin Configuration HI1-0201/883 (16 L CERIP) TOP VIEW A 1 OUT1 IN A 2 OUT2 IN2 LOGIC INPUT V REF REFERENCE, LEVEL HIFTER, AN RIVER GATE WITCH CELL OURCE RAIN GATE INPUT OUTPUT 4 13 IN V REF IN3 FIGURE 1. FUNCTIONAL IAGRAM OUT OUT3 A A 3 Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. WG. # HI1-0201/883 HI1-201/ to Ld CerIP F16.3 FN CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERIL or Copyright Intersil Americas Inc. 1989, All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

2 Absolute Maximum Ratings Voltage Between and Terminals V ±V UPPLY to Ground (, ) ±20V Analog Input Voltage, (+V ) V UPPLY +2V Analog Input Voltage, (-V ) V UPPLY -2V igital Input Voltage, (+V A ) V UPPLY +4V igital Input Voltage, (-V A ) V UPPLY -4V Peak Current ( or ) (Pulse at 1ms, 10% uty Cycle Max) mA Continuous Current Any Terminal (Except or ) mA Thermal Information Thermal Resistance θ JA ( C/W) θ JC ( C/W) CerIP Package Package Power issipation at +75 C CerIP Package W Package Power issipation erating Factor above +75 C CerIP Package mW/ C Junction Temperature C torage Temperature Range C to +150 C Lead Temperature (oldering 10s) C Recommended Operating Conditions Operating Temperature Range C to +125 C Operating upply Voltage Range (±V UPPLY ) ±15V Analog Input Voltage (V ) ±V UPPLY Logic Low Level (V AL ) V to 0.8V Logic High Level (V AH ) to +V UPPLY CAUTION: o not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. TABLE 1..C. ELECTRICAL PERFORMANCE PECIFICATION evice Tested at: +V UPPLY = +15V, V UPPLY = 15V, V REF = OPEN, = 0V, Unless Otherwise pecified..c. PARAMETER YMBOL CONITION witch ON Resistance r V A = 0.8V, V = 10V, I = -1mA, All Unused Channels V A = ource OFF Leakage Current rain OFF Leakage Current Channel ON Leakage Current Low Level Input Current I (OFF) I (OFF) I (ON) V A = 0.8V, V = -10V, I = 1mA, All Unused Channels V A = V = +14V, V = -14V, V A =, All Unused Channels V A =, V = +14V, V = -14V V = -14V, V = +14V, V A =, All Unused Channels V A =, V = -14V, V = +14V V = -14V, V = +14V, V A =, All Unused Channels V A =, V = +14V, V = -14V V = +14V, V = -14V, V A =, All Unused Channels V A =, V = -14V, V = +14V V = V = +14V, V A = 0.8V, All Unused Channels V A = 0.8V, V = V = -14V V = V = -14V, V A = 0.8V, All Unused Channels V A = 0.8V, V = V = +14V I AL V AL = 0.8V All Unused Channels V A = GROUP A UBGROUP TEMPERATURE ( C) MIN MAX UNIT Ω 2, 3-55 to Ω Ω 2, 3-55 to Ω 2, 3-55 to na 2, 3-55 to na 2, 3-55 to na 2, 3-55 to na 2, 3-55 to na 2, 3-55 to na µa 2, 3-55 to µa High Level I AH V AH = µa Input Current All Unused Channels V AH = 4.0V 2, 3-55 to µa upply Current +I CC All Channels V A = 0.8V 1, 2 +25, ma ma All Channels V A = 1, 2 +25, ma ma 2 FN7990.0

3 TABLE 1..C. ELECTRICAL PERFORMANCE PECIFICATION (Continued) evice Tested at: +V UPPLY = +15V, V UPPLY = 15V, V REF = OPEN, = 0V, Unless Otherwise pecified..c. PARAMETER YMBOL CONITION GROUP A UBGROUP TEMPERATURE ( C) MIN MAX UNIT upply Current -I CC All Channels V A = 0.8V 1, 2 +25, ma ma All Channels V A = 1, 2 +25, ma ma TABLE 2. A.C. ELECTRICAL PERFORMANCE PECIFICATION evice Tested at: +V UPPLY = +15V, V UPPLY = 15V, V REF = OPEN, = 0V, Unless Otherwise pecified. PARAMETER YMBOL CONITION Turn ON Time t ON C L = 100pF, R L = Turn OFF Time t OFF C L = 100pF, R L = GROUP A UBGROUP TEMPERATURE ( C) MIN MAX UNIT ns 10, 11-55, ns ns 10, 11-55, ns TABLE 3. ELECTRICAL PERFORMANCE PECIFICATION (NOTE 1) evice Tested at: +V UPPLY = +15V, V UPPLY = 15V, V REF = OPEN, = 0V PARAMETER YMBOL CONITION NOTE TEMPERATURE ( C) MIN MAX UNIT Address Capacitance C A f = 1MHz, V AL = 0V pf witches Input Capacitance C (OFF) f = 1MHz, V AH = 5V, Measured ource to pf witch Output Capacitance C (OFF) f = 1MHz, V AH = 5V, Measured Output to Ground C (ON) f = 1MHz, V AL = 0V, Measured Output to Ground pf pf rain to ource Capacitance C f = 1MHz, V AH = 5V pf Off Isolation V IO f = 200kHz, V A = 2.4, R L = 1k, db V GEN = 1V P-P, C L = 10pF Cross Talk V CT f = 200kHz, V A = 2.4, R L = 1k, V GEN = 1V P-P, C L = 10pF Charge Transfer Error V CTE f = 200kHz, V A = 0 to 4V, C L = 0.01µF db mv NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. TABLE 4. ELECTRICAL REQUIREMENT MIL-T-883 REQUIREMENT UBGROUP (Tables 1 and 2) Interim Electrical Parameters (Pre Burn-in) 1 Final Electrical Test Parameters 1 (Note 2), 2, 3, 9, 10, 11 Group A Test Requirements 1, 2, 3, 9, 10, 11 Groups C & Endpoints 1 NOTE: 2. PA applies to ubgroup 1 only. 3 FN7990.0

4 Test Circuits V I V I IN FIGURE 2. INPUT LEAKAGE CURRENT FIGURE 3. I (OFF) V I V I (ON) V FIGURE 4. I (OFF) FIGURE 5. I (ON) I 1 TEP GENERATOR 15V IN 1 IN 3 TEP GENERATOR 0.01µF 1 1 IN IN µF I µF µF -15V FIGURE 6. UPPLY CURRENT FIGURE 7. CHARGE TRANFER ERROR 4 FN7990.0

5 Test Circuits (Continued) 15V INE WAVE GENERATOR IN 1 IN 3 INE WAVE GENERATOR V 1 1 IN IN V FIGURE 8. R FIGURE 9. OFF CHANNEL IOLATION 0.8V 15V IN 1 IN 3 0.8V 0.8V 1 1 IN IN V 0.8V TEP GENERATOR FIGURE 10. CROTALK BETWEEN CHANNEL 5 FN7990.0

6 witching Waveforms +4V FIGURE 11. FIGURE FN7990.0

7 Burn-In Circuit NOTE: R 1 = R 2 = R 3 = R 4 = 10kΩ. C 1 = C 2 = 0.01µF (per socket) or 0.1µF (per row). 1 = 2 = IN4002 or equivalent/board. () - () = 30V. FIGURE 13. HI-201/883 CERIP chematic iagrams TTL/CMO REFERENCE CIRCUIT V REF CELL R 2 5k QP2 R6 600 QP1 QP3 Q N4 V REF M P13 Q P4 Q P5 TO P 2 Q N1 3 R k M N14 Q N2 R 4 5.4k M P14 Q N3 V LL R 5 7.9k Q P6 M N15 MN16 MN17 R 7 100k 7 FN7990.0

8 chematic iagrams (Continued) WITCH CELL A Q N11 Q N12 INPUT Q P11 Q N13 OUTPUT Q P12 A IGITAL INPUT BUFFER AN LEVEL HIFTER Q P3 Q P5 Q P1 Q P4 A Q N1 1 QP6 Q P7 Q P8 QP9 Q P10 TO V LL R1 200Ω 2 TO V REF Q N6 Q N7 Q N8 Q N9 QN10 Q P2 A A Q N2 QN4 Q N5 Q N3 8 FN7990.0

9 Typical Performance Curves T A = +25 C, V UPPLY = ±15V, V AH =, V AL = 0.8V and V REF = Open ON REITANCE (Ω) = 0V ON REITANCE (Ω) 50 = +12.5V = -12.5V = +10V = -10V = +15V = -15V TEMPERATURE ( o C) FIGURE 14. ON REITANCE vs TEMPERATURE ANALOG IGNAL LEVEL (V) FIGURE 15. ON REITANCE vs ANALOG IGNAL LEVEL AN POWER UPPLY VOLTAGE CURRENT (na) I (OFF) / I (OFF) I (ON) WITCH CURRENT (ma) TEMPERATURE ( o C) FIGURE 16. LEAKAGE CURRENT vs TEMPERATURE VOLTAGE ACRO WITCH (±V) FIGURE 17A. WITCH CURRENT vs VOLTAGE OFF IOLATION (db) R L = Hz 1kHz 10kHz 100kHz 1MHz FREQUENCY (Hz) FIGURE 18. OFF IOLATION vs FREQUENCY 9 FN7990.0

10 ie Characteristics IE IMENION: 81 X 85 X 19 mils METALLIZATION: Type: Aluminum Thickness: 16kÅ ±2kÅ Metallization Mask Layout HI-201/883 GLAIVATION: Type: Nitride over ilox ilox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1kÅ WORT CAE CURRENT ENITY: 2 x 10 5 A/cm 2 at 25mA A 1 A 2 OUT OUT 2 IN IN V REF IN IN 3 OUT OUT 3 A 4 A 3 10 FN7990.0

11 Ceramic ual-in-line Frit eal Packages (CERIP) BAE PLANE EATING PLANE 1 b2 ccc M bbb b C A - B C A - B A A e NOTE: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. imensions b1 and c1 apply to lead base metal only. imension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. imension Q shall be measured from the seating plane to the base plane. 7. Measure dimension 1 at all four corners. 8. N is the maximum number of terminal positions. 9. imensioning and tolerancing per ANI Y14.5M Controlling dimension: INCH. E L M c1 ea/2 aaa M C A - B LEA FINIH BAE METAL b1 M (b) ECTION A-A -- -A- Q -C- A -Bα ea c (c) F16.3 MIL-T-1835 GIP1-T16 (-2, CONFIGURATION A) 16 LEA CERAMIC UAL-IN-LINE FRIT EAL PACKAGE INCHE MILLIMETER YMBOL MIN MAX MIN MAX NOTE A b b b b c c E e BC 2.54 BC - ea BC 7.62 BC - ea/ BC 3.81 BC - L Q α 90 o 105 o 90 o 105 o - aaa bbb ccc M , 3 N Rev. 0 4/94 For additional products, see Intersil products are manufactured, assembled and tested utilizing IO9000 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 11 FN7990.0