MILITARY SPECIFICATION MICROCIRCUITS, LINEAR, CMOS/ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH OVERVOLTAGE PROTECTION, MONOLITHIC SILICON, POSITIVE LOGIC
|
|
- Claude Russell Dickerson
- 5 years ago
- Views:
Transcription
1 INCH-POUND 12 October 2005 SUPERSEDING MIL-M-38510/190C 22 October 1986 MILITARY SPECIFICATION MICROCIRCUITS, LINEAR, CMOS/ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH OVERVOLTAGE PROTECTION, MONOLITHIC SILICON, POSITIVE LOGIC This specification is approved for use by all Departments and Agencies of the Department of Defense. Inactive for new design as of 10 July 1995 The requirements for acquiring the product herein shall consist of this specification sheet and MIL-PRF SCOPE 1.1 Scope. This specification covers the detail requirements for monolithic silicon, CMOS/Analog logic microcircuits. Two product assurance classes and a choice of case outlines and lead finishes are provided and are reflected in the complete part number. For this product, the requirements of MIL-M have been superseded by MIL-PRF-38535, (see 6.4) 1.2 Part or Identifying Number (PIN). The PIN is in accordance with MIL-PRF-38535, and as specified herein Device types. The device types are as follows: Device type Circuit 01 Single 16-channel MUX/DEMUX 02 Single 16-channel MUX/DEMUX with overvoltage protection 03 Differential 8-channel MUX/DEMUX 04 Differential 8-channel MUX/DEMUX with overvoltage protection 05 Single 8-channel MUX/DEMUX with overvoltage protection 06 Differential 4-channel MUX/DEMUX with overvoltage protection 07 Single 8-channel MUX/DEMUX 08 Differential 4-channel MUX/DEMUX Device class. The device class is the product assurance level as defined in MIL-PRF outline. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator s Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line X See figure 4 28 Dual-in-line Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAS, 3990 East Broad St., Columbus, OH , or mailto:linear@dscc.dla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at AMSC N/A FSC 5962
2 1.3 Absolute maximum ratings. Supply voltage between V+ and V-: Device types 02, 04, 05, and V Device types 01, 03, 07, and V V+ to ground: Device types 02, 04, 05, and V Device types 01, 03, 07, and V Digital input voltage: Device types 02, 04, 05, and ((V-) 4 V) V D ((V+) + 4 V) Device types 01, 03, 07, and V V D (V+) Analog input: Device types 02, 04, 05, and ((V-) 20 V V A ((V+) + 20 V) Device types 01, 03, 07, and (V-) V A (V+) Storage temperature C to +150 C Lead temperature (soldering, 10 seconds) C Junction temperature (T J ) C 1.4 Recommended operating conditions. V V V V V REF... Open V IL (max) V V IH (min): Device types 01, 03, 07, and V Device types 02, 04, 05, and V V EN : Device types 02, 04, 05, and V Device types 01, 03, 07, and V Ambient operating temeperature range (T A ) C to +125 C 1.5 Power and thermal characteristics. outline Maximum allowable power dissipation 1/ Maximum θ JC 2/ Maximum θ JA E 400 T A = 125 C 50 C/W 125 C/W X 400 T A = 125 C 51 C/W 125 C/W 2. APPLICABLE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 1/ All leads welded or soldered to PC board. 2/ Applies only when T A 75 C. 2
3 2.2 Government documents Specifications and Standards. The following specifications and standards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF Integrated Circuits (Microcircuits) Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD Method Standard for Microelectronics. - Interface Standard Electronic Component Outlines. (Copies of these documents are available online at or or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA Order of precedence. In the event of a conflict between the text of this document and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.3). 3.2 Item requirements. The individual item requirements shall be in accordance with MIL-PRF and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF and herein. Although eutectic die bonding is preferred, epoxy die bonding may be performed. However, the resin used shall be Dupont 5504A conductive silver paste, or equivalent, which is cured at 200 C ±10 C for a minimum of 2 hours. The use of equivalent epoxies or cure cycles shall be approved by the qualifying activity. Equivalency shall be demonstrated in data submitted to the qualifying acivity for verification connections. The terminal connections shall be as specified on figure Functional diagrams. The functional diagrams shall be as specified on figure Truth tables. The truth tables shall be as specified on figure outline. The case outline shall be as specified in and figure Schematic circuits. The schematic circuits shall be maintained by the manufacturer and made available to the qualifying activity and the preparing activity (DSCC-VA) upon request. 3.4 Lead material and finish. The lead material and finish shall be in accordance with MIL-PRF (see 6.6). 3.5 Electrical performance characteristics. The electrical performance characteristics are as specified in table I, and apply over the full recommended ambient operating temperature range, unless otherwise specified. 3.6 Electrical test requirements. Electrical test requirements for each device class shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MIL-PRF Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 82 (see MIL-PRF-38535, appendix A). 3
4 TABLE I. Electrical performance characteristics. Conditions 1/ 2/ V- = -15 V, V+ = +15 V, V EN = 4.5 V, GND = 0 V, -55 C T A +125 C unless otherwise specified Device type Limits Positive input clamping voltage Negative input clamping voltage V IC(POS), V+ = V- = 0 V, I IN = 1 ma V IC(NEG), V+ = V- = 0 V, I IN = -1 ma Input leakage current 3/ I IH Measure address inputs sequentially, connect all unused address inputs to GND Input leakage current 3/ I IL Measure address inputs sequentially, connect all unused address inputs to 5 V Leakage current into the source terminal of an OFF switch Leakage current into the drain terminal of an OFF switch I S(OFF) V S = 10 V, V EN = 0.8 V, All unused sources = -10 V, V S = 10 V, V EN = 0.8 V, All unused sources = -10 V, -55 C T A 125 C V S = -10 V, V EN = 0.8 V, All unused sources= +10 V, V S = -10 V, V EN = 0.8 V, All unused sources= +10 V, -55 C T A 125 C I D+(OFF) V D = 10 V, V EN = 0.8 V, All unused sources = -10 V, V D = 10 V, V EN = 0.8 V, All unused sources = -10 V, -55 C T A 125 C 02, 04, 05, 06 02, 04, 05, 06 Min Max 1.5 V dc -1.5 V dc All µa All µa All -1 1 na , na 03, 04, 05, 06, 07, , , 04, 05, ,
5 TABLE I. Electrical performance characteristics Continued. Conditions 1/ 2/ V- = -15 V, V+ = +15 V, V EN = 4.5 V, GND = 0 V, -55 C T A +125 C unless otherwise specified Device type Limits Leakage current into the drain terminal of an OFF switch Leakage current from an ON driver into the switch (drain) I D-(OFF) V D = 10 V, V EN = 0.8 V, All unused sources = -10 V, V D = 10 V, V EN = 0.8 V, All unused sources = -10 V, -55 C T A 125 C I D(ON) V S = 10 V, V D = 10 V, Connect all unused sources to -10 V, V S = 10 V, V D = 10 V, Connect all unused sources to -10 V, -55 C T A 125 C V S = 10 V, V D = -10 V, Connect all unused sources to -10 V, V S = 10 V, V D = -10 V, Connect all unused sources to -10 V, -55 C T A 125 C Min Max 01, na 03, 04, 05, 06, 07, , , 04, 05, , , na 03, 04, 05, 06, 07, , , 04, 05, , , , 04, 05, 06, 07, , , 04, 05, ,
6 TABLE I. Electrical performance characteristics Continued. Conditions 1/ 2/ V- = -15 V, V+ = +15 V, V EN = 4.5 V, GND = 0 V, -55 C T A +125 C unless otherwise specified Device type Limits Overvoltage protected, leakage current into the drain terminal of an OFF switch I D(OFF) overvoltage V S = 33 V, V D = 0 V, V EN = 0.8 V V S = -33 V, V D = 0 V, V EN = 0.8 V 02, 04, 05, 06 Min Max µa Positive supply current I(+) V A = 0 V, V EN = 5 V 01, ma 02, 04, 05, , Negative supply current I(-) V A = 0 V, V EN = 5 V 01, ma Standby positive supply current Standby negative supply current 02, 04, 05, , I+SBY V A = 0 V, V EN = 0 V 01, ma 02, 04, 05, , I-SBY V A = 0 V, V EN = 0 V 01, ma Capacitance: Address C A V+ = V- = 0 V,, f = 1 MHz Capacitance: Enable C EN V+ = V- = 0 V,, f = 1 MHz Capacitance: Output switch Capacitance: Input switch C OS V+ = V- = 0 V, See table III C IS V+ = V- = 0 V, See table III 02, 04, 05, , All 10 pf All 10 pf pf , , , All 10 pf 6
7 TABLE I. Electrical performance characteristics Continued. Conditions 1/ 2/ V- = -15 V, V+ = +15 V, V EN = 4.5 V, GND = 0 V, -55 C T A +125 C unless otherwise specified Device type Limits Switch ON resistance R DS1 V S = 10 V, I D = 1 ma,, T A = -55 C V S = 10 V, I D = 1 ma, T A = 125 C V S = 10 V, I D = 100 µa,, T A = -55 C V S = 10 V, I D = 100 µa, T A = 125 C V S = 10 V, I D = 100 µa,, T A = -55 C V S = 10 V, I D = 100 µa, T A = 125 C V S = 10 V, I D = 1 ma,, T A = -55 C V S = 10 V, I D = 1 ma, T A = 125 C Switch ON resistance R DS1 V S = -10 V, I D = -1 ma,, T A = -55 C V S = -10 V, I D = -1 ma, T A = 125 C V S = -10 V, I D = -100 µa,, T A = -55 C V S = -10 V, I D = -100 µa, T A = 125 C V S = -10 V, I D = -100 µa,, T A = -55 C V S = -10 V, I D = -100 µa, T A = 125 C V S = -10 V, I D = -1 ma,, T A = -55 C V S = -10 V, I D = -1 ma, T A = 125 C Min Max 01, Ω , 04 1,500 2,000 05, 06 1,500 1,800 07, , Ω , 04 1,500 2,000 05, 06 1,500 1,800 07,
8 TABLE I. Electrical performance characteristics Continued. Conditions 1/ 2/ V- = -15 V, V+ = +15 V, V EN = 4.5 V, GND = 0 V, -55 C T A +125 C unless otherwise specified Device type Limits Switch ON resistance R DS2 V+ = 10 V, V- = -10 V, V S = 7.5 V, I D = 1 ma V+ = 10 V, V- = -10 V, V S = 7.5 V, I D = 100 µa V+ = 10 V, V- = -10 V, V S = -7.5 V, I D = -1 ma V+ = 10 V, V- = -10 V, V S = -7.5 V, I D = -100 µa Single channel isolation V ISO f = 200 khz, V GEN = 1 V P-P, see figure 15 Crosstalk between channels V CT F = 200 khz, V GEN = 1 V P-P, see figure 16 01, 03, 07, 08 Min Max 1,000 Ω 02, 04 2,400 05, 06 2,200 01, 03, 07, 08 1,000 02, 04 2,400 05, 06 2,200 All 50 db All 50 db Charge transfer error V CTE V S = GND, see figure 17 All 10 mv Break-before-make time delay Propagation delay times: Address inputs to I/O channels Enable to I/O t D See figure 14, All 5 ns t ON(A) t OFF(A) t ON(EN) t OFF(EN) R L = 1 kω, C L = 100 pf, see figures 6, 8, 10, and 12,, T A = -55 C R L = 1 kω, C L = 100 pf, see figures 6, 8, 10, and 12, T A = 125 C R L = 1 kω, C L = 100 pf, see figures 7, 9, 11, and 13,, T A = -55 C R L = 1 kω, C L = 100 pf, see figures 7, 9, 11, and 13, T A = 125 C All 1,000 ns 1,500 All 1,000 ns 1,500 1/ Current flowing in either direction between any associated input and output terminals of the switch shall be 30 ma maximum. 2/ Input = source; Output = drain. 3/ Input current of one input node. 8
9 4. VERIFICATION. 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF or as modified in the device manufacturer s Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and quality conformance inspection. The following additional criteria shall apply: a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II, except interim electrical parameters test prior to burn-in is optional at the discretion of the manufacturer. c. Additional screening for space level product shall be as specified in MIL-PRF Qualification inspection. Qualification inspection shall be in accordance with MIL-PRF Technology Conformance inspection (TCI). Technology conformance inspection shall be in accordance with MIL-PRF and herein for groups A, B, C, and D inspections (see through 4.4.4). TABLE II. Electrical test requirements. MIL-PRF test requirements Subgroups (see table III) 1/ 2/ 3/ Class S Class B devices 4/ devices Interim electrical parameters 1 1 Final electrical test parameters 1, 2, 3, 9 1, 2, 3,9 Group A test requirements 1,2,3,4,9,10, 11,12,13 Group B electrical test parameters when 1,2,3 and using the method 5005 QCI option table IV delta Group C end-point electrical parameters Additional electrical subgroups for group C periodic inspections Group D end-point electrical parameters Additional electrical subgroups for group D periodic inspection 1/ PDA applies to subgroup 1. 2/ See 4.4.1c 3/ See 4.4.1e 4/ See 4.4.4b limits 1,2,3 and table IV delta limits 1,2,3,4,9,12,13 N/A 1 and table IV delta limits N/A 10, 11, 12 1,2, None 9
10 Device type 01 Device type 02 X X Dev Figure 1. connections. 10
11 Device type 03 Device type 04 X X Figure 1. connections Continued. 11
12 Device types 05 and 07 E Device types 06 and 08 E Figure 1. connections Continued. 12
13 Device types 01 and 02 NOTE: Optional (normally left open) FIGURE 2. Functional diagrams. 13
14 Device types 03 and 04 NOTE: Optional (normally left open) FIGURE 2. Functional diagrams Continued. 14
15 Device types 05 and 07 Device types 06 and 08 FIGURE 2. Functional diagrams Continued. 15
16 Device types 01 and 02 A3 A2 A1 A0 EN CHANNEL SELECTED X X X X L NONE L L L L H 1 L L L H H 2 L L H L H 3 L L H H H 4 L H L L H 5 L H L H H 6 L H H L H 7 L H H H H 8 H L L L H 9 H L L H H 10 H L H L H 11 H L H H H 12 H H L L H 13 H H L H H 14 H H H L H 15 H H H H H 16 Device types 03 and 04 A2 A1 A0 EN CHANNEL SELECTED X X X L NONE L L L H 1A, 1B L L H H 2A, 2B L H L H 3A, 3B L H H H 4A, 4B H L L H 5A, 5B H L H H 6A, 6B H H L H 7A, 7B H H H H 8A, 8B FIGURE 3. Truth tables. 16
17 Device types 05 and 07 A2 A1 A0 EN CHANNEL SELECTED X X X L NONE L L L H 1 L L H H 2 L H L H 3 L H H H 4 H L L H 5 H L H H 6 H H L H 7 H H H H 8 Device types 06 and 08 A1 A0 EN CHANNEL SELECTED X X L NONE L L H 1A, 1B L H H 2A, 2B H L H 3A, 3B H H H 4A, 4B FIGURE 3. Truth tables Continued. 17
18 FIGURE 4. outline X. 18
19 Inches Millimeters Notes Min Max Min Max A b b , 8 C D E E E 2 N/A N/A N/A N/A E 3 N/A N/A N/A N/A e.100 BSC 2.54 BSC 5, 9 L L Q Q 1 N/A N/A N/A N/A S S S N/A α NOTES: 1. Index area; a notch or a pin one identification mark shall be located adjacent to pin one and shall be located Within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The minimum limit for dimension b 1 may be.023 (.58 mm) for leads number 1, 14, 15, and 28 only. 3. Dimension Q shall be measured from the seating plane to the base plane. 4. This dimension allows for off-center lid, meniscus and glass overrun. 5. The basic pin spacing is.100 (2.54 mm) between centerlines. Each pin centerline shall be located within ±.010 (.25 mm) of its exact longitudinal position relative to pins 1 and Applies to all four corners (leads number 1, 14, 15, and 28). 7. Lead center when α = 0. E 1 shall be measured at the centerline of the leads. 8. All leads Increase maximum limit by.003 (.08 mm) measured at the center of the flat, when lead finish A or B is applied. 9. Twenty six spaces. 10. If this configuration is used, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. FIGURE 4. outline X Continued. 19
20 Device types 02, 04, 05, and 06 NOTES: 1. All device inputs shall be protected from transients such a electrostatic discharge. This circuit is Intrinsic to the device. 2. This resistance is 200 to 2,000 Ω depending on device type. FIGURE 5. Address and Enable input protection circuit. 20
21 Device types 01 and 02 Address inputs to I/O Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns DYNAMIC TEST WAVEFORMS FIGURE 6. Switching time test circuit and waveforms. 21
22 Device types 01 and 02 Enable to I/O Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns DYNAMIC TEST WAVEFORMS FIGURE 7. Switching time test circuit and waveforms. 22
23 Device types 03 and 04 Address inputs to I/O Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns DYNAMIC TEST WAVEFORMS FIGURE 8. Switching time test circuit and waveforms. 23
24 Device types 03 and 04 Enable to I/O Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns DYNAMIC TEST WAVEFORMS FIGURE 9. Switching time test circuit and waveforms. 24
25 Device types 05 and 07 Address inputs to I/O Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns DYNAMIC TEST WAVEFORMS FIGURE 10. Switching time test circuit and waveforms. 25
26 Device types 05 and 07 Enable to I/O DYNAMIC TEST WAVEFORMS Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns FIGURE 11. Switching time test circuit and waveforms. 26
27 Device types 06 and 08 Address inputs to I/O Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns DYNAMIC TEST WAVEFORMS FIGURE 12. Switching time test circuit and waveforms. 27
28 Device types 06 and 08 Enable to I/O Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns DYNAMIC TEST WAVEFORMS FIGURE 13. Switching time test circuit and waveforms. 28
29 Input pulse requirements: V GEN = 4 V t THL(1) = t TLH(1) 20 ns FIGURE 14. Break before make test circuit and waveforms. 29
30 NOTE: The pulse generator has the following characteristics: V GEN = 1 V P-P, PRR = 200 khz. FIGURE 15. Single channel isolation test circuit. NOTE: The pulse generator has the following characteristics: V GEN = 1 V P-P, PRR = 200 khz. FIGURE 16. Crosstalk test circuit. 30
31 NOTE: The pulse generator has the following characteristics: V GEN = 0 5 V. FIGURE 17. Charge transfer error test circuit. 31
32 TABLE III. Group A inspection for device type MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND NC A3 I IH 2/ V GND 2.4 V A µa 2 GND A2 3 A1 4 A0 5 EN I IL 2/ V A V A2 8 A1 9 A0 10 EN I S(OFF) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 0.8 V IN na 3/ 12 IN2 13 IN3 14 IN4 15 IN5 16 IN6 17 IN7 18 IN V 2.4 V IN V -10 V IN V -10 V IN V -10 V IN V -10 V IN V -10 V IN V -10 V -10 V IN V -10 V -10 V -10 V IN V 10 V 10 V 10 V 10 V 10 V 10 V 0.8 V IN1 28 IN2 29 IN3 30 IN4 31 IN5 32 IN6 33 IN7 34 IN V 2.4 V IN V 10 V IN V 10 V IN V 10 V IN V 10 V IN V 10 V IN V 10 V IN V 10 V 10 V IN16 I D-(OFF) V 10 V 10 V 0.8 V OUT I D+(OFF) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V OUT I D+(ON) 45 IN1 & OUT 46 IN2 & OUT 47 IN3 & OUT 48 IN4 & OUT 49 IN5 & OUT 50 IN6 & OUT 51 IN7 & OUT
33 TABLE III. Group A inspection for device type 01 Continued. 33 X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT I IH 2/ 1 GND GND GND GND -15 V A µa V GND GND A2 3 GND 2.4 V GND A1 4 GND GND 2.4 V A0 5 GND GND GND 2.4 V EN I IL 2/ 6 5 V 5 V 5 V 5 V A V 5 V A2 8 5 V 0.8 V A1 9 5 V 5 V 0.8 V A V 5 V 5 V 0.8 V EN I S(OFF) V 0.8 V 0.8 V 0.8 V 10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V IN na 3/ V 2.4 V -10 V 10 V -10 V -10 V IN V 0.8 V -10 V 10 V -10 V IN V 2.4 V -10 V 10 V IN V 0.8 V 0.8 V -10 V 10 V IN V 2.4 V -10 V 10 V IN V 0.8 V -10 V 10 V IN V 2.4 V -10 V 10 V IN V 0.8 V 0.8 V -10 V IN V 2.4 V IN V 0.8 V IN V 2.4 V IN V 0.8 V 0.8 V IN V 2.4 V IN V 0.8 V IN V 2.4 V IN V 0.8 V 0.8 V 0.8 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V IN V 2.4 V 10 V -10 V 10 V 10 V IN V 0.8 V 10 V -10 V 10 V IN V 2.4 V 10 V -10 V IN V 0.8 V 0.8 V 10 V -10 V IN V 2.4 V 10 V -10 V IN V 0.8 V 10 V -10 V IN V 2.4 V 10 V -10 V IN V 0.8 V 0.8 V 10 V IN V 2.4 V IN V 0.8 V IN V 2.4 V IN V 0.8 V 0.8 V IN V 2.4 V IN V 0.8 V IN V 2.4 V IN16 I D-(OFF) V 0.8 V 0.8 V -10 V OUT I D+(OFF) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 10 V OUT I D+(ON) V 4.5 V 10 V -10 V -10 V IN1 & OUT V -10 V 10 V 10 V IN2 & OUT V 0.8 V -10 V -10 V IN3 & OUT V 2.4 V 10 V IN4 & OUT V 0.8 V 0.8 V -10 V 10 V IN5 & OUT V 0.8 V 2.4 V -10 V -10 V 10 V IN6 & OUT V 2.4 V 0.8 V -10 V -10 V -10 V IN7 & OUT
34 TABLE III. Group A inspection for device types 01 Continued. 34 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND NC A3 I D+(ON) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V GND 0.8 V IN8 & OUT na V -10 V 10 V 2.4 V IN9 & OUT V 10 V -10 V IN10 & OUT V -10 V IN11 & OUT V -10 V IN12 & OUT V -10 V IN13 & OUT V -10 V IN14 & OUT V -10 V -10 V IN15 & OUT V -10 V -10 V -10 V IN16 & OUT I D-(ON) V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 0.8 V IN1 & OUT 62 IN2 & OUT 63 IN3 & OUT 64 IN4 & OUT 65 IN5 & OUT 66 IN6 & OUT 67 IN7 & OUT 68 IN8 & OUT V 2.4 V IN9 & OUT V 10 V IN10 & OUT V 10 V IN11 & OUT V 10 V IN12 & OUT V 10 V IN13 & OUT V 10 V IN14 & OUT V 10 V 10 V IN15 & OUT V 10 V 10 V 10 V IN16 & OUT I V V ma I- 78 V I+SBY 79 V I-SBY 80 V R DS1 81 IN1 & OUT Ω 82 IN2 & OUT 83 IN3 & OUT 84 IN4 & OUT 85 IN5 & OUT 86 IN6 & OUT 87 IN7 & OUT 88 IN8 & OUT V 2.4 V IN9 & OUT V IN10 & OUT V IN11 & OUT V IN12 & OUT V IN13 & OUT V IN14 & OUT V IN15 & OUT V IN16 & OUT V IN1 & OUT 98 IN2 & OUT 99 IN3 & OUT 100 IN4 & OUT 101 IN5 & OUT
35 TABLE III. Group A inspection for device type 01 Continued. 35 X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT I D+(ON) V 2.4 V 2.4 V 4.5 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 10 V -15 V 10 V IN8 & OUT na V 0.8 V 0.8 V -10 V IN9 & OUT V 2.4 V IN10 & OUT V 0.8 V IN11 & OUT V 2.4 V IN12 & OUT V 0.8 V 0.8 V IN13 & OUT V 2.4 V IN14 & OUT V 0.8 V IN15 & OUT V 2.4 V IN16 & OUT I D-(ON) V 0.8 V 0.8 V -10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V -10 V IN1 & OUT V 2.4 V 10 V -10 V 10 V 10 V IN2 & OUT V 0.8 V 10 V -10 V 10 V IN3 & OUT V 2.4 V 10 V -10 V IN4 & OUT V 0.8 V 0.8 V 10 V -10 V IN5 & OUT V 2.4 V 10 V -10 V IN6 & OUT V 0.8 V 10 V -10 V IN7 & OUT V 2.4 V 10 V -10 V IN8 & OUT V 0.8 V 0.8 V 10 V IN9 & OUT V 2.4 V IN10 & OUT V 0.8 V IN11 & OUT V 2.4 V IN12 & OUT V 0.8 V 0.8 V IN13 & OUT V 2.4 V IN14 & OUT V 0.8 V IN15 & OUT V 2.4 V IN16 & OUT I V 0 V 0 V 5 V V ma I V V I+SBY 79 0 V V I-SBY 80 0 V V R DS V 0.8 V 0.8 V 4.5 V 10 V 100 µa IN1 & OUT Ω V 2.4 V 10 V IN2 & OUT V 0.8 V 10 V IN3 & OUT V 2.4 V 10 V IN4 & OUT V 0.8 V 0.8 V 10 V IN5 & OUT V 2.4 V 10 V IN6 & OUT V 0.8 V 10 V IN7 & OUT V 2.4 V 10 V IN8 & OUT V 0.8 V 0.8 V IN9 & OUT V 2.4 V IN10 & OUT V 0.8 V IN11 & OUT V 2.4 V IN12 & OUT V 0.8 V 0.8 V IN13 & OUT V 2.4 V IN14 & OUT V 0.8 V IN15 & OUT V 2.4 V IN16 & OUT V 0.8 V 0.8 V -10 V -100 µa IN1 & OUT V 2.4 V -10 V IN2 & OUT V 0.8 V -10 V IN3 & OUT V 2.4 V -10 V IN4 & OUT V 0.8 V 0.8 V -10 V IN5 & OUT
36 TABLE III. Group A inspection for device type 01 Continued. 36 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND NC A3 R DS V GND 0.8 V IN6 & OUT Ω 103 IN7 & OUT 104 IN8 & OUT V 2.4 V IN9 & OUT V IN10 & OUT V IN11 & OUT V IN12 & OUT V IN13 & OUT V IN14 & OUT V IN15 & OUT V IN16 & OUT R DS Same terminal conditions as for tests 81 thru 96, except V± = ± 10 V, V S = +7.5 V and limits as shown kω R DS Same terminal conditions as for tests 97 thru 112, except V± = ± 10 V, V S = -7.5 V and limits as shown kω Subgroup 4 Min Max C A GND GND 4/ A3 10 pf 146 A2 147 A1 148 A0 C OS V OUT 90 C IS 150 IN IN2 152 IN3 153 IN4 154 IN5 155 IN6 156 IN7 157 IN / IN / IN / IN / IN / IN / IN / IN / IN16 C EN 166 EN
37 TABLE III. Group A inspection for device type 01 Continued. 37 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT R DS V 0.8 V 2.4 V 4.5 V -10 V -15 V -100 µa IN6 & OUT Ω V 2.4 V 0.8 V -10 V IN7 & OUT V 2.4 V 2.4 V -10 V IN8 & OUT V 0.8 V 0.8 V IN9 & OUT V 2.4 V IN10 & OUT V 0.8 V IN11 & OUT V 2.4 V IN12 & OUT V 0.8 V 0.8 V IN13 & OUT V 2.4 V IN14 & OUT V 0.8 V IN15 & OUT V 2.4 V IN16 & OUT R DS Same terminal conditions as for tests 81 thru 96, except V± = ± 10 V, V S = +7.5 V and limits as shown kω R DS Same terminal conditions as for tests 97 thru 112, except V± = ± 10 V, V S = -7.5 V and limits as shown kω Subgroup 4 Min Max C A 145 GND A3 10 pf 146 4/ A / A / A0 C OS V 0 V 0 V 0 V 5/ OUT 90 C IS 150 4/ IN / IN / IN / IN / IN / IN / IN / IN8 158 IN9 159 IN IN IN IN IN IN IN16 C EN 166 4/ EN
38 TABLE III. Group A inspection for device type 01 Continued. 38 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 9 Subgroup 10 Subgroup 11 T A = 125 C T A = -55 C V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND NC A3 t ON(A) V -10 V GND GND GND GND GND GND GND GND _/ ADDRESS 1,000 1,500 1,000 ns and fig V _/ IN TO OUT t OFF(A) V \_ V \_ 171 GND _/ 172 _/ 173 \_ 174 \_ t ON(EN) fig V -10 V -10 V -10 V -10 V -10 V -10 V -10 V GND GND ENABLE and V 10 V 10 V 10 V 10 V 10 V 10 V 10 V TO OUT t OFF(EN) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V V 10 V 10 V 10 V 10 V 10 V 10 V 10 V Subgroup 12 Min Max V ISO fig V IN IN IN IN IN IN IN IN GND GND OUT 50 db V CT fig V IN IN IN IN IN IN IN IN GND GND OUT 50 db V CTE fig V GND IN OUT 10 mv Subgroup 13 Min Max t D fig V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V GND _/ OUT 5 ns V -10 V -10 V -10 V -10 V -10 V -10 V -10 V _/ V 10 V 10 V 10 V 10 V 10 V 10 V 10 V \_ V -10 V -10 V -10 V -10 V -10 V -10 V -10 V \_
39 TABLE III. Group A inspection for device type 01 Continued. 39 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 9 Subgroup 10 Subgroup 11 T A = 125 C T A = -55 C A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT t ON(A) 167 _/ _/ _/ 5 V GND GND GND GND GND GND GND GND -15 V OUT ADDRESS 1,000 1,500 1,000 ns and 168 _/ _/ _/ IN TO OUT t OFF(A) 169 \_ \_ \_ 170 \_ \_ \_ 171 _/ _/ _/ -10 V 172 _/ _/ _/ 10 V 173 \_ \_ \_ -10 V 174 \_ \_ \_ 10 V t ON(EN) 175 GND GND GND _/ -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V ENABLE and 176 \_ 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V TO OUT t OFF(EN) 177 _/ -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 178 \_ 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V Subgroup 12 Min Max V ISO 179 GND GND GND 0 V IN IN IN IN IN IN IN IN -15 V OUT OUT 50 db V CT 180 GND GND GND 5 V 6/ IN IN IN IN IN IN IN -15 V OUT OUT 50 db V CTE 181 IN IN IN 5 V GND -15 V OUT OUT 10 mv Subgroup 13 Min Max t D 182 _/ _/ _/ 5 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V -15 V OUT OUT 5 ns 183 _/ _/ _/ -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 184 \_ \_ \_ 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 185 \_ \_ \_ -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V
40 TABLE III. Group A inspection for device type MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND V REF A3 V IC(POS) 1 GND GND 1 ma A3 1.5 V 2 A2 3 A1 4 A0 5 EN V IC(NEG) 6-1 ma A A2 8 A1 9 A0 10 EN I IH 2/ V 4.0 V A µa 12 GND A2 13 A1 14 A0 15 EN I IL 2/ V A V A2 18 A1 19 A0 20 EN I S(OFF) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 0.8 V IN na 3/ 22 IN2 23 IN3 24 IN4 25 IN5 26 IN6 27 IN7 28 IN V 4.0 V IN V -10 V IN V -10 V IN V -10 V IN V -10 V IN V -10 V IN V -10 V -10 V IN V -10 V -10 V -10 V IN V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 0.8 V IN1 38 IN2 39 IN3 40 IN4 41 IN5 42 IN6 43 IN7 44 IN V 4.0 V IN V 10 V IN V 10 V IN V 10 V IN V 10 V 10 V IN V 10 V 10 V 10 V IN14
41 TABLE III. Group A inspection for device type 02 Continued. 41 X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT V IC(POS) 1 1 ma A3 1.5 V 2 1 ma A2 3 1 ma A1 4 1 ma A0 5 EN V IC(NEG) 6-1 ma GND A ma A2 8-1 ma A1 9-1 ma A0 10 EN I IH 2/ 11 GND GND GND 15 V -15 V A µa V GND GND A2 13 GND 4.0 V GND A1 14 GND GND 4.0 V A0 15 GND GND GND 4.0 V EN I IL 2/ 16 5 V 5 V 5 V 5 V A V 5 V 5 V A V 0.8 V 5 V A V 5 V 0.8 V A V 5 V 5 V 0.8 V EN I S(OFF) V 0.8 V 0.8 V 10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V IN na 3/ V 4.0 V -10 V 10 V -10 V -10 V IN V 0.8 V -10 V 10 V -10 V IN V 4.0 V -10 V 10 V IN V 0.8 V 0.8 V -10 V 10 V IN V 4.0 V -10 V 10 V IN V 0.8 V -10 V 10 V IN V 4.0 V -10 V 10 V IN V 0.8 V 0.8 V -10 V IN V 4.0 V IN V 0.8 V IN V 4.0 V IN V 0.8 V 0.8 V IN V 4.0 V IN V 0.8 V IN V 4.0 V IN V 0.8 V 0.8 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V IN V 4.0 V 10 V -10 V 10 V 10 V IN V 0.8 V 10 V -10 V 10 V IN V 4.0 V 10 V -10 V IN V 0.8 V 0.8 V 10 V -10 V IN V 4.0 V 10 V -10 V IN V 0.8 V 10 V -10 V IN V 4.0 V 10 V -10 V IN V 0.8 V 0.8 V 10 V IN V 4.0 V IN V 0.8 V IN V 4.0 V IN V 0.8 V 0.8 V IN V 0.8 V 4.0 V IN14
42 TABLE III. Group A inspection for device type 02 Continued. 42 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND V REF A3 I S(OFF) V 10 V -10 V 10 V 10 V 10 V 10 V 10 V 10 V GND 4.0 V IN na 3/ V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 4.0 V IN I D(OFF) V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 0.8 V OUT V -10 V -10 V -10 V -10 V -10 V -10 V -10 V OUT I D(ON) 55 IN1 & OUT 56 IN2 & OUT 57 IN3 & OUT 58 IN4 & OUT 59 IN5 & OUT 60 IN6 & OUT 61 IN7 & OUT 62 IN8 & OUT V 4.0 V IN9 & OUT V -10 V IN10 & OUT V -10 V IN11 & OUT V -10 V IN12 & OUT V -10 V IN13 & OUT V -10 V IN14 & OUT V -10 V IN15 & OUT V -10 V IN16 & OUT V 0.8 V IN1 & OUT 72 IN2 & OUT 73 IN3 & OUT 74 IN4 & OUT 75 IN5 & OUT V 10 V 10 V 10 V 10 V 10 V 10 V 10 V IN6 & OUT V IN7 & OUT V IN8 & OUT V 4.0 V IN9 & OUT V 10 V IN10 & OUT V 10 V IN11 & OUT V 10 V IN12 & OUT V 10 V IN13 & OUT V 10 V IN14 & OUT V 10 V 10 V IN15 & OUT V 10 V 10 V 10 V IN16 & OUT I V V ma I- 88 V I+SBY 89 V I-SBY 90 V I D+(OFF) V OUT µa open 92 voltage V 4.0 V V 4.0 V
43 TABLE III. Group A inspection for device type 02 Continued. 43 X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT I S(OFF) V 4.0 V 0.8 V 0.8 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V -15 V 10 V IN na 3/ V 4.0 V 4.0 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V IN I D(OFF) V 0.8 V 0.8 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V -10 V OUT V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 10 V OUT I D(ON) V 4.0 V 10 V -10 V -10 V -10 V IN1 & OUT V -10 V 10 V -10 V -10 V IN2 & OUT V 0.8 V -10 V 10 V -10 V IN3 & OUT V 4.0 V -10 V 10 V IN4 & OUT V 0.8 V 0.8 V -10 V 10 V IN5 & OUT V 4.0 V -10 V 10 V IN6 & OUT V 0.8 V -10 V 10 V IN7 & OUT V 4.0 V -10 V 10 V IN8 & OUT V 0.8 V 0.8 V -10 V IN9 & OUT V 4.0 V IN10 & OUT V 0.8 V IN11 & OUT V 4.0 V IN12 & OUT V 0.8 V 0.8 V IN13 & OUT V 4.0 V IN14 & OUT V 0.8 V IN15 & OUT V 4.0 V IN16 & OUT V 0.8 V 0.8 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V -10 V IN1 & OUT V 4.0 V 10 V -10 V 10 V 10 V IN2 & OUT V 0.8 V 10 V -10 V 10 V IN3 & OUT V 4.0 V 10 V 10 V -10 V IN4 & OUT V 0.8 V 0.8 V 10 V 10 V 10 V -10 V IN5 & OUT V 4.0 V -10 V IN6 & OUT V 0.8 V -10 V IN7 & OUT V 4.0 V -10 V IN8 & OUT V 0.8 V 0.8 V IN9 & OUT V 4.0 V IN10 & OUT V 0.8 V IN11 & OUT V 4.0 V IN12 & OUT V 0.8 V 0.8 V IN13 & OUT V 4.0 V IN14 & OUT V 0.8 V IN15 & OUT V 4.0 V IN16 & OUT I V 0 V 0 V 5.0 V V ma I- 88 V I+SBY 89 0 V V I-SBY 90 V I D+(OFF) V 0.8 V 0.8 V 0.8 V 33 V 0 V OUT µa over V 33 V voltage V 0.8 V 33 V V 4.0 V 33 V V 0.8 V 0.8 V 33 V V 4.0 V 33 V V 0.8 V 33 V V 4.0 V 33 V V 0.8 V 0.8 V V 0.8 V 4.0 V
44 TABLE III. Group A inspection for device type 02 Continued. 44 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND V REF A3 I D+(OFF) V 33 V GND 4.0 V OUT µa over V voltage V V V V I D-(OFF) V over- 108 voltage V 4.0 V V V V V V V V R DS V IN1 & OUT kω 124 IN2 & OUT 125 IN3 & OUT 126 IN4 & OUT 127 IN5 & OUT 128 IN6 & OUT 129 IN7 & OUT 130 IN8 & OUT V 4.0 V IN9 & OUT V IN10 & OUT V IN11 & OUT V IN12 & OUT V IN13 & OUT V IN14 & OUT V IN15 & OUT V IN16 & OUT V IN1 & OUT 140 IN2 & OUT 141 IN3 & OUT 142 IN4 & OUT 143 IN5 & OUT 144 IN6 & OUT 145 IN7 & OUT 146 IN8 & OUT V 4.0 V IN9 & OUT V IN10 & OUT V IN11 & OUT V IN12 & OUT V IN13 & OUT V IN14 & OUT V IN15 & OUT V IN16 & OUT R DS2 155 thru 170 Same terminal conditions as tests 123 thru 138, except V± = ±10 V, V S = +7.5 V, and limits as shown R DS2 171 thru 186 Same terminal conditions as tests 139 thru 154, except V± = ±10 V, V S = -7.5 V, and limits as shown
45 TABLE III. Group A inspection for device type 02 Continued. 45 X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT I D+(OFF) V 4.0 V 0.8 V 0.8 V -15 V OUT µa over V 4.0 V 4.0 V voltage V 0.8 V 0.8 V V 4.0 V V 0.8 V V 4.0 V I D-(OFF) V 0.8 V 0.8 V -33 V over V 4.0 V -33 V voltage V 0.8 V -33 V V 4.0 V -33 V V 0.8 V 0.8 V -33 V V 4.0 V -33 V V 0.8 V -33 V V 4.0 V -33 V V 0.8 V 0.8 V V 4.0 V V 0.8 V V 4.0 V V 0.8 V 0.8 V V 4.0 V V 0.8 V V 4.0 V R DS V 0.8 V 0.8 V 4.0 V 10 V 100 µa IN1 & OUT kω V 4.0 V 10 V IN2 & OUT V 0.8 V 10 V IN3 & OUT V 4.0 V 10 V IN4 & OUT V 0.8 V 0.8 V 10 V IN5 & OUT V 4.0 V 10 V IN6 & OUT V 0.8 V 10 V IN7 & OUT V 4.0 V 10 V IN8 & OUT V 0.8 V 0.8 V IN9 & OUT V 4.0 V IN10 & OUT V 0.8 V IN11 & OUT V 4.0 V IN12 & OUT V 0.8 V 0.8 V IN13 & OUT V 4.0 V IN14 & OUT V 0.8 V IN15 & OUT V 4.0 V IN16 & OUT V 0.8 V 0.8 V -10 V -100 µa IN1 & OUT V 4.0 V -10 V IN2 & OUT V 0.8 V -10 V IN3 & OUT V 4.0 V -10 V IN4 & OUT V 0.8 V 0.8 V -10 V IN5 & OUT V 4.0 V -10 V IN6 & OUT V 0.8 V -10 V IN7 & OUT V 4.0 V -10 V IN8 & OUT V 0.8 V 0.8 V IN9 & OUT V 4.0 V IN10 & OUT V 0.8 V IN11 & OUT V 4.0 V IN12 & OUT V 0.8 V 0.8 V IN13 & OUT V 4.0 V IN14 & OUT V 0.8 V IN15 & OUT V 4.0 V IN16 & OUT R DS2 155 thru 170 Same terminal conditions as tests 123 thru 138, except V± = ±10 V, V S = +7.5 V, and limits as shown R DS2 171 thru 186 Same terminal conditions as tests 139 thru 154, except V± = ±10 V, V S = -7.5 V, and limits as shown
46 TABLE III. Group A inspection for device type 02 Continued. 46 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 4 V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND V REF A3 Min Max C A GND GND A3 10 pf 188 A2 189 A1 190 A0 C OS 191 OUT 85 C IS 192 IN IN2 194 IN3 195 IN4 196 IN5 197 IN6 198 IN7 199 IN / IN / IN / IN / IN / IN / IN / IN / IN16 C EN 208 Subgroup 9 Subgroup 10 T A = 125 C Subgroup 11 T A = -55 C t ON(A) V -10 V GND GND GND GND GND GND GND GND _/ ADDRESS 1,000 1,500 1,000 ns and fig V _/ IN TO OUT t OFF(A) V \_ V \_ 213 GND _/ 214 _/ 215 \_ 216 \_ t ON(EN) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V GND and fig V 10 V 10 V 10 V 10 V 10 V 10 V 10 V t OFF(EN) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V V 10 V 10 V 10 V 10 V 10 V 10 V 10 V
47 TABLE III. Group A inspection for device type 02 Continued. 47 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 4 A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT Min Max C A 187 GND A3 10 pf 188 4/ A / A / A0 C OS V 0 V 0 V 0 V 5/ OUT 85 C IS 192 4/ IN / IN / IN / IN / IN / IN / IN / IN8 200 IN V IN IN IN IN IN IN IN16 C EN 208 4/ GND EN Subgroup 9 Subgroup 10 T A = 125 C Subgroup 11 T A = -55 C t ON(A) 209 _/ _/ _/ 5 V GND GND GND GND GND GND GND GND -15 V OUT ADDRESS 1,000 1,500 1,000 ns and 210 _/ _/ _/ IN TO OUT t OFF(A) 211 \_ \_ \_ 212 \_ \_ \_ 213 _/ _/ _/ -10 V 214 _/ _/ _/ 10 V 215 \_ \_ \_ -10 V 216 \_ \_ \_ 10 V t ON(EN) 217 GND GND GND -10 V -10 V -10 V -10 V -10 V -10 V -10 V and V 10 V 10 V 10 V 10 V 10 V 10 V t OFF(EN) V -10 V -10 V -10 V -10 V -10 V -10 V V 10 V 10 V 10 V 10 V 10 V 10 V
48 TABLE III. Group A inspection for device type 02 Continued. MIL- STD-883 method X conditions 1/ Measured limits Subgroup 4 V+ NC NC IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 GND V REF A3 Min Max V ISO fig V IN IN IN IN IN IN IN IN GND GND OUT 50 db V CT fig V IN IN IN IN IN IN IN IN GND GND OUT 50 db V CTE fig V GND IN OUT 10 mv Subgroup 13 Min Max t D fig V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V GND _/ OUT 5 ns V -10 V -10 V -10 V -10 V -10 V -10 V -10 V _/ V 10 V 10 V 10 V 10 V 10 V 10 V 10 V \_ V -10 V -10 V -10 V -10 V -10 V -10 V -10 V \_ 48
49 TABLE III. Group A inspection for device type 02 Continued. MIL- STD-883 method X conditions 1/ Measured limits Subgroup 4 A2 A1 A0 EN IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 V- OUT Min Max V ISO 221 GND GND GND 0 V IN IN IN IN IN IN IN IN -15 V OUT OUT 50 db V CT 222 GND GND GND 5 V 6/ IN IN IN IN IN IN IN -15 V OUT OUT 50 db V CTE 223 IN IN IN 5 V GND OUT OUT 10 mv Subgroup 13 Min Max t D 224 _/ _/ _/ 5 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V -15 V OUT OUT 5 ns 225 _/ _/ _/ -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 226 \_ \_ \_ 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 227 \_ \_ \_ -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V MIL-M-38510/139C 49 42
50 TABLE III. Group A inspection for device type MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C V+ OUTB NC IN8B IN7B IN6B IN5B IN4B IN3B IN2B IN1B GND NC NC I IH 2/ V GND A µa 2 A1 3 A0 4 EN I IL 2/ A A1 7 A0 8 EN I S(OFF) 9-10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 10 V IN1B na 3/ V -10 V 10 V -10 V IN2B V 10 V -10 V IN3B V -10 V IN4B V -10 V IN5B V -10 V IN6B V -10 V IN7B V -10 V IN8B V IN1A 18 IN2A 19 IN3A 20 IN4A 21 IN5A 22 IN6A 23 IN7A 24 IN8A V 10 V 10 V 10 V 10 V 10 V 10 V 10 V IN1B V 10 V -10 V 10 V IN2B V -10 V 10 V IN3B V 10 V IN4B V 10 V IN5B V 10 V IN6B V 10 V IN7B V 10 V IN8B V IN1A 34 IN2A 35 IN3A 36 IN4A 37 IN5A 38 IN6A 39 IN7A 40 IN8A I D(OFF) 41 OUTA V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V OUTA V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V OUTB V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V OUTB I D(ON) V IN1A & OUTA 46 IN2A & OUTA 47 IN3A & OUTA 48 IN4A & OUTA 49 IN5A & OUTA 50 IN6A & OUTA MIL-M-38510/139C
51 TABLE III. Group A inspection for device type 03 Continued. 51 X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C A2 A1 A0 EN IN1A IN2A IN3A IN4A IN5A IN6A IN7A IN8A V- OUTA I IH 2/ V GND GND 5.0 V -15 V A µa 2 GND 2.4 V GND 5.0 V A1 3 GND GND 2.4 V 5.0 V A0 4 GND GND GND 4.5 V EN I IL 2/ V 5.0 V 5.0 V 5.0 V A V 0.8 V 5.0 V 5.0 V A V 5.0 V 0.8 V 5.0 V A V 5.0 V 5.0 V 0.8 V EN I S(OFF) V 0.8 V 0.8 V 0.8 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V IN1B na 3/ V 2.4 V IN2B V 0.8 V IN3B V 2.4 V IN4B V 0.8 V 0.8 V IN5B V 2.4 V IN6B V 0.8 V IN7B V 2.4 V IN8B V 0.8 V 0.8 V 10 V IN1A V 2.4 V -10 V 10 V IN2A V 0.8 V -10 V 10 V IN3A V 2.4 V -10 V 10 V IN4A V 0.8 V 0.8 V -10 V 10 V IN5A V 2.4 V -10 V 10 V IN6A V 0.8 V -10 V -10 V 10 V IN7A V 2.4 V -10 V -10 V -10 V 10 V IN8A V 0.8 V 0.8 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V IN1B V 2.4 V IN2B V 0.8 V IN3B V 2.4 V IN4B V 0.8 V 0.8 V IN5B V 2.4 V IN6B V 0.8 V IN7B V 2.4 V IN8B V 0.8 V 0.8 V -10 V IN1A V 2.4 V 10 V -10 V IN2A V 0.8 V 10 V -10 V IN3A V 2.4 V 10 V -10 V IN4A V 0.8 V 0.8 V 10 V -10 V IN5A V 2.4 V 10 V -10 V IN6A V 0.8 V 10 V -10 V IN7A V 2.4 V 10 V 10 V -10 V IN8A I D(OFF) V 0.8 V 0.8 V 10 V 10 V 10 V -10 V OUTA V -10 V -10 V -10 V -10 V -10 V -10 V -10 V 10 V OUTA V 10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V OUTB V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V OUTB I D(ON) V 10 V -10 V -10 V -10 V 10 V IN1A & OUTA V -10 V 10 V -10 V -10 V IN2A & OUTA V 0.8 V -10 V 10 V -10 V IN3A & OUTA V 2.4 V -10 V 10 V IN4A & OUTA V 0.8 V 0.8 V -10 V -10 V 10 V IN5A & OUTA V 0.8 V 2.4 V -10 V -10 V -10 V 10 V IN6A & OUTA
52 TABLE III. Group A inspection for device type 03 Continued. 52 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C V+ OUTB NC IN8B IN7B IN6B IN5B IN4B IN3B IN2B IN1B GND NC NC I D(ON) V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V -10 V GND IN7A & OUTA na V -10 V -10 V IN8A & OUTB V -10 V 10 V IN1B & OUTB V -10 V IN2B & OUTB V -10 V IN3B & OUTB V -10 V IN4B & OUTB V -10 V IN5B & OUTB V -10 V IN6B & OUTB V -10 V -10 V IN7B & OUTB V -10 V -10 V -10 V IN8B & OUTB V 10 V 10 V 10 V 10 V 10 V 10 V IN1A & OUTA 62 IN2A & OUTA 63 IN3A & OUTA 64 IN4A & OUTA 65 IN5A & OUTA 66 IN6A & OUTA 67 IN7A & OUTA 68 IN8A & OUTB V -10 V IN1B & OUTB V 10 V IN2B & OUTB V 10 V IN3B & OUTB V 10 V IN4B & OUTB V 10 V IN5B & OUTB V 10 V IN6B & OUTB V 10 V 10 V IN7B & OUTB V 10 V 10 V 10 V IN8B & OUTB I+ 77 V ma I- 78 V I+SBY 79 V I-SBY 80 V R DS1 81 IN1A & OUTA Ω V IN2A & OUTA V IN3A & OUTA V IN4A & OUTA V IN5A & OUTA V IN6A & OUTA V IN7A & OUTA V IN8A & OUTB 89 1 ma 10 V IN1B & OUTB 90 IN2B & OUTB 91 IN3B & OUTB 92 IN4B & OUTB 93 IN5B & OUTB 94 IN6B & OUTB 95 IN7B & OUTB 96 IN8B & OUTB 97 IN1A & OUTA 98 IN2A & OUTA 99 IN3A & OUTA 100 IN4A & OUTA
53 TABLE III. Group A inspection for device type 03 Continued. 53 MIL- STD-883 method X conditions 1/ Measured limits Subgroup 1 Subgroup 2 Subgroup 3 T A = 125 C T A = -55 C A2 A1 A0 EN IN1A IN2A IN3A IN4A IN5A IN6A IN7A IN8A V- OUTA I D(ON) V 2.4 V 0.8 V 4.5 V -10 V -10 V -10 V -10 V -10 V -10 V 10 V -10 V -15 V 10 V IN7A & OUTA na V 2.4 V 2.4 V 10 V 10 V IN8A & OUTB V 0.8 V 0.8 V -10 V IN1B & OUTB V 2.4 V IN2B & OUTB V 0.8 V IN3B & OUTB V 2.4 V IN4B & OUTB V 0.8 V 0.8 V IN5B & OUTB V 2.4 V IN6B & OUTB V 0.8 V IN7B & OUTB V 2.4 V IN8B & OUTB V 0.8 V 0.8 V -10 V 10 V 10 V 10 V 10 V 10 V 10 V 10 V IN1A & OUTA V 2.4 V 10 V -10 V 10 V 10 V IN2A & OUTA V 0.8 V 10 V -10 V 10 V IN3A & OUTA V 2.4 V 10 V -10 V IN4A & OUTA V 0.8 V 0.8 V 10 V -10 V IN5A & OUTA V 2.4 V 10 V -10 V IN6A & OUTA V 0.8 V 10 V -10 V IN7A & OUTA V 2.4 V 10 V -10 V IN8A & OUTB V 0.8 V 0.8 V 10 V 10 V IN1B & OUTB V 2.4 V IN2B & OUTB V 0.8 V IN3B & OUTB V 2.4 V IN4B & OUTB V 0.8 V 0.8 V IN5B & OUTB V 2.4 V IN6B & OUTB V 0.8 V IN7B & OUTB V 2.4 V IN8B & OUTB I V 0 V 0 V 5.0 V V ma I V V I+SBY 79 0 V V I-SBY 80 0 V V R DS V 0.8 V 0.8 V 4.5 V 10 V 1 ma IN1A & OUTA Ω V 10 V IN2A & OUTA V 0.8 V 10 V IN3A & OUTA V 2.4 V 10 V IN4A & OUTA V 0.8 V 0.8 V 10 V IN5A & OUTA V 2.4 V 10 V IN6A & OUTA V 0.8 V 10 V IN7A & OUTA V 2.4 V 10 V IN8A & OUTA V 0.8 V 0.8 V IN1B & OUTB V 2.4 V IN2B & OUTB V 0.8 V IN3B & OUTB V 2.4 V IN4B & OUTB V 0.8 V 0.8 V IN5B & OUTB V 2.4 V IN6B & OUTB V 0.8 V IN7B & OUTB V 2.4 V IN8B & OUTB V 0.8 V 0.8 V -10 V -1 ma IN1A & OUTA V 2.4 V -10 V IN2A & OUTA V 0.8 V -10 V IN3A & OUTA V 2.4 V -10 V IN4A & OUTA
MICROCIRCUITS, DIGITAL, TTL, FLIP-FLOPS, MONOLITHIC SILICON. Inactive for new design after 7 September 1995
MILITARY SPECIFICATION INCH-POUND MIL-M-38510/2G 8 February 2005 SUPERSEDING MIL-M-38510/2E 24 December 1974 MIL-M-0038510/2F (USAF) 24 OCTOBER 1975 MICROCIRCUITS, DIGITAL, TTL, FLIP-FLOPS, MONOLITHIC
More informationMILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, TTL, DECODERS MONOLITHIC SILICON. Inactive for new design after 7 September 1995.
INCH-POUND 16 February 2005 SUPERSEDING MIL-M-38510/10C 3 March 1986 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, TTL, DECODERS MONOLITHIC SILICON This specification is approved for use by all
More informationMILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, SCHOTTKY TTL, FLIP-FLOPS, CASCADABLE, MONOLITHIC SILICON
INCH-POUND 2 November 2005 SUPERSEDING MIL-M-38510/71C 23 July 1984 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, SCHOTTKY TTL, FLIP-FLOPS, CASCADABLE, MONOLITHIC SILICON This specification is
More informationMILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, TTL, MONOSTABLE MULTIVIBRATORS, MONOLITHIC SILICON
INCH-POUND MIL-M-38510/12J 22 February 2005 SUPERSEDING MIL-M-38510/12H 16 December 2003 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, TTL, MONOSTABLE MULTIVIBRATORS, MONOLITHIC SILICON This
More informationMICROCIRCUITS, DIGITAL, BIPOLAR LOW-POWER SCHOTTKY TTL, FLIP-FLOPS, CASCADABLE, MONOLITHIC SILICON. Inactive for new design after 18 April 1997.
INCH-POUND MIL-M-38510/301F 4 March 2004 SUPERSEDING MIL-M-38510/301E 14 February 2003 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR LOW-POWER SCHOTTKY TTL, FLIP-FLOPS, CASCADABLE, MONOLITHIC
More informationMICROCIRCUITS, DIGITAL, LOW-POWER SCHOTTKY TTL, COUNTERS, MONOLITHIC SILICON. Inactive for new design after 18 April 1997.
INCH-POUND MIL-M-38510/315D 27 October 2003 SUPERSEDING MIL-M-38510/315C 17 JANUARY 1984 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, LOW-POWER SCHOTTKY TTL, COUNTERS, MONOLITHIC SILICON This specification
More informationMILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, CMOS, STATIC SHIFT REGISTER, MONOLITHIC SILICON, POSITIVE LOGIC
MIITARY SPECIFICATION MICROCIRCUITS, DIGITA, CMOS, STATIC SIFT REGISTER, MONOITIC SIICON, POSITIVE OGIC This specification is approved for use by all Departments and Agencies of the Department of Defense.
More informationSTANDARD MICROCIRCUIT DRAWING MICROCIRCUIT, LINEAR, 4-CHANNEL DIFFERENTIAL, ANALOG MULTIPLEXER, MONOLITHIC SILICON
REVISIONS LTR DESCRIPTION DTE (YR-MO-D) PPROVED Update boilerplate paragraphs to current MIL-PRF-38535 requirements. Delete references to device class M requirements. - ro 12-10-29 C. SFFLE REV REV REV
More informationSTANDARD MICROCIRCUIT DRAWING MICROCIRCUIT, LINEAR, PRECISION TIMER, MONOLITHIC SILICON
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV REV 15 16 17 REV STATUS REV OF S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS
More informationReactivated after 17 Jan and may be used for new and existing designs and acquisitions.
C-POUND MI-M-38510/653 17 January 2006 SUPERSEDG MI-M-38510/653 15 January 1988 MIITRY SPECIFICTION MICROCIRCUITS, DIGIT, IG-SPEED CMOS, FIP-FOPS, MONOITIC SIICON, POSITIVE OGIC This specification is approved
More informationMICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, DECADE COUNTERS, MONOLITHIC SILICON
INCH-POUND MIL-M-38510/344A 14 April 2004 SUPERSEDING MIL-M-38510/344 12 June 1986 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR, ADVANCED SCHOTTKY TTL, DECADE COUNTERS, MONOLITHIC SILICON This
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. A Update to current requirements. Editorial changes throughout. - gap Raymond Monnin
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update to current requirements. Editorial changes throughout. - gap 06-10-05 Raymond Monnin Remove class M references. Update drawing to current MIL-PRF-38535
More informationReactivated after 10 Aug and may be used for new and existing designs and acquisitions.
INC-POUND 10 August 2004 SUPERSEDING MI-M-38510/175B 30 April 1984 MIITARY SPECIFICATION MICROCIRCUITS, DIGITA, CMOS, POSITIVE OGIC, FIP-FOPS AND MONOSTABE MUTIVIBRATOR, MONOITIC SIICON Reactivated after
More informationDevice Type Generic Number Circuit Function 01 DG406A(x)/883B 16-Channel Analog Multiplexer 02 DG407A(x)/883B Dual 8-Channel Analog Multiplexer
SCOPE: IMPROVED 6-CHANNEL/DUAL 8-CHANNEL, HIGH PERFORMANCE CMOS ANALOG MULTIPLEXER Device Type Generic Number Circuit Function 0 DG406A(x)/883B 6-Channel Analog Multiplexer DG407A(x)/883B Dual 8-Channel
More informationMILITARY SPECIFICATION MICROCIRCUITS, LINEAR, LOW OFFSET OPERATIONAL AMPLIFIERS, MONOLITHIC SILICON
INCH-POUND MIL-M-38510/135G 22 March 2010 SUPERSEDING MIL-M-38510/135F 8 April 2008 MILITARY SPECIFICATION MICROCIRCUITS, LINEAR, LOW OFFSET OPERATIONAL AMPLIFIERS, MONOLITHIC SILICON Reactivated after
More informationCase Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
+SCOPE: TTL COMPATIBLE CMOS ANALOG SWITCHES Device Type Generic Number 0 DG300A(x)/883B 02 DG30A(x)/883B 03 DG302A(x)/883B 04 DG303A(x)/883B Case Outline(s). The case outlines shall be designated in Mil-Std-835
More informationRadiation Performance Data Package MUX8522-S
March 15, 2010 Radiation Performance Data Package MUX8522-S MUX8522-S DSCC SMD Part Number: 5962-0923101KXC Dual 16 channel analog multiplexer, high impedance analog input. Prepared by: Aeroflex Plainview,
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. A Changes in accordance with N.O.R R M. A. FRYE
RVISIONS LTR DSCRIPTION DAT (YR-MO-DA) APPROVD A Changes in accordance with N.O.R. 5962-R163-92. 92-03-26 M. A. FRY B Changes in accordance with N.O.R. 5962-R228-94. 94-07-27 M. A. FRY C Drawing updated
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. A Drawing updated to reflect current requirements R. MONNIN
REVISIONS LTR DESRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. 02-11-20 R. MONNIN B Part of 5 year review update. -rrp 09-06-20 J. RODENBEK Update document paragraphs
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 REV STATUS OF SHEETS SHEET
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV REV 15 REV STATUS REV OF S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A MICROCIRCUIT DRAWING PREPARED BY Greg Cecil CHECKED BY Greg Cecil http://www.landandmaritime.dla.mil/
More informationHigh Speed Quad SPST CMOS Analog Switch
High Speed Quad SPST CMOS Analog Switch HI-21HS/883 The HI-21HS/883 is a monolithic CMOS analog switch featuring very fast switching speeds and low ON resistance. This integrated circuit consists of four
More informationCase Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
SCOPE: QUAD, SPST, HIGH SPEED ANALOG SWITCH Device Type Generic Number SMD Number DG44A(x)/883B 56-04MC DG44A(x)/883B 56-04MC Case Outline(s). The case outlines shall be designated in Mil-Std-835 and as
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
REVISIONS LTR DESRIPTION DATE (YR-MO-DA) APPROVED A Add conditions of I R = 15 ma for subgroups 2, 3 and make limit changes to the V R / T test as specified under Table I. - ro 11-03-24. SAFFLE B Add device
More informationRadiation Performance Data Package MUX8501-S
February 01, 2010 Radiation Performance Data Package MUX8501-S MUX8501-S DSCC SMD Part Number: 5962-0050202KXC 64 channel analog multiplexer, high impedance analog input with ESD protection Prepared by:
More informationSTANDARD MICROCIRCUIT DRAWING MICROCIRCUIT, LINEAR, CMOS 8-BIT DAC WITH OUTPUT AMPLIFIER, MONOLITHIC SILICON
REVISIONS LTR DESCRIPTION DTE (YR-MO-D) PPROVED Drawing updated to reflect current requirements. - ro 03-01-28 R. MONNIN REV REV REV STTUS REV OF S 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/ STNDRD MICROCIRCUIT
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. A Delete all match referenced tests as specified under Table I. - ro C.
REVISIONS LTR DESCRIPTION DTE (YR-MO-D) PPROVED Delete all match referenced tests as specified under Table I. - ro 16-04-04 C. SFFLE REV REV REV STTUS REV OF S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/
More informationMILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, CMOS 4096 BIT STATIC RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON
INCH POUND 23 JANUARY 2006 SUPERSEDING MIL-M-38510/289 4 DECEMBER 1986 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, CMOS 4096 BIT STATIC RANDOM ACCESS MEMORY (RAM) MONOLITHIC SILICON This specification
More informationMILITARY SPECIFICATION MICROCIRCUITS, LINEAR, 8 BIT, DIGITAL-TO-ANALOG CONVERTERS, MONOLITHIC SILICON
NCHPOUND October, 2011 SUPERSEDNG MLM8510/11B 21 June 2005 MLTARY SPECFCATON MCROCRCUTS, LNEAR, 8 BT, DGTALTOANALOG CONVERTERS, MONOLTHC SLCON This specification is approved for use by all Departments
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED R. HEBER devices back to the document. - ro
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A B Change the location of footnote 2/ under Table IIA in accordance with N.O.R. 5962-R038-97. Add case outline X, paragraph 1.5, and radiation hardened
More informationDLA LAND AND MARITIME COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, CMOS SPDT SWITCH, MONOLITHIC SILICON REVISIONS
REVISIONS LTR DESCRIPTION DTE PPROVED Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/ PREPRED BY RICK OFFICER
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. A Changes in accordance with NOR 5962-R Monica L.
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R020-98. 98-01-22 Monica L. Poelking Updated boilerplate and Appendix A. Editorial changes throughout. - tmh 00-05-09
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED SIZE A
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R015-98. 98-01-07 Monica L. Poelking Update boilerplate to MIL-PRF-38535 and updated appendix A. Editorial changes
More informationDATASHEET HI-390. Features. Ordering Information. Pinout Switch States shown for a Logic 1 Input. Applications. Functional Diagram
HI-39 Dual SPDT CMOS nalog Switch NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLCEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc DTSHEET FN7 Rev 1. ugust The Hl-39
More informationthroughout. --les. Raymond Monnin H Update to reflect latest changes in format and requirements. Correct
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED C Convert to military drawing format. Case E inactive for new design. Change V IL, t PLH1, t PHL1, and t PLH2. Delete minimum limits from I IL and propagation
More informationDG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118.
Data Sheet FN3118.4 SPST 4-Channel Analog Switch The is a low cost, CMOS monolithic, Quad SPST analog switch. It can be used in general purpose switching applications for communications, instrumentation,
More informationCase Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
SCOPE: CMOS, BUFFERED, MULTIPLYING 8-BIT D/A CONVERTER Device Type Generic Number Circuit Function 0 MX7528S(x)/883B DAC with ±4 LSB 02 MX7528T(x)/883B DAC with ±2 LSB 03 MX7528U(x)/883B DAC with ± LSB
More informationCMOS HIGHSPEED 8-BIT A/D CONVERTER WITH TRACK AND HOLD. Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
SCOPE: CMOS HIGHSPEED 8-BIT A/D CONVERTER WITH TRACK AND HOLD Device Type Generic Number 01 MX7824T(x)/883B 02 MX7824U(x)/883B Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and
More informationCase Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
SCOPE: CMOS, BUFFERED, MULTIPLYING 8-BIT D/A CONVERTER Type Generic Number Circuit Function 0 MX7528S(x)/883B DAC with ±4 LSB 02 MX7528T(x)/883B DAC with ±2 LSB 03 MX7528U(x)/883B DAC with ± LSB Case Outline(s).
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
EVISIONS LT DESCIPTION DATE (Y-MO-DA) APPOVED H J K Add vendors CAGE 07933, 04713, and 27014. Add device type 02. Inactive case D for new design. Change input offset current limit for +25 C. Change group
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. C Update boilerplate paragraph to current MIL-PRF requirements. - ro C.
REVISIONS LTR DESRIPTION DATE (YR-MO-DA) APPROVED A B Add device types 04, 05, and 06. Add case outlines D and H. Make changes to 1.3, table I, and figure 1. Replaced reference to MIL-STD-973 with reference
More informationMICROCIRCUIT, HYBRID, CMOS, LINEAR, ANALOG MULTIPLEXER, 64 CHANNEL, +3.3 TO +5 VOLT
REVISIONS LTR DESCRIPTION DTE (YR-MO-D) PPROVED REV REV 15 16 17 18 19 20 REV STTUS REV OF S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/ STNDRD MICROCIRCUIT DRWING THIS DRWING IS VILBLE FOR USE BY LL DEPRTMENTS
More informationSTANDARD MICROCIRCUIT DRAWING. MICROCIRCUIT, DIGITAL-LINEAR, BiCMOS, RADIATION HARDENED, NON-INVERTING QUAD DRIVER, MONOLITHIC SILICON
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add a footnote and make clarification changes to SET as specified under 1.5 and Table I. Add T C = +25 C to SEL, SE, and SET as specified under 1.5
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. A Add device type 02 and case outline Y. - ro C. SAFFLE SIZE A
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 02 and case outline Y. - ro 16-06-10 C. SAFFLE Make corrections under figure 2; for case outline X, pin 23, delete A3 and substitute
More informationMILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, SCHOTTKY TTL, ARITHMETIC LOGIC UNIT / FUNCTION GENERATORS, MONOLITHIC SILICON
C OUND MI-M-38510/78 7 September 2005 SUERSED MI-M-38510/78 6 JUNE 1984 MIITRY SECIFICTION MICROCIRCUITS, DIIT, SCOTTKY TT, RITMETIC OIC UNIT / FUNCTION ENERTORS, MONOITIC SIICON This specification is
More informationREVISIONS. A Changes made in accordance with NOR 5962-R thl Raymond L. Monnin
REVISIONS LTR ESCRIPTION ATE (YR-MO-A) APPROVE A Changes made in accordance with NOR 5962-R066-98. - thl 98-03-25 Raymond L. Monnin B Add device class T criteria. Editorial changes throughout. - jak 98-12-07
More informationQuad SPST CMOS Analog Switch
Quad PT CMO Analog witch HI-201/883 The HI-201/883 is a monolithic device comprised of four independently selectable PT switchers which feature fast switching speeds (185ns typical) combined with low power
More informationIH5341, IH5352. Dual SPST, Quad SPST CMOS RF/Video Switches. Description. Features. Ordering Information. Applications. Pinouts.
SEMICONDUCTOR IH, IH2 December Features Description Dual SPST, Quad SPST CMOS RF/Video Switches R DS(ON) < Ω Switch Attenuation Varies Less Than db From DC to 00MHz "OFF" Isolation > 0dB Typical at 0MHz
More informationDETAIL SPECIFICATION SHEET
INCH POUND MIL DTL 28803/1E 1 September 2018 SUPERSEDING MIL D 28803/1E 4 September 2013 DETAIL SPECIFICATION SHEET DISPLAY, OPTOELECTRONIC, SEGMENTED READOUT, BACKLIGHTED, STYLE II (LIGHT EMITTING DIODE),
More informationLow Power Quint Exclusive OR/NOR Gate
100307 Low Power Quint Exclusive OR/NOR Gate General Description The 100307 is monolithic quint exclusive-or/nor gate. The Function output is the wire-or of all five exclusive-or outputs. All inputs have
More informationNTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset
NTE74HC109 Integrated Circuit TTL High Speed CMOS, Dual J K Positive Edge Triggered Flip Flop w/set & Reset Description: The NTE74HC109 is a dual J K flip flip with set and reset in a 16 Lead plastic DIP
More information8-CHANNEL MULTIPLEXER DESCRIPTION: FEATURES: SEi 338RP
A0 1 16 A1 V+ V- GND EN V- NO1 NO2 NO3 SEi 338RP A2 GND V+ NO5 NO6 NO1 NO2 NO3 NO4 NO5 NO6 NO7 NO8 COM NO4 NO7 CMOS DECODE LOGIC COM 8 9 NO8 A2 A1A0 EN FEATURES: DESCRIPTION: RAD-PAK Technology hardened
More informationLC2 MOS 4-/8-Channel High Performance Analog Multiplexers ADG408/ADG409
a FEATURES 44 upply Maximum Ratings to Analog Signal Range Low On Resistance ( max) Low Power (I SUPPLY < 75 A) Fast Switching Break-Before-Make Switching Action Plug-in Replacement for G408/G409 APPLICATIONS
More informationDATASHEET HS Features. Pinouts. ARINC 429 Bus Interface Line Driver Circuit. FN2963 Rev 3.00 Page 1 of 7. May 30, FN2963 Rev 3.
DATASHEET ARI 429 Bus Interface Line Driver Circuit FN2963 Rev 3.00 The is a monolithic dielectric ally isolated bipolar differential line driver designed to meet the specifications of ARI 429. This device
More informationNC7SB3157 TinyLogic Low Voltage UHS Analog Switch 2-Channel Multiplexer/Demultiplexer (Preliminary)
September 1999 Revised November 1999 TinyLogic Low Voltage UHS Analog Switch 2-Channel Multiplexer/Demultiplexer (Preliminary) General Description The is a high performance, Analog Switch 2- channel CMOS
More informationINTEGRATED CIRCUITS. 74ALS11A Triple 3-Input AND gate. Product specification 1991 Feb 08 IC05 Data Handbook
INTEGRATED CIRCUITS Triple 3-Input AND gate 1991 Feb 08 IC05 Data Handbook TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 5.5ns 1.3mA PIN CONFIGURATION 1A 1 1B 2 14 13 V CC 1C ORDERING INFORMATION
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. B Add class T requirements. Update boilerplate. Redrawn. - rrp R.
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add paragraph 3.1.1 and add appendix A for microcircuit die. Changes in accordance with NOR 5962-R033-97. 96-11-06 R. MONNIN B Add class T requirements.
More informationDescription. For Fairchild s definition of Eco Status, please visit:
FSA2357 Low R ON 3:1 Analog Switch Features 10µA Maximum I CCT Current Over an Expanded Control Voltage Range: V IN=2.6V, V CC=4.5V On Capacitance (C ON): 70pF Typical 0.55Ω Typical On Resistance (R ON)
More information74HC4053; 74HCT4053. Triple 2-channel analog multiplexer/demultiplexer
Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A. The is triple
More informationNTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output
NTE74HC299 Integrated Circuit TTL High Speed CMOS, 8 Bit Universal Shift Register with 3 State Output Description: The NTE74HC299 is an 8 bit shift/storage register with three state bus interface capability
More informationORGANIZATION AND APPLICATION The MUX8523 consists of two independent 16 channel multiplexers arranged as shown in the block diagram.
Standard Products MUX8523 Dual 16-Channel Analog Multiplexer Module Radiation Tolerant & ESD Protected www.aeroflex.com/mux May 17, 2011 FEATURES 32-channels provided by two independent 16-channel multiplexers
More informationStandard Products ACT Channel Analog Multiplexer Module Radiation Tolerant & ESD Protected
Standard Products ACT8513 48-Channel Analog Multiplexer Module Radiation Tolerant & ESD Protected www.aeroflex.com/mux November 17, 2008 FEATURES 48 channels provided by three -channel multiplexers Radiation
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. C Add radiation hardened level L devices and delete figures 1 and 3. - ro R.
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A B Make changes to TR(tr), TR(os), SR+, SR-, NI(BB), NI(PC), CS tests as specified in table I, 1.5, 4.4.1b, and table II. - ro Add test conditions to
More informationImproved Quad CMOS Analog Switches
Improved Quad CMOS Analog Switches DG211B, DG212B DESCRIPTION The DG211B, DG212B analog switches are highly improved versions of the industry-standard DG211, DG212. These devices are fabricated in proprietary
More informationREVISIONS. A Changes in accordance with NOR 5962-R thl Monica L. Poelking
REVISIONS LTR DESRIPTION DATE (YR-MO-DA) APPROVED A hanges in accordance with NOR 5962-R195-97. - thl 97-02-28 Monica L. Poelking B hanges in accordance with NOR 5962-R431-97. rc 97-08-08 Raymond Monnin
More informationStandard Products ACT Channel Analog Multiplexer Module Radiation Tolerant & ESD Protected
Standard Products ACT8511 64-Channel Analog Multiplexer Module Radiation Tolerant & ESD Protected www.aeroflex.com/mux November 14, 2008 FEATURES 64-channels provided by four -channel multiplexers Radiation
More information74HC4051; 74HCT channel analog multiplexer/demultiplexer
Product data sheet 1. General description 2. Features 3. Applications The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The device is specified in compliance
More informationonlinecomponents.com
a FEATURES +.8 V to +. ingle Supply 2. V ual Supply 2. ON Resistance. ON Resistance Flatness pa Leakage Currents 4 ns Switching Times Single 6-to- Multiplexer AG76 ifferential 8-to- Multiplexer AG77 28-Lead
More informationDATASHEET ISL7457SRH. Features. Related Literature. Applications. Radiation Hardened, SEE Hardened, Non-Inverting, Quad CMOS Driver
DATASHEET ISL747SRH Radiation Hardened, SEE Hardened, Non-Inverting, Quad CMOS Driver FN6874 Rev.3.00 The ISL747SRH is a radiation hardened, SEE hardened, high speed, non-inverting, quad CMOS driver. It
More informationDLA LAND AND MARITIME COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, +5 V PROGRAMMABLE LOW DROPOUT VOLTAGE REGULATOR, MONOLITHIC SILICON
REVISIONS LTR DESCRIPTION DTE PPROVED Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/ PREPRED BY RICK OFFICER DL LND
More informationCD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits constructed
More informationHEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder
Rev. 06 25 November 2009 Product data sheet 1. General description 2. Features 3. Applications The is a 4-bit, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer.
More informationPERFORMANCE SPECIFICATION SHEET
The documentation and process conversion measures necessary to comply with this revision shall be completed by 21 August 2010. INCH-POUND MIL-PRF-19500/749B 21 May 2010 SUPERSEDING MIL-PRF-19500/749A 16
More informationDEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, DIGITAL, DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR, MONOLITHIC SILICON REVISIONS
REVISIONS LTR DESCRIPTION DTE PPROVED Update boilerplate to current MIL-PRF-38535 requirements. - PHN 14-06-24 Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME 43218-3990
More informationREVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. A Changes in accordance with NOR 5962-R Raymond L. Monnin
RVISIONS LTR DSCRIPTION DAT (YR-MO-DA) APPROVD A Changes in accordance with NOR 5962-R129-98. 98-07-14 Raymond L. Monnin B C D Update boilerplate to MIL-PRF-38535 and updated appendix A. ditorial changes
More informationCMOS, +1.8 V to +5.5 V/ 2.5 V, 2.5 Low-Voltage, 8-/16-Channel Multiplexers ADG706/ADG707 REV. A
a FEATURES +.8 V to +. ingle Supply. V ual Supply. ON Resistance. ON Resistance Flatness pa Leakage Currents ns Switching Times Single -to- Multiplexer AG ifferential 8-to- Multiplexer AG 8-Lead TSSOP
More information8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).
Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and
More informationDATASHEET CD40109BMS. Features. Description. Applications. Functional Diagram. Pinout. CMOS Quad Low-to-High Voltage Level Shifter
DATASHEET CD19BMS CMOS Quad Low-to-High Voltage Level Shifter Features High Voltage Type (V Rating) Independence of Power Supply Sequence Considerations - can Exceed - Input Signals can Exceed Both and
More informationDPDT CMOS Analog Switch
DPDT CMOS nalog Switch HI-5046/883 This CMOS analog switch offers low-resistance switching performance for analog voltages up to the supply rails and for signal currents up to 70m. ON resistance is low
More information1 pc Charge Injection, 100 pa Leakage CMOS 5 V/5 V/3 V 4-Channel Multiplexer ADG604
a FEATURES 1 pc Charge Injection (Over the Full Signal Range) 2.7 V to 5.5 V ual Supply 2.7 V to 5.5 ingle Supply Automotive Temperature Range: 4 C to +125 C 1 pa Max @ 25 C Leakage Currents 85 Typ On
More information2 Input NAND Gate L74VHC1G00
Input NAND Gate The is an advanced high speed CMOS input NAND gate fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining
More informationDS34C87T CMOS Quad TRI-STATE Differential Line Driver
DS34C87T CMOS Quad TRI-STATE Differential Line Driver General Description The DS34C87T is a quad differential line driver designed for digital data transmission over balanced lines The DS34C87T meets all
More information60 V, 0.3 A N-channel Trench MOSFET
Rev. 01 11 September 2009 Product data sheet 1. Product profile 1.1 General description ESD protected N-channel enhancement mode Field-Effect Transistor (FET) in a small SOT2 (TO-26AB) Surface-Mounted
More informationORGANIZATION AND APPLICATION The MUX8532 consists of two independent 16 channel multiplexers arranged as shown in the block diagram.
Standard Products MUX8532 Dual 16-Channel Analog Multiplexer Module Radiation Tolerant www.aeroflex.com/mux May 17, 2011 FEATURES 32-channels provided by two independent 16-channel multiplexers Radiation
More informationMAX14753 V DD INA0 INA1 INA2 INA3 OUT INB0 INB1 INB2 INB3
19-4255; Rev 3; 7/10 8-Channel/Dual 4-Channel General Description The are 8-to-1 and dual 4-to-1 high-voltage analog multiplexers. Both devices feature 60Ω (typ) on-resistance with 0.03Ω (typ) on-resistance
More informationUNISONIC TECHNOLOGIES CO., LTD L16B45 Preliminary CMOS IC
UNISONIC TECHNOLOGIES CO., LTD L16B45 Preliminary CMOS IC 16-BIT CONSTANT CURRENT LED SINK DRIVER DESCRIPTION The UTC L16B45 is designed for LED displays. UTC L16B45 contains a serial buffer and data latches
More informationCD4013BC Dual D-Type Flip-Flop
Dual D-Type Flip-Flop General Description The CD4013B dual D-type flip-flop is a monolithic complementary MOS (CMOS) integrated circuit constructed with N- and P-channel enhancement mode transistors. Each
More informationN-Channel Enhancement-Mode Vertical DMOS FET
N-Channel Enhancement-Mode Vertical DMOS FET Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability Integral
More informationThe 74LV08 provides a quad 2-input AND function.
Quad 2-input ND gate Rev. 03 6 pril 2009 Product data sheet. General description 2. Features 3. Ordering information The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC0
More informationMM74HC74A Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part.
More information74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting
3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible
More information5-stage Johnson decade counter
Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
More informationCD40174BC CD40175BC Hex D-Type Flip-Flop Quad D-Type Flip-Flop
Hex D-Type Flip-Flop Quad D-Type Flip-Flop General Description The CD40174BC consists of six positive-edge triggered D- type flip-flops; the true outputs from each flip-flop are externally available. The
More informationCD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,
More informationFeatures Y Wide analog input voltage range g6v. Y Low on resistance 50 typ (VCC V EE e4 5V) Y Logic level translation to enable 5V logic with g5v
74VHC4051 8-Channel Analog Multiplexer 74VHC4052 Dual 4-Channel Analog Multiplexer 74VHC4053 Triple 2-Channel Analog Multiplexer General Description These multiplexers are digitally controlled analog switches
More informationMM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer
MM74C150 MM82C19 16-Line to 1-Line Multiplexer 3-STATE 16-Line to 1-Line Multiplexer General Description The MM74C150 and MM82C19 multiplex 16 digital lines to 1 output. A 4-bit address code determines
More informationCD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders
CD4514BC CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS (CMOS) circuits constructed
More informationDual 3-channel analog multiplexer/demultiplexer with supplementary switches
with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer
More informationDATASHEET HI-518. Features. Ordering Information. Applications. Pinout. 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer
DATASHEET HI-518 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer F3147 Rev 4.00 The Hl-518 is a monolithic, dielectrically isolated, high speed, high performance CMOS analog multiplexer.
More informationMM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation
More informationThe 74HC21 provide the 4-input AND function.
Rev. 03 12 November 2004 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with low-power Schottky TTL (LSTTL).
More information