Reactivated after 10 Aug and may be used for new and existing designs and acquisitions.

Transcription

1 INC-POUND 10 August 2004 SUPERSEDING MI-M-38510/175B 30 April 1984 MIITARY SPECIFICATION MICROCIRCUITS, DIGITA, CMOS, POSITIVE OGIC, FIP-FOPS AND MONOSTABE MUTIVIBRATOR, MONOITIC SIICON Reactivated after 10 Aug and may be used for new and existing designs and acquisitions. This specification is approved for use by all Departments And Agencies of the Department of Defense. The requirements for acquiring the product herein shall consist of this specification sheet and MI-PRF SCOPE 1.1 Scope. This specification covers the detail requirements for monolithic silicon, CMOS, logic microcircuits. Two product assurance classes and a choice of case outlines, lead finishes, and radiation hardness assurance (RA) are provided and are reflected in the complete Part or Identifying Number (PIN). For this product, the requirements of MI-M have been superseded by MI-PRF (see 6.3). 1.2 Part or identifying number (PIN). The PIN is in accordance with MI-PRF and as specified herein Device types. The device types are as follows: Device type Circuit 01 4-bit D-type register 02 Gated J K master-slave flip-flop (noninverting J K) 03 Gated J K master-slave flip-flop (inverting J K) 04 Dual monostable multivibrator 05 ex D-type flip-flop Device class. The device class is the product assurance level as defined in MI-PRF Comments, suggestions, or questions on this document should be addressed to: Commander, Defense Supply Center Columbus, ATTN: DSCC-VAC, P.O. Box 3990, Columbus, O , or CMOS@dscc.dla.mil. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at AMSC N/A FSC 5962

2 1.2.3 Case outlines. The case outlines are as designated in MI-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style A GDFP5-F14 or CDFP6-F14 14 Flat pack C GDIP1-T14 or CDIP2-T14 14 Dual-in-line D GDFP1-F14 or CDFP2-F14 14 Flat pack E GDIP1-T16 or CDIP2-T16 16 Dual-in-line F GDFP2-F16 or CDFP3-F16 16 Flat pack N CDFP4-F16 16 Flat pack X 1/ 2/ GDFP5-F14 or CDFP6-F14 14 Flat pack, except A dimension equals (2.54 mm) max Y 1/ 2/ GDFP1-F14 or CDFP2-F14 14 Flat pack, except A dimension equals (2.54 mm) max Z 1/ 2/ GDFP2-F16 or CDFP3-F16 16 Flat pack, except A dimension equals (2.54 mm) max 1.3 Absolute maximum ratings. Supply voltage range (V DD - V SS) V dc to V dc Input current (each input)... ±10 ma Input voltage range... (V SS V) V I (V DD V) Storage temperature range (T STG) to +175 C Maximum power dissipation (P D) mw ead temperature (soldering, 10 seconds) C Thermal resistance, junction to case (Θ JC)... See MI-STD-1835 Junction temperature (T J) C 1.4 Recommended operating conditions. Supply voltage range (V DD - V SS) V dc to.0 V dc Input low voltage range (V I)... V O = 10% V DD, V O = 90% V DD 0.0 V to 1.5 V V DD = 5.0 V dc 0.0 V to 2.0 V V DD = 10.0 V dc 0.0 V to 4.0 V V DD =.0 V dc Input high voltage range (V I)... V O = 10% V DD, V O = 90% V DD 3.5 V to 5.0 V V DD = 5.0 V dc 8.0 V to 10.0 V V DD = 10.0 V dc 11.0 V to.0 V V DD =.0 V dc Operating temperature range (T A) C to +125 C Minimum value of external resistance (Rx)... 5 kω Maximum value of external capacitance (Cx) µf 1/ As an exception to the nickel plate and undercoating paragraph of MI-PRF-38535, appendix A, for case outlines X, Y, and Z only, the leads of bottom brazed ceramic packages (i.e., configuration 2 of case outlines A, D, and F) may have electroless nickel undercoating which is 50 to 200 microinches (1.27 to 5.08 µm) thick provided the lead finish is hot solder dip (i.e., finish letter A) and provided that, after any lead forming, an additional hot solder dip coating is applied which extends from the outer tip of the lead to no more than 0.0 inch (0.38 mm) from the package edge. 2/ For bottom or side brazed packages, case outlines X, Y, and Z only, the S 1 dimension may go to.000 inch (.00 mm) minimum. 2

3 2. APPICABE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3, 4, or 5 of this specification. This section does not include documents cited in other sections of this specification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirements of documents cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 Government documents Specifications and Standards. The following specifications and standards form a part of this specification to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MI-PRF Integrated Circuits (Microcircuits) Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MI-STD Test Method Standard Microcircuits. MI-STD Interface Standard Electronic Component Case Outlines. (Copies of these documents are available online at or or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA ) 2.3 Order of precedence. In the event of a conflict between the text of this document and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Qualification. Microcircuits furnished under this specification shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listing on the applicable qualified manufacturers list before contract award (see 4.3 and 6.4). 3.2 Item requirements. The individual item requirements shall be in accordance with MI-PRF and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.3 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MI-PRF and herein. Although eutectic die bonding is preferred, epoxy die bonding may be performed. owever, the resin used shall be Dupont 5504 Conductive Silver Paste, or equivalent, which is cured at 200 C ±10 C for a minimum of 2 hours. The use of equivalent epoxies or cure cycles shall be approved by the qualifying activity. Equivalency shall be demonstrated in data submitted to the qualifying activity for verification Terminal connections. The terminal connections shall be as specified on figure ogic diagrams The logic diagrams shall be as specified on figure Truth tables. The truth tables shall be as specified on figure Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure Schematic circuits. The schematic circuits shall be maintained by the manufacturer and made available to the qualifying activity or preparing activity upon request Case outlines. The case outlines shall be as specified in ead material and finish. The lead material and finish shall be in accordance with MI-PRF (see 6.6). 3.5 Electrical performance characteristics. Unless otherwise specified, the electrical performance characteristics are as specified in table I, and apply over the full recommended ambient operating temperature range,. 3

4 3.6 Electrical test requirements. The electrical test requirements for each device class shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table III. 3.7 Marking. Marking shall be in accordance with MI-PRF Radiation hardness assurance identifier. The radiation hardness assurance identifier shall be in accordance with MI-PRF and herein. 3.8 Microcircuit group assignment. The devices covered by this specification shall be in microcircuit group number 38 (see MI-PRF-38535, appendix A). 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MI-PRF or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MI-PRF and shall be conducted on all devices prior to qualification and conformance inspection. The following additional criteria shall apply: a. The burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MI-PRF The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MI-PRF and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 10 of MI-STD-883. b. Delete the sequence specified as interim (pre-burn-in) electrical parameters through interim (post-burn-in) electrical parameters of table IA of MI-PRF and substitute lines 1 through 7 of table II herein. c. Burn-in (method 10 of MI-STD-883). (1) Unless otherwise specified in the manufacturers QM plan for static tests (test condition A), ambient temperature (T A) shall be +125 C minimum. Test duration for each static test shall be 24 hours minimum for class S devices and in accordance with table I of method 10 for class B devices. i. For static burn-in I, all inputs shall be connected to 0.0 V. ii. For static burn-in II, all inputs shall be connected to V DD. V DD = V minimum and 18 V maximum. iii. Except for V DD and V SS, the terminal shall be connected through resistors whose value is 2 kω to 47 kω. The actual measured value of the resistor selected shall not exceed ±20% of its branded value due to use, heat or age. iv. Output may be open or connected to V DD/2. v. Terminals 2 and 14 shall each be connected to V DD through separate 2 kω to 47 kω resisitors. This requirement is only applicable to device type 04. (2) Unless otherwise specified in the manufacturers QM plan for dynamic test (test condition D), ambient temperature shall be +125 C minimum. Test duration shall be in accordance with table I of method 10. i. Except for V DD and V SS, the terminals shall be connected through resistors whose value is 2 kω to 47 kω. The actual measured value of the resistor selected shall not exceed ±20% of its branded value due to use, heat or age. ii. Input signal requirements: Square wave, 50% duty cycle; 25 kz < PRR < 1 Mz; t T and t T < 1 µs. Voltage level: 0 to V minimum to 18 V maximum peak. iii. For device type 05, positive transition of F occurs at center of F/2. d. Interim and final electrical test parameters shall be as specified in table II. e. For class S devices, post dynamic burn-in, or class B devices, post static burn-in, electrical parameter measurements may, at the manufacturer s option, be performed separately or included in the final electrical parameter requirements. 4

5 Positive clamping input to V DD TABE I. Electrical performance characteristics. Test Symbol Conditions V SS = 0 V -55 C T A +125 C Unless otherwise specified Negative clamping input to V SS Quiescent supply current V IC (POS) V IC (NEG) I SS or I DD T A = +25 C, V DD = V SS = Open, Output = Open I IN = 1 ma T A = +25 C, V DD = V SS =, Output = Open I IN = -1 ma V DD = 18 V dc V IN = V SS or V DD All input combinations Device imits type Min Max Unit All 1.5 V dc All -6.0 V dc All -2.5 µa igh level output voltage V O1 V DD = Vdc, see table III I 0 1 µa All V dc ow level output voltage V O1 V DD = Vdc, see table III All 0.05 V dc I 0 1 µa Three-state output leakage current I OC1 V DD = 18 Vdc V 0 = V SS na I OC2 V DD = 18 Vdc V 0 = V DD na Input high voltage V I1 V DD = 5 V dc see table III I O 1µA All 3.5 V dc Input low voltage Output high (source) current V I2 V I3 V I1 V I2 V I3 I O1 I O2 V DD = 10 V dc see table III I O 1µA V DD = V dc see table III I O 1µA V DD = 5 V dc see table III I O 1µA V DD = 10 V dc see table III I O 1µA V DD = V dc see table III I O 1µA V DD = 5 V dc V IN = V DD V O = 4.6 V dc VDD = V dc V IN = V DD V O = 13.5 V dc All 7.0 V dc All 11.0 V dc All 1.5 V dc All 3.0 V dc All 4.0 V dc All ma dc All -2.4 ma dc 5

6 TABE I. Electrical performance characteristics Continued. Output low (sink) current Input leakage 1/ current, high Input leakage 1/ current, low Test Symbol Conditions V SS = 0 V -55 C T A +125 C Unless otherwise specified I O1 I O2 I I I I V DD = 5 V dc see table III V O = 0.4 V dc V DD = V dc see table III V O = 1.5 V dc V DD = 18 V dc Measure inputs sequentially Connect all unused inputs to V DD or V SS V DD = 18 V dc Measure inputs sequentially Connect all unused inputs to V DD or V SS Input capacitance C i V DD = 0 V dc, f = 1 Mz, T A = 25 C Propagation delay times, COCK to output, high to low level and low to high level t P1, t P1 V DD = 5 V dc, C = 50 pf R = 200 kω (See figure 4) Device imits type Min Max Unit All 0.36 ma dc All 2.4 ma dc 01, 02, 03, , 02, 03, na na 02, 03, 7.5 pf 04 01, 05 pf , 03, ns V DD = 10 V dc, C = 50 pf R = 200 kω T A = +25 C (See figure 4) 01,02, ns Propagation delay times, RESET, SET, or CEAR to output, high to low level and low to high level t P2, t P2 2/ V DD = 5 V dc, C = 50 pf R = 200 kω (See figure 4) , 03, ns V DD = 10 V dc, C = 50 pf R = 200 kω T A = +25 C (See figure 4) , ns / Input current of one input node. 2/ Device types 01 and 05 do not have a t P2 test. 6

7 TABE I. Electrical performance characteristics Continued. Transition times, high to low level and low to high level Test Symbol Conditions V SS = 0 V -55 C T A +125 C Unless otherwise specified Three-state output propagation delay times, output high to high impedance output low to high impedance high impedance to output low t T, t T t PZ t PZ t PZ V DD = 5 V dc, C = 50 pf R = 200 kω (See figure 4) see table III for device type 04 V DD = 10 V dc, C = 50 pf R = 200 kω T A = +25 C, (See figure 4) see table III for device type 04 V DD = 5.0 Vdc, C = 50 pf R = 200 kω (see figure 4) Device imits Unit type Min Max All ns All ns ns high impedance to output high t PZ Three-state output propagation output high to high impedance output low to high impedance t PZ t PZ V DD = 10.0 Vdc, C = 50 pf R = 200 kω (see figure 4) ns high impedance to output low t PZ high impedance to output high t PZ Minimum COCK transition times, high to low level and low to high level t r(ck), t f(ck) V DD = 5.0 Vdc, C = 50 pf R = 200 kω (see figure 4) 01, 02, 03, 05 µs Minimum data setup times, high to low level and low to high level Minimum data hold times, high to low level and low to high level Minimum pulse width, RESET Minimum pulse width, SET Minimum pulse width, COCK Minimum pulse width, CEAR t S, t S t, t t P(R) t P(S) t P(CK) t P(CR) V DD = 5.0 Vdc, C = 50 pf R = 200 kω (see figure 4) V DD = 5.0 Vdc, C = 50 pf R = 200 kω (see figure 4) , V DD = 5.0 Vdc, C = 50 pf R = 200 kω (see figure 4) 02, V DD = 5.0 Vdc, C = 50 pf R = 200 kω (see figure 4) V DD = 5.0 Vdc, C = 50 pf 01, R = 200 kω (see figure 4) 02, V DD = 5.0 Vdc, C = 50 pf R = 200 kω (see figure 4) Minimum COCK frequency f CK V DD = 5.0 Vdc, C = 50 pf R = 200 kω (see figure 4) , ns ns ns 7

8 FIGURE 1. Terminal connections. 8

9 FIGURE 2. ogic diagrams. 9

10 NOTES: Input to output is: a. A bi-directional low impedance state exists when the control input 1 is low and the control input is 2 is high. b. An open circuit state exists when the control input 1 is high and the control input 2 is low. FIGURE 2. ogic diagrams Continued. 10

11 NOTES: Input to output is: a. A bi-directional low impedance state exists when the control input 1 is low and the control input 2 is high. b. An open circuit state exists when the control input 1 is high and the control input 2 is low. FIGURE 2. ogic diagrams Continued. 11

12 NOTE: Schematic shown is 1/2 of the total package. Terminals 1, 8, and are electrically connected internally. FIGURE 2. ogic diagrams Continued. 12

13 FIGURE 2. ogic diagrams Continued. 13

14 Device type 01 Truth table Data input RESE COC disable Data Output next state T K G1 G2 D Q X X X X X X X Q NC X X Q NC X X Q NC X X X Q NC X X X Q NC When either output disable M or N is high, the outputs are disabled (high impedance state); however sequential operation of the flip-flops is not affected. = igh level voltage = ow level voltage = ow-to-high transition of the clock = igh-to-low transiton of the clock X = Don t care Device type 02 and 03 Synchronous operation Asynchronous operation (S = 0, R = 0) (J and K don t care) Inputs before positive clock transition Truth table Outputs after positive clock transition Truth table Inputs Outputs S R Q Q Inputs Outputs NC NC J * K * Q Q NC NC Toggles * Device type 02 For device type 02 J = J1 J2 J3 K = K1 K2 K3 For device type 03 J = J1 J2 J3 K = K1 K2 K3 = high level voltage = ow level voltage NC = No change FIGURE 3. Truth tables. 14

15 Device type 04 Truth table Inputs Outputs +Trigger -Trigger RESET Q Q Rx-Cx N/C N/C N/C N/C Device type 05 Truth table for 1 of 6 flip-flops Inputs Output COCK Data CEAR Q X N/C X X = igh level voltage = ow level voltage = ow-to-high transition of the clock = igh-to-low transition of the clock X = Don t care N/C = No change FIGURE 3. Truth tables Continued.

16 NOTES: 1. Pulse generator number 1 has the following characteristics: V GEN = V DD ±1%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns and PRR = 200 kz. 2. Pulse generators number 2 have the following characteristics: V GEN = V DD ±1%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns and PRR = 100 kz. 3. Requirements for minimum clock frequency (f C), t r, t f, t S, t S, t p(c), and t p(r) are established by setting the parameter to the limits given in table III and observing proper output state change. 4. Complete terminal conditions are as specified in table III. 5. For the t PZ and t PZ measurements, the output is tied to V DD through a 1 kω resistor. 6. For the t PZ and t PZ measurements, the output is tied to V SS through a 1 kω resistor. FIGURE 4. Switching waveforms and test circuit. 16

17 NOTES: 1. Pulse generator number 1 has the following characteristics: V GEN = V DD ±1%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns and PRR = 200 kz. 2. Pulse generators number 2 have the following characteristics: V GEN = V DD ±1%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns and PRR = 100 kz. 3. Requirements for minimum clock frequency (f CK), t r, t f, t p(ck), t p(r), t S, and t S are established by setting the parameter to the limits given in table III and observing proper output state change. 4. Complete terminal conditions are as specified in table III. FIGURE 4. Switching waveforms and test circuit Continued. 17

18 NOTES: 1. Pulse generator number 1 has the following characteristics: V GEN = V DD ±1%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns, and PRR = 200 kz. 2. Pulse generators number 2 have the following characteristics: V GEN = V DD ±1%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns and PRR = 100 kz. 3. Requirements for minimum clock frequency (f CK), t r, t f, t p(ck), t p(r), t S, and t S are established by setting the parameter to the limits given in table III and observing proper output state change. 4. Complete terminal conditions are as specified in table III. FIGURE 4. Switching waveforms and test circuit Continued. 18

19 NOTES: 1. Pulse generator number 1 has the following characteristics: V GEN = V DD ±1.0%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns and PRR = 200 kz. 2. Pulse generators number 2 have the following characteristics: V GEN = V DD ±1.0%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns and delayed 2.0 µs after pulse generator number Complete terminal conditions are as specified in table III. FIGURE 4. Switching waveforms and test circuit Continued. 19

20 NOTES: 1. Pulse generator number 1 has the following characteristics: V GEN = V DD ±1.0%, t p as specified in +TR and TR waveforms, t r and t f = 20 ±2 ns and PRR = 877 kz. 2. Pulse generator number 2 has the following characteristics: V GEN = V DD ±1.0%, t r and t f = 20 ±2 ns and PRR = 877 kz. 3. Identical switching measurements are obtained from mono 1 and mono Complete terminal conditions are as specified in table III. FIGURE 4. Switching waveforms and test circuit Continued. 20

21 NOTES: 1. Pulse generator number 1 has the following characteristics: V GEN = V DD ±1%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns, and PRR = 200 kz. 2. Pulse generators number 2 have the following characteristics: V GEN = V DD ±1%, t P = 1.0 ±0.1 µs, t r and t f = 20 ±2 ns, and PRR = 100 kz. 3. Requirements for minimum clock frequency (f CK), t r, t f, t p(ck), t p(cr), t S, t S, t, and t are established by setting the parameter to the limits given in table III and observing proper output state change. 4. Identical switching measurements are obtained from flip flop 1 thru Complete terminal conditions are as specified in table III. FIGURE 4. Switching waveforms and test circuit Continued. 21

22 TABE II. Electrical test requirements. ine no. MI-PRF test requirements Ref. par. Class S device 1/ Class B device 1/ Table III Ref. Table III Subgroups par. subgroups 2/ 2/ Table IV delta limits 3/ Table IV delta limits 3/ 1 Interim electrical parameters Static burn-in I (method 10) 4.2c Same as line Static burn-in II 4.2c 4.2c 4/ (method 10) Same as line 1 4.2e 1* 4.2e 1* 6 Dynamic burn-in (method 10) 4.2c Same as line 1 4.2e 1* 8 Final electrical parameters (method 5004) 1*, 2, 3, 7, 9 1*, 2, 3, 7, 9, 10, 11 9 Group A test requirements (method 5005) 10 Group B test when using method 5005 QCI option 11 Group C endpoint electrical parameters (method 5005) 12 Group D endpoint electrical parameters (method 5005) 1/ Blank spaces indicate tests are not applicable , 2, 3, 4, 7, 8, 9, 10, 11, , 2, 3, 9, 10, 11 2/ * indicates PDA applies to subgroup 1 (see 4.2.1) , 2, 3, 4, 7, , 2, , 2, , 2, 3 3/ indicates delta limits shall be required only on table III subgroup 1, where specified, and the delta values shall be computed with reference to the previous interim electrical parameters. 4/ The device manufacturer may at his option either perform delta measurements or within 24 hours after burn-in (or removal of bias) perform the final electrical parameter measurements. 22

23 4.2.1 Percent defective allowable (PDA). a. The PDA for class S devices shall be 5 percent for static burn-in and 5 percent for dynamic burn-in, based on the exact number of devices submitted to each separate burn-in. b. Static burn-in I and II failure shall be cumulative for determining the PDA. c. The PDA for class B devices shall be in accordance with MI-PRF for static burn-in. Dynamic burn-in is not required. d. Those devices whose measured characteristics, after burn-in, exceed the specified delta ( ) limits or electrical parameter limits specified in table III, subgroup 1, are defective and shall be removed from the lot. The verified failures divided by the total number of devices in the lot initially submitted to burn-in shall be used to determine the percent defective for the lot and the lot shall be accepted or rejected based on the specified PDA. 4.3 Qualification inspection. Qualification inspection shall be in accordance with MI-PRF Technology Conformance inspection (TCI). Technology conformance inspection shall be in accordance with MI-PRF and herein for groups A, B, C, D, and E inspections (see through 4.4.5) Group A inspection. Group A inspection shall be in accordance with table III of MI-PRF and as follows: a. Tests shall be performed in accordance with table II herein. b. Subgroups 5 and 6 shall be omitted. c. Subgroup 4 (C I measurement) shall be measured only for initial qualification and after process or design changes that may affect input capacitance. Capacitance shall be measured between the designated terminal and V SS at a frequency of 1 Mz. d. Subgroup 12 shall be added to group A inspection requirements for class S devices using sample size series of (acceptance 0) and consist of the procedures, test conditions, and limits specified in table III. e. Subgroups 9 and 11 shall be measured only for initial qualification and after process or design changes which may affect dynamic performance Group B inspection. Group B inspection shall be in accordance with table II of MI-PRF Group C inspection. Group C inspection shall be in accordance with table IV of MI-PRF and as follows: a. End-point electrical parameters shall be as specified in table II herein. Delta limits shall apply only to subgroup 1 of group C inspection and shall consist of tests specified in table IV herein. b. The steady-state life test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MI-PRF The burn-in test circuit shall be maintained under document control by the device manufacturer's Technology Review Board (TRB) in accordance with MI-PRF and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of MI-STD

24 24 TABE III. Group A inspection for device type 01. Symbol MI- Cases STD- E,F,Z Symbol M N CK V SS G1 G2 D4 D3 D2 D1 R V DD method Test no. V IC 1 1 ma (pos) 2 1 ma 3 1 ma 4 1 ma 5 1 ma 6 1 ma 7 1 ma 8 1 ma 9 1 ma 10 1 ma V IC 11-1 ma (neg) 12-1 ma 13-1 ma 14-1 ma -1 ma 16-1 ma 17-1 ma 18-1 ma 19-1 ma 20-1 ma V O1 V O1 I SS 2/ /.0V.0V.0V.0V.0V.0V Measured terminal M N CK G1 G2 D4 D3 D2 D1 R M N CK G1 G2 D4 D3 D2 D1 R I OC11 34 All outputs together I OC21 35 All outputs together See footnotes at end of table. V SS Unit Subgroup 1 Subgroup 2 Subgroup 3 T A = 25 C T A = 125 C T A = -55 C 1.5 Vdc µa 100 na -100

25 TABE III. Group A inspection for device type 01 Continued. 25 Symbol I OC12 I OC22 V I1 MI- Cases STD- E,F,Z 883 method Test no M N CK V SS G1 G2 D4 D3 D2 D1 R V DD 1.5V 1.5V 14/ 1.5V 3.5V 1.5V 1.5V 3.5V 1.5V 3.5V 1.5V 3.5V 1.5V 3.5V 1.5V 3.5V 1.5V 1.5V 3.5V 1.5V 3.5V 1.5V 1.5V 1.5V 3.5V 1.5V 3.5V 1.5V 3.5V Measured terminal Subgroup 1 Subgroup 2 Subgroup 3 T A = 25 C T A = 125 C T A = -55 C Unit na Vdc See footnotes at end of device type 01.

26 TABE III. Group A inspection for device type 01 Continued. 26 Symbol MI- STD- 883 V I1 V I2 Cases E,F,Z Symbol M N CK V SS G1 G2 D4 D3 D2 D1 R V DD method Test no V 1.5V 14/ 1.5V 1.5V 3.5V 3.5V 3.5V 3.5V 1.5V V V V 1.5V V 1.5V 1.5V V 3.5V 3.5V 3.5V V V 1.5V V 3.5V 1.5V V 3.5V 3.5V 1.5V V 3.0V / 3.0V 7.0V 3.0V 3.0V 7.0V 3.0V 7.0V 3.0V 7.0V 3.0V 7.0V 3.0V 7.0V 3.0V 3.0V 7.0V 3.0V 7.0V 3.0V 3.0V 3.0V 7.0V 3.0V 7.0V 3.0V 7.0V 10.0V Measured terminal Subgroup 1 Subgroup 2 Subgroup 3 T A = 25 C T A = 125 C T A = -55 C Unit Vdc See footnotes at end of device type 01.

27 TABE III. Group A inspection for device type 01 Continued. 27 Symbol V I2 MI- Cases STD- E,F,Z 883 method Test no M N CK V SS G1 G2 D4 D3 D2 D1 R V DD 3.0V 3.0V / 3.0V 3.0V 3.0V 7.0V 3.0V 7.0V 7.0V 3.0V 7.0V 3.0V 3.0V 3.0V 7.0V 7.0V 3.0V 7.0V 3.0V 3.0V 7.0V 7.0V 3.0V 7.0V 3.0V 7.0V 3.0V 10.0V Measured terminal Subgroup 1 T A = 25 C Subgroup 2 T A = 125 C Subgroup 3 T A = -55 C Unit Vdc See footnotes at end of device type 01.

28 TABE III. Group A inspection for device type 01 Continued Cases E,F,Z M N CK V SS G1 G2 D4 D3 D2 D1 R V DD Subgroup 1 T A = 25 C Subgroup 2 T A = 125 C Subgroup 3 T A = -55 C Symbol MI- STD- 883 method Test no. Measured terminal Unit V I V 4.0V 16/ 4.0V 11.0V 4.0V 4.0V 11.0V 4.0V 11.0V 4.0V 11.0V 4.0V 11.0V 4.0V 11.0V 4.0V 4.0V 11.0V 4.0V 11.0V 4.0V 4.0V 4.0V 11.0V 4.0V 11.0V 4.0V 11.0V.0V Vdc V I V 11.0V 4.0V 11.0V 4.0V 11.0V 4.0V 4.0V 4.0V 11.0V 4.0V 11.0V 4.0V 4.0V 11.0V 4.0V 11.0V 4.0V 11.0V 4.0V See footnotes at end of device type

29 29 Symbol MI- STD- 883 I I1 3/ I I2 I I1 3/ I I2 Cases E,F,Z TABE III. Group A inspection for device type 01 Continued M N CK V SS G1 G2 D4 D3 D2 D1 R V DD Measured terminal method Test no All outputs together M N CK G1 G2 D4 D3 D2 D1 R All outputs together See footnotes at end of device type 01. M N CK G1 G2 D4 D3 D2 D1 R Unit Subgroup 1 Subgroup 2 Subgroup 3 T A = 25 C T A = 125 C T A = -55 C 10 na

30 TABE III. Group A inspection for device type 01 Continued. Symbol MI- STD- 883 Cases E,F,Z Symbol M N CK V SS G1 G2 D4 D3 D2 D1 R V DD Measured terminal Subgroup 1 T A = 25 C Test circuit Subgroup 2 T A = 125 C Subgroup 3 T A = -55 C Unit 30 I O1 I O2 I O1 I O2 C i method Test no / 6/ 0.4V 0.4V 0.4V 0.4V 1.5V 1.5V 1.5V 1.5V 4.6V 4.6V 4.6V 4.6V 13.5V 13.5V 13.5V 13.5V 17/ 13/ 6/ 6/ 6/.0V 6/.0V 6/.0V 6/.0V 6/.0V 6/.0V.0V M N CK G1 G2 D4 D3 D2 D1 R Subgroup 4 T A = 25 C Min Max ma pf See footnotes at end of device type 01.

31 TABE III. Group A inspection for device type 01 Continued. 31 Symbol MI- Cases STD- E,F,Z Symbol M N CK V SS G1 G2 D4 D3 D2 D1 R V DD method Test no. Truth table test Measured terminal All outputs Subgroup 7 Subgroup 8 T A = 25 C Min Max T A = 125 C T A = -55 C Min Max Min Max See 4/ 5/ Unit See footnotes at end of device type 01.

32 TABE III. Group A inspection for device type 01 Continued. 32 Symbol MI- Cases Measured STD- E,F,Z terminal Subgroup 9 Subgroup 10 Subgroup Symbol M N CK V SS G1 G2 D4 D3 D2 D1 R V DD T A = 25 C T A = 125 C T A = -55 C method Test no. t P IN1 CK to Fig CK to 233 CK to 234 CK to t P1 235 CK to 236 CK to 237 CK to 238 CK to t P2 239 R to R to 241 R to 242 R to t T Fig t T t PZ Fig M to / 252 M to 253 M to 254 M to 255 N to 256 N to 257 N to 258 N to t PZ 259 M to 8/ 260 M to 261 M to 262 M to 263 N to 264 N to 265 N to 266 N to t PZ 267 M to 7/ 268 M to 269 M to 270 M to Unit ns µs ns See footnotes at end of device type 01.

33 TABE III. Group A inspection for device type 01 Continued. 33 Symbol MI- Cases Measured Unit STD- E,F,Z terminal Subgroup 9 Subgroup 10 Subgroup Symbol M N CK V SS G1 G2 D4 D3 D2 D1 R V DD T A = 25 C T A = 125 C T A = -55 C method Test no. t PZ Fig IN1 N to ns 8/ 272 N to 273 N to 274 N to t r 275 CK to µs (CK) 276 CK to 11/ 277 CK to 278 CK to t f 279 CK to (CK) 280 CK to 11/ 281 CK to 282 CK to t P(R) 283 R to ns 10/ 284 R to 285 R to 286 R to t S 287 IN1 CK to D ns 288 CK to D2 289 CK to D3 290 CK to D4 t S1 291 D1 to CK 292 D2 to CK 293 D3 to CK 294 D4 to CK f CK 295 CK to / 296 CK to 297 CK to 298 CK to t p 299 CK to (CK) 300 CK to 10/ 301 CK to 302 CK to See footnotes at end of device type 01.

34 TABE III. Group A inspection for device type 01 Continued. 34 Symbol MI- Cases Measured STD- E,F,Z terminal Subgroup Symbol M N CK V SS G1 G2 D4 D3 D2 D1 R V DD T A = 25 C method Test no. Min Max t P IN CK to Fig V CK to 305 CK to 306 CK to t P1 307 CK to 308 CK to 309 CK to 310 CK to t P V 10.0V 10.0V 10.0V R to R to 313 R to 314 R to t T Fig V V 10.0V V 10.0V 10.0V t T V 10.0V 10.0V V 10.0V 10.0V V 10.0V V 10.0V t PZ Fig V M to 8 0 7/ 324 M to 325 M to 326 M to 327 N to 328 N to 329 N to 330 N to t PZ 331 M to 8/ 332 M to 333 M to 334 M to 335 N to 336 N to 337 N to 338 N to Unit ns See footnotes at end of device type 01.

35 TABE III. Group A inspection for device type 01 Continued. Symbol MI- Cases STD- E,F,Z Symbol M N CK V SS G1 G2 D4 D3 D2 D1 R V DD method Test no. t PZ Fig IN1 10.0V 10.0V 10.0V 10.0V 10.0V 7/ t PZ 343 8/ Measured terminal M to M to M to M to N to N to N to N to Subgroup 12 T A = 25 C Min Max 8 0 Unit ns 35 1/ Pins not designated may be high level logic, low level logic or open. Exceptions are as follows: V IC(pos) tests, the V SS terminals shall be open; V IC(neg) tests, the V DD terminal shall be open, I SS tests, the output terminals shall be open. 2/ The I SS measurements shall be performed in sequence. 3/ The device manufacturer may, at his option, measure I I and I I at 25 C for each individual input or measure all inputs together. 4/ The truth table tests shall be performed in sequence. 5/ The truth table tests shall be performed at V I and V DD 5 Vdc and 18 Vdc. = V SS V maximum and = V DD 0.5 V minimum. 6/ See 4.4.1c. 7/ Pins 3, 4, 5, and 6 tied to V SS through 1 kω resistors. 8/ Pins 3, 4, 5, and 6 tied to V DD through 1 kω resistors. 9/ The minimum clock frequency (f CK) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column. 10/ The minimum clock or reset pulse width (t p(ck), t p(r)) requirement is considered met if proper output state changes occur with the pulse width set to that given in the limits column. 11/ Pulse repetition period = 100 µs, 50 percent duty cycle. The maximum clock rise or fall time (t r(ck), t f(ck)) requirement is considered met if proper output state changes occur with the rise time set to that given in the limits column. 12/ 100 kω resistors shall be connected between pins 2 and 14 to. 13/ Apply clock pulse; V IN = 0 to Vdc. 14/ Apply clock pulse; V IN = 1.5 to 3.5 Vdc. / Apply clock pulse; V IN = 3.0 to 7.0 Vdc. 16/ Apply clock pulse; V IN = 4.0 to 11.0 Vdc. 17/ Apply clock pulse; V IN = 0 to 5 Vdc.

36 36 Symbol V IC (pos) V IC (neg) I SS 2/ MI- STD-883 method 3005 TABE III. Group A inspection for device type 02. V DD Cases Units A,C,D,X,Y Measured Subgroup 2 Subgroup 3 Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S terminal Subgroup 1 T A = 25 C T A = 125 C T A = -55 C Test No. 1 1 ma R 1.5 Vdc 2 1 ma J1 3 1 ma J2 4 1 ma J3 5 1 ma K3 6 1 ma K2 7 1 ma K1 8 1 ma CK 9 1 ma S 10-1 ma R ma J ma J ma J ma K3-1 ma K ma K ma CK 18-1 ma S 19 V SS µa V O V.0V.0V.0V.0V.0V 10/.0V Q Vdc V O1 V O / Q Q V O Q See footnotes at end of device type 02.

37 37 Symbol V I1 V I2 V I3 MI- STD-883 method V I1 30 V I2 31 V I3 32 I O1 33 I O1 34 TABE III. Group A inspection for device type 02 Continued. V Cases Units A,C,D,X,Y Measured Subgroup 2 Subgroup 3 Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S terminal Subgroup 1 T A = 25 C T A = 125 C T A = -55 C Test No. DD 27 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ All 12/ 12/ 12/ 12/ 12/ 12/ Vdc 28 outputs V 11/ Q V 11/ Q I O1 0.4V Q 0.51 I O V 11/ Q 0.51 I O2 37.0V.0V.0V 13.5V.0V.0V.0V 10/.0V Q -3.4 I O V 10/ Q -3.4 I O2 1.5V Q 3.4 I O V 10/ Q 3.4 I I All inputs 3/ together I I2 42 R 43 J1 44 J2 45 J3 46 K3 47 K2 48 K1 49 CK 50 S I I1 3/ I I All inputs together See footnotes at end of device type 02. R J1 J2 J3 K3 K2 K1 CK S ma na na -1-45

38 TABE III. Group A inspection for device type 02 Continued. 38 Symbol C i Truth table test MI- STD-883 method S V DD Cases A,C,D,X,Y Measured Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK terminal Subgroup 4 T A = 25 C Test No. Min Max 61 4/ R / J1 63 4/ J2 64 4/ J3 65 4/ K3 66 4/ K2 67 4/ K1 68 4/ CK 69 4/ S Subgroup 7 Subgroup 8 T A = 25 C T A = 125 C T A = -55 C V All 71 outputs See notes 5/, 6/ Units pf See footnotes at end of device type 02.

39 39 TABE III. Group A inspection for device type 02 Continued. Cases Units MI- A,C,D,X,Y Measured Subgroup 8 Subgroup 7 Symbol STD- Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S V terminal DD T A = 25 C T A = 125 C T A = -55 C 883 Test No. method Truth All table test outputs See notes 5/, 6/ Subgroup 9 Subgroup 10 Subgroup 11 T A = 25 C T A = 125 C T A = -55 C t P1 t P1 t P1 t P1 t P2 t P2 t P2 t P2 t T t T t T t T f CK 7/ f CK 7/ t p(ck) 8/ t ps 8/ t ps 8/ t pr 8/ t pr 8/ t r(ck) 9/ t f(ck) 9/ 3003 Fig Fig. 4 Fig. 4 Fig IN1 See footnotes at end of device type 02. IN1 IN1 IN1 CK to Q CK to Q CK to Q CK to Q S to Q S to Q R to Q R to Q Q Q Q Q CK to Q CK to Q CK to Q CK to Q S to Q S to Q R to Q R to Q CK to Q CK to Q CK to Q CK to Q ns ns µs

40 40 Symbol t S1 t S1 t P1 t P1 t P2 t P2 t T t T MI- STD-883 method Fig Fig Fig. 4 TABE III. Group A inspection for device type 02 Continued. V DD Cases Units A,C,D,X,Y Measured Subgroup 10 Subgroup 11 Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S terminal Subgroup 9 T A = 25 C T A = 125 C T A = -55 C Test No. 130 IN1 CK to J ns 131 CK to J2 132 CK to J3 133 CK to K3 134 CK to K2 135 CK to K V 10.0V 10.0V IN1 10.0V 10.0V 10.0V J1 to CK J2 to CK J3 to CK K3 to CK K2 to CK K1 to CK 10.0V 10.0V 10.0V IN1 10.0V CK to Q CK to Q CK to Q CK to Q S to Q S to Q R to Q R to Q 10.0V 10.0V 10.0V IN1 10.0V Q Q Q Q Subgroup 12 T A = 25 C / Pins not designated may be high level logic, low level logic or open. Exceptions are as follows: V IC(pos) tests, the V SS terminals shall be open; V IC(neg) tests, the V DD terminal shall be open; I SS tests, the output terminals shall be open. 2/ The I SS measurements shall be performed in sequence. 3/ The device manufacturer may, at his option, measure I I and I I at 25 C for each individual input or measure all inputs together. 4/ See 4.4.1c. 5/ The truth table tests shall be performed in sequence. 6/ The truth table tests shall be performed at V I and V DD 5 Vdc and 18 Vdc. = V SS V maximum and = V DD V minimum. 7/ The minimum clock frequency (f CK) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column. 8/ The minimum clock, reset, or set pulse width (t p(ck), t p(r), t p(s)) requirement is considered met if proper output state changes occur with the pulse width set to that given in the limits column. 9/ Pulse repetition period = 100 µs, 50 percent duty cycle. The maximum clock rise or fall time (t r(ck), t f(ck)) requirement is considered met if proper output state changes occur with the rise time set to that given in the limits column. 10/ Apply clock pulse; V IN = 0 to Vdc. 11/ Apply clock pulse; V IN = 0 to 5 Vdc. ns

41 41 12/ The input/output conditions and timing sequence shall apply: Test V DD Input/output conditions Input levels Output levels Min Max 1.5V 4.5V 0.5V V I1 V I1 3.5V V I2 10.0V V I2 7.0V V I3.0V V I3 11.0V 3.0V 9.0V 4.0V 13.5V * Time slot R I J N J P J U K T K S K CK S V 1.5V O U T Q P Q U T S * Tests are to be run in sequence.

42 42 Symbol V IC (pos) V IC (neg) I SS 2/ MI- STD-883 method TABE III. Group A inspection for device type 03. Cases Units A,C,D,X,Y Subgroup 2 Subgroup 3 Subgroup 1 Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S V Measured DD T A = 25 C T A = 125 C T A = -55 C terminal Test No. 1 1 ma R 1.5 Vdc 2 1 ma J1 3 1 ma J2 4 1 ma J3 5 1 ma K3 6 1 ma K2 7 1 ma K1 8 1 ma CK 9 1 ma S 10-1 ma R ma J ma J ma J ma K3-1 ma K ma K ma CK 18-1 ma S V SS µa V O V V V V 10/ V Q Vdc V O1 V O / Q Q V O Q V I1 V I / 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ 12/ All Outputs 12/ 12/ 12/ 12/ 12/ 12/ V I3 V I1 V I2 V I3 I O1 I O1 I O2 I O See footnotes at end of device type V 0.4V.0V.0V 13.5V 1.5V 4.6V 0.4V 13.5V 1.5V 11/ 11/ 11/.0V.0V 10/ 10/ 10/.0V Q Q Q Q Q Q Q Q ma

43 43 TABE III. Group A inspection for device type 03 Continued. Cases Units MI- A,C,D,X,Y Subgroup 2 Subgroup 3 Subgroup 1 Symbol STD-883 Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S V Measured DD T A = 25 C T A = 125 C T A = -55 C method terminal Test No. I I1 3/ All inputs together 9 na I I2 42 R J1 44 J2 45 J3 46 K3 47 K2 48 K1 49 CK 50 S I I1 3/ All inputs together I I2 C i See footnotes at end of table 03. 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ 6/ R J1 J2 J3 K3 K2 K1 CK S R J1 J2 J3 K3 K2 K1 CK S -1 Subgroup 4 T A = 25 C Min -9 Max na pf

44 TABE III. Group A inspection for device type 03 Continued. 44 Symbol Truth table test MI- STD-883 method 3014 Cases Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S V Measured DD T A = 25 C T A = 125 C T A = -55 C terminal Test No. A,C,D,X,Y Subgroup 7 Subgroup 8 70 All 71 outputs See 4/, 5/ Units See footnotes at end of device type 03.

45 TABE III. Group A inspection for device type 03 Continued. 45 Symbol t P1 t P1 t P2 t P2 t T t T f CK 7/ t p(ck) 8/ t p(s) 8/ t p(r) 8/ t r(ck) 9/ t f(ck) 9/ t S1 t S1 Cases Units MI- A,C,D,X,Y Measured Subgroup 10 Subgroup 11 Subgroup 9 STD- terminal Symbol T A = 25 C 883 NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S V DD T A = 125 C T A = -55 C method Test No IN1 CK to Q ns Fig CK to Q 108 CK to Q 109 CK to Q 110 IN1 S to Q S to Q 112 R to Q 113 R to Q IN1 Q Fig. 4 1 Q 116 Q 117 Q Fig CK to Q CK to Q CK to Q CK to Q S to Q S to Q 124 R to Q 125 R to Q 126 IN1 CK to Q µs 127 CK to Q 128 CK to Q 129 CK to Q 130 CK to J ns 131 CK to J2 132 CK to J3 133 CK to K3 134 CK to K2 135 CK to K J1 to CK J2 to CK J3 to CK K3 to CK K2 to CK K1 to CK See footnotes at end of device type 03.

46 Symbol t P1 t P1 t P2 t P2 t T t T MI- STD-883 method 3003 Fig Fig Fig. 4 TABE III. Group A inspection for device type 03 Continued. Cases A,C,D,X,Y Subgroup 12 Symbol NC R J1 J2 J3 Q V SS Q K3 K2 K1 CK S V Measured DD T A = 25 C terminal Test No Min Max V 10.0V 10.0V 10.0V IN1 10.0V CK to Q CK to Q 144 CK to Q 145 CK to Q 146 IN1 10.0V 10.0V S to Q IN1 10.0V 10.0V S to Q IN1 10.0V 10.0V 10.0V R to Q IN1 10.0V 10.0V R to Q V 10.0V 10.0V 10.0V IN1 Q Q 2 Q 3 Q Units ns ns 46 1/ Pins not designated may be high level logic, low level logic or open. Exceptions are as follows: V IC(pos) tests, the V SS terminals shall be open; V IC(neg) tests, the V DD terminal shall be open, I SS tests, the output terminals shall be open. 2/ The I SS measurements shall be performed in sequence. 3/ The device manufacturer may, at his option, measure I I and I I at 25 C for each individual input or measure all inputs together. 4/ The truth table tests shall be performed in sequence. 5/ The truth table tests shall be performed at V I and V DD 5 Vdc and 18 Vdc. = V SS V maximum and = V DD 0.5 V minimum. 6/ See 4.4.1c. 7/ The minimum clock frequency (f CK) requirement is considered met if proper output state changes occur with the pulse repetition period set to that given in the limits column. 8/ The minimum clock, reset, or set pulse width (t p(ck), t p(r), t p(s)) requirement is considered met if proper output state changes occur with the pulse width set to that given in the limits column. 9/ Pulse repetition period = 100 µs, 50 percent duty cycle. The maximum clock rise or fall time (t r(ck), t f(ck)) requirement is considered met if proper output state changes occur with the rise time set to that given in the limits column. 10/ Apply clock pulse; V IN = 0 to Vdc. 11/ Apply clock pulse; V IN = 0 to 5 Vdc.

47 12/ The input/output conditions and timing sequence shall apply: 47 Test V DD Input/output conditions Input levels Output levels Min Max 1.5V 4.5V 0.5V V I1 V I1 3.5V V I2 10.0V V I2 7.0V V I3.0V V I3 11.0V 3.0V 9.0V 4.0V 13.5V * Time slot R I J N J P J U K T K S K CK S V 1.5V O U T Q P Q U T S * Tests are to be run in sequence.

48 TABE III. Group A inspection for device type MI- Cases Symbol STD- E,F,N,Z 883 Symbol CX1 RC1 R1 +TR1 -TR1 VSS -TR2 +TR2 R2 RC2 CX2 V DD method Test No. V IC 1 1mA (pos) 2 1mA 3 1mA 4 1mA 5 1mA 6 1mA 7 1mA 8 1mA V IC 9-1mA (neg) 10-1mA 11-1mA 12-1mA 13-1mA 14-1mA -1mA 16-1mA I SS / 8/ Measured terminal RC1 R1 +TR1 -TR1 -TR2 +TR2 R2 RC2 RC1 R1 +TR1 -TR1 -TR2 +TR2 R2 RC2 V SS Subgroup 1 T A = 25 C Subgroup 2 T A = 125 C Subgroup 3 T A = -55 C Units Vdc µa See footnotes at end of device type 04.

49 49 Symbol V O1 V O1 TABE III. Group A inspection for device type 04 Continued. MI- Cases STD- E,F,N,Z 883 Symbol CX1 RC1 R1 +TR1 -TR1 VSS -TR2 +TR2 R2 RC2 CX2 V DD method Test No V O1 V O V O V O V O V O V I1 V I2 V I3 V I1 V I2 V I3 I O1 I O / 10/ 8/ 4.6V 8/.0V.0V.0V 10 See footnotes at end of device type / 10/ 10/ 0.4V 10/ 0.4V 4.6V 10/ 0.4V 4.6V 10/ 0.4V.0V.0V.0V 10/ 10/ 10/ 7/ 10/ 8/ 4.6V 8/ 10/.0V 5.0 V 10.0V.0V 5.0 V 10.0V.0V Measured terminal All outputs None None RC1 RC2 None Units Subgroup 1 Subgroup 2 Subgroup 3 T A = 25 C T A = 125 C T A = -55 C / / / / / / Vdc ma