DEFENSE SUPPLY CENTER, COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, DIGITAL, DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR, MONOLITHIC SILICON REVISIONS
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1 REVISIONS LTR DESCRIPTION DTE PPROVED Update boilerplate to current MIL-PRF requirements. - PHN Thomas M. Hess CURRENT DESIGN CTIVITY CGE CODE HS CHNGED NMES TO: DL LND ND MRITIME Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE PMIC N/ PREPRED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY Phu H. Nguyen PPROVED BY Thomas M. Hess TITLE MICROCIRCUIT, DIGITL, DUL RETRIGGERBLE MONOSTBLE MULTIVIBRTOR, MONOLITHIC SILICON CODE IDENT. NO. REV PGE 1 OF 11 MSC N/ 5962-V079-14
2 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance dual retriggerable mono stable multi vibrator microcircuit, with an operating temperature range of -55 C to +125 C. 1.2 Vendor Item Drawing dministrative Control Number. The manufacturer s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: Device type(s) X E Drawing Device type Case outline Lead finish number (See 1.2.1) (See 1.2.2) (See 1.2.3) Device type Generic Circuit function 01 SN74HC123-EP Dual retriggerable mono stable multi vibrator Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 Package style X 16 MS-012 Plastic small outline Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator B C D E Z Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other REV PGE 2
3 1.3 bsolute maximum ratings. 1/ Supply voltage range ( V CC ) V to +7.0 V 2/ Input voltage range ( V I ) V to +7.0 V 3/ Output voltage range in high or low state ( V O ) V to V CC V 2/ Output voltage range in power off state ( V O ) V to +7.0 V 2/ Input clamp current ( I IK ) ( V I < 0 ) m Output clamp current ( I OK ) ( V O < 0 V or V O < V CC )... ±20 m Continuous output current ( I O ) (V O = 0 V to V CC)... ±25 m Continuous current through V CC or GND... ±50 m Package thermal impedance ( θ J ) C/W 4/ Storage temperature range (T STG ) C to 150 C 1.4 Recommended operating conditions. 5/ Supply voltage (V CC ) V to +5.5 V Minimum high level input voltage ( V IH): V CC = 2.0 V V V CC = 3.0 V V V CC = 5.5 V V Maximum low level input voltage (V IL): V CC = 2.0 V V V CC = 3.0 V V V CC = 5.5 V V Input voltage (V I)... 0 V to 5.5 V Output voltage (V O)... 0 to V CC Maximum high level output current ( I OH ): V CC = 2.0 V μ V CC = 3.3 V ±0.3 V m V CC = 5 V ±0.5 V m Maximum low level output current ( I OL ): V CC = 2.0 V μ V CC = 3.3 V ±0.3 V... 4 m V CC = 5 V ±0.5 V... 8 m Minimum external timing resistance: V CC = 2.0 V... 5 kω V CC > 3.0 V... 1 kω V Minimum power up ramp rate (Δt/ΔV CC)... 1 ms/v Operating free-air temperature range ( T ) C to +125 C 1/ Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2/ Voltage values are with respect to the network ground terminal. 3/ The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 4/ The package thermal impedance is calculated in accordance with JESD / Unused Rext/Cext terminals should be left unconnected. ll remaining unused inputs of the device must be held at VCC or GND to ensure proper device operation. REV PGE 3
4 2. PPLICBLE DOCUMENTS JEDEC SOLID STTE TECHNOLOGY SSOCITION (JEDEC) JEP95 Registered and Standard Outlines for Semiconductor Devices JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages (Copies of these documents are available online at or from JEDEC Solid State Technology ssociation, 3103 North 10th Street, Suite 240 S, rlington, V ). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer s part number as shown in 6.3 herein and as follows:. Manufacturer s name, CGE code, or logo B. Pin 1 identifier C. ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer s part number and with items and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams Case outline. The case outline shall be as shown in and figure Terminal connections. The terminal connections shall be as shown in figure Function table. The Function table shall be as shown in figure Logic diagram. The logic diagram shall be as shown in figure Input/Output timing diagram. The input/output timing diagram shall be as shown in figure Load circuit and timing waveforms. The load circuit and timing waveforms shall be as shown in figure 6. REV PGE 4
5 Test Symbol Conditions TBLE I. Electrical performance characteristics. 1/ unless otherwise specified V CC Limits Unit T = 25 C -55 C T 125 C Min Max Min Max 2 V V I OH = -50 µ 3 V High level output voltage V OH 4.5 V I OH = -4 m 3 V I OH = -8 m 4.5 V V V I OL = 50 µ 3 V Low level output voltage V OL 4.5 V I OL = 4 m 3 V I OL = 8 m 4.5 V Input R ext/c ext 2/ I I V I = V CC or GND 5.5 V ±0.25 ±2.5 μ current, B, and CLR V I = V CC or GND 0 V to 5.5 V ±0.1 ±1 3/ Quiescent supply current I CC V I = V CC or GND, I O = V 4 40 μ V I = V CC or GND, 3 V μ ctive state (per circuit) I CC R ext/c ext = 0.5 V CC 4.5 V V Input capacitance C i V I = V CC or GND 5 V pf Pulse duration Pulse retrigger time CLR 3.3 V ±0.3 V 5 5 ns t w 5 V ±0.5 V 5 5 or B trigger 3.3 V ±0.3 V V ±0.5 V 5 5 R ext = 1 kω, C ext = 100 pf 3.3 V ±0.3 V 4/ 76 Typ 4/ ns t rr R ext = 1 kω, C ext = 0.01 μf 4/ 1.8 Typ 4/ R ext = 1 kω, C ext = 100 pf 5 V ±0.5 V 4/ 59 Typ 4/ μs R ext = 1 kω, C ext = 0.01 μf 4/ 1.5 Typ 4/ Switching characteristics From input or B See footnotes at end of table. t PLH C L = 15 pf 3.3 V ±0.3 V / 5 V ±0.5 V 12 5/ t PHL 3.3 V ±0.3 V / 5 V ±0.5 V 12 5/ 24 5/ ns 14 5/ 24 5/ 14 5/ REV PGE 5
6 Pulse duration at Q or Q TBLE I. Electrical performance characteristics Continued. 1/ Test Symbol Conditions t w unless otherwise specified C L = 50 pf, C ext = 28 μf, R ext = 2 kω C L = 50 pf, C ext = 0.01 μf, R ext = 10 kω C L = 50 pf, C ext = 0.1 μf, R ext = 10 kω V CC Limits Unit T = 25 C -55 C T 125 C Min Max Min Max Switching characteristics - continued From input CLR t PLH C L = 15 pf 3.3 V ±0.3 V / / ns 5 V ±0.5 V 9.4 5/ 11 5/ t PHL 3.3 V ±0.3 V / / 5 V ±0.5 V 9.4 5/ 11 5/ From input CLR trigger t PLH 3.3 V ±0.3 V / 26 5/ 5 V ±0.5 V / 15 5/ t PHL 3.3 V ±0.3 V / 26 5/ 5 V ±0.5 V / 15 5/ From input or B t PLH C L = 50 pf 3.3 V ±0.3 V V ±0.5 V t PHL 3.3 V ±0.3 V V ±0.5 V From input CLR t PLH 3.3 V ±0.3 V V ±0.5 V t PHL 3.3 V ±0.3 V V ±0.5 V From input CLR trigger t PLH 3.3 V ±0.3 V V ±0.5 V t PHL 3.3 V ±0.3 V V ±0.5 V V ±0.3 V ns 5 V ±0.5 V Output pulse duration variation (Q or Q ) between circuits in same package Operating Characteristics Power dissipation capacitance 3.3 V ±0.3 V μs 5 V ±0.5 V V ±0.3 V ms 5 V ±0.5 V V ±0.3 V ±1% Typ 5 V ±0.5 V ±1% Typ 5 V 29 Typ pf 1/ Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. 2/ This test is performed with the terminal in the off state condition. 3/ On products compliant to MIL-PRF-38535, this parameter in not production tested at V CC = 0 V. 4/ See retriggering in the manufacturer data. 5/ On products compliant to MIL-PRF-38535, this parameter in not production tested. REV PGE 6
7 Case X Dimension Symbol Inches Millimeters Symbol Inches Millimeters Min Max Min Max Min Max Min Max E E b e.050 BSC 1.27 BSC c L D NOTES: 1. ll linear dimensions are in inches (millimeters). 2. This drawing is subject to change without notice. 3. Body length does not include mold flash, protrusions, or gat burrs. Mold flash, protrusions, or gat burs shall not exceed.006 inches (0.15 mm) per end. 4. Body width does not include interlead flash. Interlead flash shall not exceed.017 inches (0.43 mm) per side. 5. Falls within JEDEC MS-012 variation C FIGURE 1. Case outline. REV PGE 7
8 Case X Terminal number Terminal symbol Terminal number Terminal symbol B 10 2B 3 1 CLR 11 2 CLR 4 1 Q 12 2 Q 5 2Q 13 1Q 6 2C ext 14 1C ext 7 2R ext/c ext 15 1R ext/c ext 8 GND 16 V CC FIGURE 2. Terminal connections. Note: These outputs are based on the assumption that the indicated steady-state condition at the and B inputs have been set up long enough to complete any pulse started before the setup. FIGURE 3. Function table. REV PGE 8
9 FIGURE 4. Logic diagram. FIGURE 5. Input/output timing diagram REV PGE 9
10 NOTES: 1. C L includes probe and jig capacitance. 2. ll input pulses are supplied by generators having the following characteristics: Z O = 50 Ω, t r = 3 ns, t f = 3 ns.. 3. The outputs are measured one at a time with one input transition per measurement. FIGURE 5. Load circuit and timing waveforms. REV PGE 10
11 4. VERIFICTION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPRTION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DL Land and Maritime maintains an online database of all current sources of supply at Vendor item drawing administrative control number 1/ Device manufacturer CGE code Vendor part number Top side marking -01XE SN74HC123MDREP HC123-EP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CGE code Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest lane P.O. Box Dallas, TX Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX REV PGE 11
DLA LAND AND MARITIME COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, CMOS SPDT SWITCH, MONOLITHIC SILICON REVISIONS
REVISIONS LTR DESCRIPTION DTE PPROVED Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PMIC N/ PREPRED BY RICK OFFICER
DLA LAND AND MARITIME COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, +5 V PROGRAMMABLE LOW DROPOUT VOLTAGE REGULATOR, MONOLITHIC SILICON
REVISIONS LTR DESCRIPTION DTE PPROVED Prepared in accordance with SME Y14.24 Vendor item drawing REV PGE REV PGE REV STTUS OF PGES REV PGE 1 2 3 4 5 6 7 8 9 10 11 PMIC N/ PREPRED BY RICK OFFICER DL LND
DLA LAND AND MARITIME COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, VOLTAGE REFERENCE, MONOLITHIC SILICON
REVISIONS LTR DESCRIPTION DTE PPROVED Make change to the lead finish from -01XB to -01XE. Update document paragraphs to current requirements. - ro 17-08-15 C. SFFLE Prepared in accordance with SME Y14.24
DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO TITLE MICROCIRCUIT, LINEAR, PRECISION LOW DROPOUT CONTROLLER, MONOLITHIC SILICON REVISIONS
REVISIONS LTR DESCRIPTION DTE PPROVED Update the boilerplate paragraphs. - ro 09-02-19 R. HEBER B dd footnote 1/ to Table I. Update document paragraphs to current requirements. - ro 15-02-05 C. SFFLE CURRENT
DLA LAND AND MARITIME COLUMBUS, OHIO
REVISIONS LTR DESCRIPTION DTE PPROVED Make correction to the vendor part number by deleting TPS51200-EP and replacing with TPS51200MDRCTEP as specified under paragraph 6.3. - ro 16-12-06 C. SFFLE Prepared
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April 1994 Revised May 1999 74VHC221A Dual Non-Retriggerable Monostable Multivibrator General Description The VHC221A is an advanced high speed CMOS Monostable Multivibrator fabricated with silicon gate
74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop.
Rev. 03 14 September 2005 Product data sheet 1. General description 2. Features 3. pplications 4. uick reference data he are high-speed Si-gate CMOS devices and are pin compatible with the HEF4040B series.
74LS75 Quad Latch. DM74LS75 Quad Latch. General Description. Ordering Code: Logic Diagram. Connection Diagram. Function Table (Each Latch)
74LS75 Quad Latch General Description These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present
STANDARD MICROCIRCUIT DRAWING MICROCIRCUIT, LINEAR, 4-CHANNEL DIFFERENTIAL, ANALOG MULTIPLEXER, MONOLITHIC SILICON
REVISIONS LTR DESCRIPTION DTE (YR-MO-D) PPROVED Update boilerplate paragraphs to current MIL-PRF-38535 requirements. Delete references to device class M requirements. - ro 12-10-29 C. SFFLE REV REV REV
Low Power Quint Exclusive OR/NOR Gate
100307 Low Power Quint Exclusive OR/NOR Gate General Description The 100307 is monolithic quint exclusive-or/nor gate. The Function output is the wire-or of all five exclusive-or outputs. All inputs have
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
74HC1G125; 74HCT1G125
Rev. 05 23 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed, Si-gate CMOS device. The provides one non-inverting buffer/line driver with 3-state
74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting
3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible
SGM7SZ32 Small Logic Two-Input OR Gate
Preliminary Datasheet GENERL DESCRIPTION The is a single two-input OR gate from SGMICRO's Small Logic series. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high
MM74HC157 Quad 2-Input Multiplexer
Quad 2-Input Multiplexer General Description The MM74HC157 high speed Quad 2-to-1 Line data selector/multiplexers utilizes advanced silicon-gate CMOS technology. It possesses the high noise immunity and
MM74HC175 Quad D-Type Flip-Flop With Clear
Quad D-Type Flip-Flop With Clear General Description The MM74HC175 high speed D-type flip-flop with complementary outputs utilizes advanced silicon-gate CMOS technology to achieve the high noise immunity
74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset
Rev. 05 13 July 2009 Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance
MM74HC373 3-STATE Octal D-Type Latch
MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power
MM74HC573 3-STATE Octal D-Type Latch
MM74HC573 3-STATE Octal D-Type Latch General Description The MM74HC573 high speed octal D-type latches utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity and low
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED. A Update to current requirements. Editorial changes throughout. - gap Raymond Monnin
REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update to current requirements. Editorial changes throughout. - gap 06-10-05 Raymond Monnin Remove class M references. Update drawing to current MIL-PRF-38535
MM74HCT08 Quad 2-Input AND Gate
MM74HCT08 Quad 2-Input AND Gate General Description The MM74HCT08 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS low quiescent
74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
June 1998 Revised February 2001 74LCX112 Low oltage Dual J-K Negative Edge-Triggered Flip-Flop with 5 Tolerant Inputs General Description The LCX112 is a dual J-K flip-flop. Each flip-flop has independent
DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118.
Data Sheet FN3118.4 SPST 4-Channel Analog Switch The is a low cost, CMOS monolithic, Quad SPST analog switch. It can be used in general purpose switching applications for communications, instrumentation,
Dual 3-channel analog multiplexer/demultiplexer with supplementary switches
with supplementary switches Rev. 03 16 December 2009 Product data sheet 1. General description 2. Features 3. Applications 4. Ordering information The is a dual 3-channel analog multiplexer/demultiplexer
8-bit binary counter with output register; 3-state
Rev. 01 30 March 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low power Schottky TTL (LSTTL). It
74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.
Rev. 03 12 November 2007 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The are octal non-inverting buffer/line drivers with 3-state
74AHC1G14; 74AHCT1G14
Rev. 6 18 May 29 Product data sheet 1. General description 2. Features 3. pplications 74HC1G14 and 74HCT1G14 are high-speed Si-gate CMOS devices. They provide an inverting buffer function with Schmitt
MM74HC251 8-Channel 3-STATE Multiplexer
8-Channel 3-STATE Multiplexer General Description The MM74HC251 8-channel digital multiplexer with 3- STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and
74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.
Rev. 03 31 January 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
74AHC125; 74AHCT125. Quad buffer/line driver; 3-state
Rev. 04 January 2008 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). They
MM74HC00 Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption
8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).
Rev. 04 12 January 2005 Product data sheet 1. General description 2. Features The is an with three address inputs (0 to 2), an active LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and
5-stage Johnson decade counter
Rev. 06 5 November 2009 Product data sheet 1. General description The is a with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9),
74LVU General description. 2. Features. 3. Applications. Hex inverter
Rev. 06 20 December 2007 Product data sheet. General description 2. Features 3. pplications The is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HCU04. The is a general purpose
74HC244; 74HCT244. Octal buffer/line driver; 3-state
Rev. 03 22 December 2005 Product data sheet 1. General description 2. Features 3. Quick reference data The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
MM74HC244 Octal 3-STATE Buffer
MM74HC244 Octal 3-STATE Buffer General Description The MM74HC244 is a non-inverting buffer and has two active low enables (1G and 2G); each enable independently controls 4 buffers. This device does not
INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 May 15 IC24 Data Handbook 1998 Jun 23 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for low voltage applications: 1.0V to 3.6V Accepts TTL input levels
SGM7SZ00 Small Logic Two-Input NAND Gate
GENERAL DESCRIPTION The SGM7SZ00 is a single two-input NAND gate from SGMICRO s Small Logic series. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part.
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs
NTE74HC173 Integrated Circuit TTL High Speed CMOS, 4 Bit D Type Flip Flop with 3 State Outputs Description: The NTE74HC173 is an high speed 3 State Quad D Type Flip Flop in a 16 Lead DIP type package that
MICROCIRCUITS, DIGITAL, BIPOLAR LOW-POWER SCHOTTKY TTL, FLIP-FLOPS, CASCADABLE, MONOLITHIC SILICON. Inactive for new design after 18 April 1997.
INCH-POUND MIL-M-38510/301F 4 March 2004 SUPERSEDING MIL-M-38510/301E 14 February 2003 MILITARY SPECIFICATION MICROCIRCUITS, DIGITAL, BIPOLAR LOW-POWER SCHOTTKY TTL, FLIP-FLOPS, CASCADABLE, MONOLITHIC
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 1999 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. DM74LS174 DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description
MM74HC138 3-to-8 Line Decoder
3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit features
74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.
Rev. 05 20 December 2007 Product data sheet. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The has octal non-inverting buffer/line drivers with 3-state
MM74HC139 Dual 2-To-4 Line Decoder
MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.