DATASHEET HI-390. Features. Ordering Information. Pinout Switch States shown for a Logic 1 Input. Applications. Functional Diagram

Transcription

1 HI-39 Dual SPDT CMOS nalog Switch NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLCEMENT contact our Technical Support Center at INTERSIL or DTSHEET FN7 Rev 1. ugust The Hl-39 switch is a monolithic device fabricated using CMOS technology and the Intersil dielectric isolation process. This device is TTL compatible and features low leakage and supply currents, low and nearly constant ON resistance over the analog signal range, break-before-make switching and low power dissipation. Ordering Information PRT NUMBER TEMP. RNGE ( o C) PCKGE PKG. NO. HI to 1 16 Ld CERDIP F16.3 Pinout Switch States shown for a Logic 1 Input HI-39 (CERDIP) TOP VIEW D 1 NC D 3 S 3 S D NC D S 1 1 IN 1 1 V- 13 GND 1 NC 11 V+ 1 IN 9 S Features nalog Signal Range ( 1V Supplies) V Low Leakage p Low On Resistance Break-Before-Make Delay ns Charge Injection pC TTL Compatible Symmetrical Switch Elements Low Operating Power mW pplications Sample and Hold (i.e., Low Leakage Switching) Op mp Gain Switching (i.e., Low On Resistance) Portable, Battery Operated Circuits Low Level Switching Circuits Dual or Single Supply Systems Functional Diagram S IN N P LOGIC SW1, SW SW3, SW D OFF ON 1 ON OFF FN7 Rev 1. Page 1 of 8 ugust

2 HI-39 Schematic Diagrams SWITCH CELL V+ MN1B MNB MN3B IN MPB MPB MNB MNB OUT MP3B MPB MP1B V- DIGITL INPUT BUFFER ND LEVEL SHIFTER V+ D MP1 MP MP3 MP MP MP6 MP7 MP8 LOGIC IN D1 MN1 MN MN3 MN MN MN6 MN7 MN8 GND V- SWITCH CELL DRIVER (ONE PER SWITCH CELL) FN7 Rev 1. Page of 8 ugust

3 HI-39 bsolute Maximum Ratings Voltage Between Supplies (V+ to V-) V Digital Input Voltage (V+) +V to (V-) -V nalog Input Voltage (V+) +1.V to (V-) -1.V Operating Conditions Temperature Ranges HI o C to 1 o C Thermal Information Thermal Resistance (Typical, Note 1) J ( o C/W) JC ( o C/W) CERDIP Package Maximum Junction Temperature Hermetic Package o C Maximum Storage Temperature Range o C to 1 o C Maximum Lead Temperature (Soldering 1s) o C CUTION: Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. J is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Supplies = +1V, -1V; V IN = Logic Input. V IN for Logic 1 = V, for Logic =.8V, Unless Otherwise Specified PRMETER TEST CONDITIONS TEMP ( o C) MIN TYP MX UNITS DYNMIC CHRCTERISTICS Switch ON Time, t ON ns Switch OFF Time, t OFF - 16 ns Break-Before-Make Delay, t OPEN ns Charge Injection Voltage, V (Note 7) mv OFF Isolation (Note 6) db Input Switch Capacitance, C S(OFF) pf Output Switch Capacitance, C D(OFF) pf Output Switch Capacitance, C D(ON) pf Digital Input Capacitance, C IN - - pf DIGITL INPUT CHRCTERISTICS Input Low Level, V INL Full V Input High Level, V INH Full - - V Input Leakage Current (Low), I INL (Note ) Full Input Leakage Current (High), I INH (Note ) Full NLOG SWITCH CHRCTERISTICS nalog Signal Range Full V ON Resistance, r ON (Note ) - 3 Full - 7 OFF Input Leakage Current, I S(OFF) (Note 3) -. 1 n Full n OFF Output Leakage Current, I D(OFF) (Note 3) -. 1 n Full n ON Input Leakage Current, I S(ON) (Note ) n Full -. 1 n FN7 Rev 1. Page 3 of 8 ugust

4 HI-39 Electrical Specifications Supplies = +1V, -1V; V IN = Logic Input. V IN for Logic 1 = V, for Logic =.8V, Unless Otherwise Specified (Continued) PRMETER TEST CONDITIONS TEMP ( o C) MIN TYP MX UNITS POWER SUPPLY CHRCTERISTICS Current, I+ (Note 8) -.9. m Full m Current, I- (Note 8) Full Current, I+ (Note 9) Full Current, I- (Note 9) Full NOTES:. V S = 1V, I OUT = 1m. On resistance derived from the voltage measured across the switch under these conditions. 3. V S = 1V, V D = 1V.. V S = V D = 1V.. The digital inputs are diode protected MOS gates and typical leakages of 1n or less can be expected. 6. V S = 1V RMS, f = khz, C L = 1pF, R L = 1K, C L = C FIXTURE + C PROBE, OFF Isolation = Log V S /V D. 7. V S = V, C L = 1nF, Logic Drive = V pulse. Switches are symmetrical; S and D may be interchanged. Charge Injection = Q = C L x V. 8. V IN = V (one input, all other inputs = V). 9. V IN =.8V (all inputs). Test Circuits and Waveforms 1V V+ 6 R GEN = V GEN S IN D R L 1k C L 1pF LOGIC INPUT (V) LOGIC INPUT V LOGIC GND V- -1V FIGURE 1. TEST CIRCUIT FIGURE 1B. LOGIC INPUT 1 V GEN = 1V (NOTE 1) V GEN = V FIGURE 1C. V NLOG = 1V FIGURE 1D. V NLOG = V FN7 Rev 1. Page of 8 ugust

5 HI-39 Test Circuits and Waveforms (Continued) - V GEN = V - V GEN = -V FIGURE 1E. V NLOG = V FIGURE 1F. V NLOG = -V - -1 V GEN = -1V FIGURE 1G. V NLOG = -1V NOTE: 1. If R GEN, R L or C L is increased, there will be proportional increases in rise and/or fall RC times. FIGURE 1. SWITCHING WVEFORMS FOR VRIOUS NLOG INPUT VOLTGES Typical Performance Curves 8 V+ = +1V, V- = -1V 8 T = o C D 6 6 C r DS(ON) ( ) 1 o C o C - o C r DS(ON) ( ) B V+ = +1V, V- = -1V B V+ = +1V, V- = -1V C V+ = +7.V, V- = -7.V D V+ = +V, V- = -V DRIN VOLTGE (V) DRIN VOLTGE (V) FIGURE. r DS(ON) vs V D FIGURE 3. r DS(ON) vs V D FN7 Rev 1. Page of 8 ugust

6 HI-39 Typical Performance Curves (Continued) POWER DISSIPTION (mw) V+ = +1V, V- = -1V T = o C, V S = 1V, R L = K OFF ISOLTION (db) R L = 1k R L = 1 V+ = +1V, V- = -1V C LOD = 3pF, V S = 1V RMS K 1K 1K 1M LOGIC SWITCHING FREQUENCY (% DUTY CYCLE) (Hz) FREQUENCY (Hz) FIGURE. DEVICE POWER DISSIPTION vs SWITCHING FREQUENCY (SINGLE LOGIC INPUT) FIGURE. OFF ISOLTION vs FREQUENCY 1. V+ = +1V, V- = -1V 1. V+ = +1V, V- = -1V V D = V S = 1V I S(OFF) OR I D(OFF) (n) 1..1 I D(ON) (n) TEMPERTURE ( o C) TEMPERTURE ( o C) FIGURE 6. I S(OFF) OR I D(OFF) vs TEMPERTURE (NOTE 11) FIGURE 7. I D(ON) vs TEMPERTURE (NOTE 11) NOTE: 11. The net leakage into the source or drain is the N-Channel leakage minus the P-Channel leakage. This difference can be positive, negative or zero depending on the analog voltage and temperature, and will vary greatly from unit to unit C D(ON) (pf) C IN (pf) 8 TRNSITION (INDETERMINTE DUE TO CTIVE INPUT) DRIN VOLTGE (V) INPUT VOLTGE (V) FIGURE 8. OUTPUT ON CPCITNCE vs DRIN VOLTGE FIGURE 9. DIGITL INPUT CPCITNCE vs INPUT VOLTGE FN7 Rev 1. Page 6 of 8 ugust

7 HI-39 Typical Performance Curves (Continued) 3 V+ = +1V, V- = -1V V INH =.V, V INL = V t ON 3 t ON V+ = +1V, T = o C V INH = V, V INL = V t ON, t OFF (ns) 1 t OFF t ON, t OFF (ns) 1 t OFF TEMPERTURE ( o C) 1 1 NEGTIVE SUPPLY (V) FIGURE 1. SWITCHING TIME vs TEMPERTURE FIGURE 11. SWITCHING TIME vs NEGTIVE SUPPLY VOLTGE t ON, t OFF ( s) V- = -1V, T = o C V INH =.V, V INL = V t OFF t ON INPUT SWITCHING THRESHOLD (V) V- = -1V, T = o C 1 1 POSITIVE SUPPLY VOLTGE (V) 1 1 POSITIVE SUPPLY VOLTGE (V) FIGURE 1. SWITCHING TIME vs POSITIVE SUPPLY VOLTGE FIGURE 13. INPUT SWITCHING THRESHOLD vs POSITIVE SUPPLY VOLTGE FN7 Rev 1. Page 7 of 8 ugust

8 HI-39 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BSE PLNE SETING PLNE S1 b ccc M bbb S b C - B Q -C- -B- C - B S D e D S -D- -- NOTES: 1. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.. Corner leads (1, N, N/, and N/+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b.. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per NSI Y1.M Controlling dimension: INCH. E L M c1 e/ S D S aaa M C - B LED FINISH BSE METL b1 M (b) SECTION - S e c D S (c) F16.3 MIL-STD-183 GDIP1-T16 (D-, CONFIGURTION ) 16 LED CERMIC DUL-IN-LINE FRIT SEL PCKGE INCHES MILLIMETERS SYMBOL MIN MX MIN MX NOTES b b b b c c D E e.1 BSC. BSC - e.3 BSC 7.6 BSC - e/.1 BSC 3.81 BSC - L Q S o 1 o 9 o 1 o - aaa bbb ccc M , 3 N Rev. /9 Copyright Intersil mericas LLC. ll Rights Reserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN7 Rev 1. Page 8 of 8 ugust