DATASHEET HI-518. Features. Ordering Information. Applications. Pinout. 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer

Size: px

Start display at page:

Download "DATASHEET HI-518. Features. Ordering Information. Applications. Pinout. 8-Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer"

Rolf Wilson
5 years ago
Views:

1 DATASHEET HI Channel/Differential 4-Channel, CMOS High Speed Analog Multiplexer F3147 Rev 4.00 The Hl-518 is a monolithic, dielectrically isolated, high speed, high performance CMOS analog multiplexer. It offers unique built-in channel selection decoding plus an inhibit input for disabling all channels. The dual function of address input A 2 enables the Hl-518 to be user programmed either as a single ended 8-Channel multiplexer by connecting Out A to Out B and using A 2 as a digital address input, or as a 4-Channel differential multiplexer by connecting A 2 to the V- supply. The substrate leakages and parasitic capacitances are reduced substantially by using the Intersil Dielectric Isolation process to achieve optimum performance in both high and low level signal applications. The low output leakage current (l D(OFF) < 100pA at 25 o C) and fast settling (t SETTLE = 800ns to 0.01%) characteristics of the device make it an ideal choice for high speed data acquisition systems, precision instrumentation, and industrial process control. Ordering Information PART UMBER PART MARKIG TEMP. RAGE ( o C) PACKAGE PKG. DWG. # HI HI to Ld PDIP E18.3 HI Z (See ote) HI Z 0 to Ld PDIP* (Pb-free) E18.3 HI to Ld CERDIP F18.3 *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. OTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Features Access Time (Typical) ns Settling Time ns (0.1%) Low Leakage (Typical) - I S(OFF) pA - I D(OFF) pA Low Capacitance (Max) - C S(OFF) pF - C D(OFF) pF Off Isolation at 500kHz dB (Min) Low Charge Injection Error mV Single Ended to Differential Selectable (SDS) Logic Level Selectable (LLS) Pb-Free Plus Anneal Available (RoHS Compliant) Applications Data Acquisition Systems Precision Instrumentation Industrial Control Pinout B I8/4B I7/3B I6/2B I5/1B V DD /LLS HI-518 (CERDIP, PDIP) TOP VIEW 1 18 A 2 17 V I4/4A I3/3A I2/2A I1/1A EABLE A 0 F3147 Rev 4.00 Page 1 of 8

2 Truth Tables TABLE 1. HI-518 USED AS A 8-CHAEL MULTIPLEXER OR DUAL 4-CHAEL MULTIPLEXER (OTE 1) USE A 2 AS DIGITAL ADDRESS IPUT O CHAEL TO EABLE A 2 A 0 A B L X X X one one H L L L 1A one H L L H 2A one H L H L 3A one H L H H 4A one H H L L one 1B H H L H one 2B H H H L one 3B H H H H one 4B OTE: 1. For 8-Channel single ended function, tie Out A to Out B ; for dual 4-Channel function, use the A 2 address pin to select between Mux A and Mux B, where Mux A is selected with A 2 low. TABLE 2. HI-518 USED AS A DIFFERETIAL 4-CHAEL MULTIPLEXER A 2 COECTED TO V- SUPPLY O CHAEL TO EABLE A 0 A B L X X one one H L L 1B H L H 2A 2B H H L 3A 3B H H H 4A 4B Functional Block Diagram V DD /LLS I 1A P E A 0 DECODER A I 4A A 2 P Q A 2 DECODER I 1B Q P B DECODER I 4B P IPUT BUFFER AD DECODERS MULTIPLEXER SWITCHES A 2 DECODE A 2 Q Q H H ml L L H V- L L F3147 Rev 4.00 Page 2 of 8

3 Absolute Maximum Ratings to V V Analog (V I, V ) (V-) -2V to () +2V Digital Input Voltage: TTL Levels Selected (V DD /LLS Pin = or Open) V to +6V 2/SDS (V-) -2V to () +2V CMOS Levels Selected (V DD /LLS Pin = V DD ) V to () +2V Operating Conditions Temperature Ranges HI o C to 125 o C HI o C to 75 o C Thermal Information Thermal Resistance (Typical, ote 2) JA ( o C/W) JC ( o C/W) PDIP Package* /A CERDIP Package Maximum Junction Temperature Ceramic Package o C Plastic Package o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTIO: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. OTE: 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; H (Logic Level High) = 2.4V, L (Logic Level Low) = 0.8V; V DD /LLS = (ote 3), Unless Otherwise Specified TEST TEMP -8-5 PARAMETER CODITIOS ( o C) MI TYP MAX MI TYP MAX UITS DYAMIC CHARACTERISTICS Access Time, t A ns Full ns Break-Before-Make Delay, t OPE ns Enable Delay (O), t O(E) ns Enable Delay (OFF), t OFF(E) ns Settling Time To 0.1% ns To 0.01% ns Charge Injection Error ote mv Off Isolation ote db Channel Input Capacitance, C S(OFF) pf Channel Output Capacitance, C D(OFF) pf Digital Input Capacitance, C A pf Input to Output Capacitance, C DS(OFF) pf DIGITAL IPUT CHARACTERISTICS Input Low Threshold, L (TTL) ote 3 Full V Input High Threshold, H (TTL) ote 3 Full V Input Low Threshold, L (CMOS) ote 3 Full V DD V DD V Input High Threshold, H (CMOS) ote 3 Full 0.7V DD V DD - - V Input Leakage Current, I AH (High) Full A Input Leakage Current, I AL (Low) Full A AALOG CHAEL CHARACTERISTICS Analog Signal Range, V I ote 4 Full V On Resistance, r O ote Full - - 1, ,000 Off Input Leakage Current, l S(OFF) na Full na Off Output Leakage Current, I D(OFF) na Full na On Channel Leakage Current, I D(O) na Full na POWER SUPPLY CHARACTERISTICS Power Dissipation, P D Full mw F3147 Rev 4.00 Page 3 of 8

4 Electrical Specifications Supplies = +15V, -15V; H (Logic Level High) = 2.4V, L (Logic Level Low) = 0.8V; V DD /LLS = (ote 3), Unless Otherwise Specified (Continued) TEST TEMP -8-5 PARAMETER CODITIOS ( o C) MI TYP MAX MI TYP MAX UITS I+, Current V E = 2.4V Full ma I-, Current Full ma OTES: 3. V DD /LLS pin = open or grounded for TTL compatibility. V DD /LLS pin = V DD for CMOS compatibility. 4. At temperatures above 90 o C, care must be taken to assure V I remains at least 1. below the V SUPPLY for proper operation. 5. V I = 1, I = -100A. 6. V I =, C L = 100pF, enable input pulse = 3V, f = 500kHz. 7. C L = 40pF, R L = 1K, V E = 0.8V, V I = 3V RMS, f = 500kHz. Due to the pin to pin capacitance between I 8/4B and B, channel 8/4B exhibits 60dB of OFF isolation under the above test conditions. Test Circuits and Waveforms V DD /LLS =, Unless Otherwise Specified I 100A E 0.8V V 2 1 I V I r O = V 2 100A 1 A I D(OFF) 1 FIGURE 1. O RESISTACE TEST CIRCUIT FIGURE 2. I D(OFF) TEST CIRCUIT (OTE 8) I S(OFF) A E 0.8V E A 2 A 0 A I D(O) FIGURE 3. I S(OFF) TEST CIRCUIT (OTE 8) FIGURE 4. I D(O) TEST CIRCUIT (OTE 8) 2.4V +15V +1 50% t A 3.5V PUT 10% ADDRESS DRIVE ( ) V I 1 I 2-7 I 8 A 0 A E B V DD /LLS V- -15V k pf FIGURE 5A. MEASUREMET POITS FIGURE 5B. TEST CIRCUIT FIGURE 5. ACCESS TIME OTE: 8. Two measurements per channel: 1 and 1. (Two measurements per device for I D(OFF) 1 and 1.) F3147 Rev 4.00 Page 4 of 8

5 Test Circuits and Waveforms V DD /LLS =, Unless Otherwise Specified (Continued) +15V 3.5V ADDRESS DRIVE ( ) PUT 50 A 0 I 1 I 2-7 I 8 A +5V S 1 O 50% 50% S 8 O t OPE 2.4V E B V DD /LLS V pF V -15V FIGURE 6A. MEASUREMET POITS FIGURE 6. BREAK-BEFORE-MAKE DELAY FIGURE 6B. TEST CIRCUIT +15V 50% 3.5V 50% EABLE DRIVE ( ) I % PUT I 2-8 t O(E) t OFF(E) 10% 50 A 0 E A V DD /LLS V pF -15V FIGURE 7A. MEASUREMET POITS FIGURE 7. EABLE DELAY FIGURE 7B. TEST CIRCUIT 2.4V +15V 3V A 0,, V V O I A OR B V C L = 100pF E V DD /LLS V- -15V FIGURE 8A. MEASUREMET POITS V O is the measured voltage error due to charge injection. The error in coulombs is Q = C L x V O. FIGURE 8. CHARGE IJECTIO FIGURE 8B. TEST CIRCUIT F3147 Rev 4.00 Page 5 of 8

6 Die Characteristics DIE DIMESIOS: 89 mils x 93 mils METALLIZATIO: Type: AlCu Thickness: 16kÅ 2kÅ SUBSTRATE POTETIAL (OTE): -V SUPPLY PASSIVATIO: Type: itride Over Silox itride Thickness: 3.5kÅ 1.0kÅ Silox Thickness: 12kÅ 2.0kÅ WORST CASE CURRET DESITY: 1.43 x 10 5 A/cm 2 TRASISTOR COUT: 356 PROCESS: CMOS-DI OTE: The substrate appears resistive to the -V SUPPLY terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -V SUPPLY potential. Metallization Mask Layout HI-518 E A 0 V DD /LLS I 1/1A I 5/1B I 2/2A I 6/2B I 3/3A I 7/3B I 4/4A I 8/4B V- A B F3147 Rev 4.00 Page 6 of 8

7 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLAE SEATIG PLAE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- OTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1,, /2, and /2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ASI Y14.5M Controlling dimension: ICH. E L M c1 ea/2 S D S aaa M C A - B LEAD FIISH BASE METAL b1 M (b) SECTIO A-A S ea c D S (c) F18.3 MIL-STD-1835 GDIP1-T18 (D-6, COFIGURATIO A) 18 LEAD CERAMIC DUAL-I-LIE FRIT SEAL PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A b b b b c c D E e BSC 2.54 BSC - ea BSC 7.62 BSC - ea/ BSC 3.81 BSC - L Q S o 105 o 90 o 105 o - aaa bbb ccc M , Rev. 0 4/94 F3147 Rev 4.00 Page 7 of 8

8 Dual-In-Line Plastic Packages (PDIP) IDEX AREA BASE PLAE SEATIG PLAE D1 B1 -C- -A /2 B D e D1 E1 OTES: 1. Controlling Dimensions: ICH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ASI Y14.5M Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication o Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed inch (0.25mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed inch (0.25mm). 9. is the maximum number of terminal positions. 10. Corner leads (1,, /2 and /2 + 1) for E8.3, E16.3, E18.3, E28.3 may have a B1 dimension of inch ( mm). -B- A (0.25) M C A A2 L B S A e C E C L e A C e B E18.3 (JEDEC MS-001-BC ISSUE D) 18 LEAD DUAL-I-LIE PLASTIC PACKAGE ICHES MILLIMETERS SYMBOL MI MAX MI MAX OTES A A A B B , 10 C D D E E e BSC 2.54 BSC - e A BSC 7.62 BSC 6 e B L Rev. 2 11/03 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. o license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see F3147 Rev 4.00 Page 8 of 8

DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118.

DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118. Data Sheet FN3118.4 SPST 4-Channel Analog Switch The is a low cost, CMOS monolithic, Quad SPST analog switch. It can be used in general purpose switching applications for communications, instrumentation,