ICL7662. Features. CMOS Voltage Converter. Applications. Pinouts. Data Sheet January 9, 2006 FN3181.4

Size: px

Start display at page:

Download "ICL7662. Features. CMOS Voltage Converter. Applications. Pinouts. Data Sheet January 9, 2006 FN3181.4"

Ella Farmer
6 years ago
Views:

1 Data Sheet January 9, 00 OBSOLETE PRODUCT POSSIBLE SUBSTITUTE PRODUCT INTERSIL ICL0XXX SERIES ICL FN. CMOS Voltage Converter The Intersil ICL is a monolithic highvoltage CMOS power supply circuit which offers unique performance advantages over previously available devices. The ICL performs supply voltage conversion from positive to negative for an input range of.v to 0.0V, resulting in complementary output voltages of.v to 0V. Only noncritical external capacitors are needed for the charge pump and charge reservoir functions. The ICL can also function as a voltage doubler, and will generate output voltages up to.v with a 0V input. Contained on chip are a series DC power supply regulator, RC oscillator, voltage level translator, four output power MOS switches. A unique logic element senses the most negative voltage in the device and ensures that the output N Channel switch sourcesubstrate junctions are not forward biased. This assures latchup free operation. The oscillator, when unloaded, oscillates at a nominal frequency of 0kHz for an input supply voltage of.0v. This frequency can be lowered by the addition of an external capacitor to the OSC terminal, or the oscillator may be overdriven by an external clock. The LV terminal may be tied to GROUND to bypass the internal series regulator and improve low voltage (LV) operation. At medium to high voltages (0V to 0V), the LV pin is left floating to prevent device latchup. Features No External Diode Needed Over Entire Temperature Range Pin Compatible With ICL0 Simple Conversion of V Supply to V Supply Simple Voltage Multiplication ( = ()nv IN ) 99.9% Typical Open Circuit Voltage Conversion Efficiency 9% Typical Power Efficiency Wide Operating Voltage Range.V to 0.0V Easy to Use Requires Only External NonCritical Passive Components PbFree Plus Anneal Available (RoHS Compliant) Applications On Board Negative Supply for Dynamic RAMs Localized µprocessor (00 Type) Negative Supplies Inexpensive Negative Supplies Data Acquisition Systems Up to 0V for Op Amps Pinouts ICLCBD0 (SOIC) TOP VIEW ICLCBD AND IBD (SOIC) TOP VIEW TEST V V OSC TEST CAP OSC LV CAP LV GND 0 GND CAP CAP ICL (PDIP) TOP VIEW TEST V CAP OSC GND LV CAP CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 00, 00, 00. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 ICL Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. DWG. # ICLCPA 0 to 0 Ld PDIP E. ICLCPAZ (Note) 0 to 0 Ld PDIP* (Pbfree) E. ICLCBD0 0 to 0 Ld SOIC (N) M. ICLCBD 0 to 0 Ld SOIC (N) M. ICLIPA 0 to Ld PDIP E. ICLIBD 0 to Ld SOIC (N) M. *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. NOTE: Intersil Pbfree plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and 00% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD00. Functional Block Diagram V RC OSCILLATOR VOLTAGE LEVEL TRANSLATOR CAP CAP TEST P N OSC LV VOLTAGE REGULATOR LOGIC NETWORK

3 ICL Absolute Maximum Ratings Supply Voltage V Oscillator Input Voltage V to (V 0.V) for V < 0V (Note ) (V 0V) to (V 0.V) for V > 0V Current Into LV (Note ) µA for V > 0V Output Short Duration Continuous Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) θ JC ( o C/W) PDIP Package* N/A Plastic SOIC Package N/A Maximum Lead Temperature (Soldering, 0s) o C (SOIC Lead Tips Only) *Pbfree PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES:. Connecting any terminal to voltages greater than V or less than GND may cause destructive latchup. It is recommended that no inputs from sources operating from external supplies be applied prior to power up of ICL0S.. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V = V, T A = o C, C OSC = 0, Unless Otherwise Specified. Refer to Figure. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Supply Voltage Range Lo VL R L = 0kΩ, Min < T A < Max. V Supply Voltage Range Hi VH R L = 0kΩ, LV = Open Min < T A < Max 9 0 V Supply Current I R L =, LV = Open T A = o C ma 0 o C < T A < 0 o C 0 o C < T A < o C ma o C < T A < o C ma Output Source Resistance R O I O = 0mA, LV = Open T A = o C 0 00 Ω 0 o C < T A < 0 o C 0 o C < T A < o C 0 0 Ω o C < T A < o C 0 Ω Supply Current I V = V, R L =, T A = o C 0 0 µa 0 o C < T A < 0 o C 0 o C < T A < o C 00 µa o C < T A < o C 0 0 µa Output Source Resistance R O V = V, I O = ma, T A = o C 00 Ω 0 o C < T A < 0 o C 0 o C < T A < o C 0 0 Ω o C < T A < o C 00 0 Ω Oscillator Frequency FOSC 0 khz Power Efficiency P EFF R L = kω T A = o C 9 9 % Min < T A < Max 9 % Voltage Conversion Efficiency VoEf R L = Min < T A < Max % Oscillator Sink or Source Current I OSC V = V (V OSC = 0V to V) 0. µa V = V (V OSC = V to V).0 µa NOTE:. Pin is a Test pin and is not connected in normal use. When the TEST pin is connected to V, an internal transmission gate disconnects any external parasitic capacitance from the oscillator which would otherwise reduce the oscillator frequency from its nominal value.

4 ICL Typical Performance Curves (See Figure, Test Circuit) OUTPUT RESISTAE (Ω) V (V) FIGURE. OUTPUT SOURCE RESISTAE AS A FUTION OF SUPPLY VOLTAGE I L = 0mA T A = o C C OSC = 0pF LV = OPEN OUTPUT RESISTAE (Ω) V (V) FIGURE. OUTPUT SOURCE RESISTAE AS A FUTION OF SUPPLY VOLTAGE I L = ma T A = o C C OSC = 0pF LV = OPEN OUTPUT RESISTAE (Ω) V = V I L = ma V = V I L = 0mA TEMPERATURE ( o C) POWER CONVERSION EFFICIEY (%) P EFF 00 V = V 0 I L = ma T A = o C 0 00 K 0K 00K F OSC (Hz) RO OUTPUT RESISTAE (Ω) FIGURE. OUTPUT SOURCE RESISTAE AS A FUTION OF TEMPERATURE FIGURE. POWER CONVERSION EFFICIEY AND OUTPUT SOURCE RESISTAE AS A FUTION OF OSCILLATOR FREQUEY OSCILLATOR FREQUEY (khz) 0 9 R L = T A = o C C OSC = 0pF LV = OPEN SUPPLY VOLTAGE (V) OSCILLATOR FREQUEY (Hz) 0K K 00 0 C OSC (pf) V = V T A = o C R L = K FIGURE. OSClLLATOR FREQUEY vs SUPPLY VOLTAGE NOTE: All typical values have been characterized but are not tested. FIGURE. FREQUEY OF OSCILLATION AS A FUTION OF EXTERNAL OSCILLATOR CAPACITAE

5 ICL Typical Performance Curves (See Figure, Test Circuit) OSCILLATOR FREQUEY (Hz) K V = V K C OSC = 0pF K K K 0K 9K K K K K TEMPERATURE ( o C) FIGURE. UNLOADED OSClLLATOR FREQUEY AS A FUTION OF TEMPERATURE (Continued) OUTPUT VOLTAGE V O (V) 9 0 V = V T A = o C LV = OPEN SLOPE = Ω LOAD CURRENT I L (ma) FIGURE. OUTPUT VOLTAGE AS A FUTION OF LOAD CURRENT OUTPUT VOLTAGE VO (V) 0 V = V T A = o C SLOPE = Ω LOAD CURRENT I L (ma) POWER CONVERSION EFFICIEY (%) PBFF V = V T A = o C LOAD CURRENT I L (ma) I 0 SUPPLY CURRENT I (ma) FIGURE 9. OUTPUT VOLTAGE AS A FUTION OF LOAD CURRENT FIGURE 0. SUPPLY CURRENT AND POWER CONVERSION EFFICIEY AS A FUTION OF LOAD POWER CONVERSION EFFICIEY (%) PBFF V = V T A = o C LOAD CURRENT I L (ma) I SUPPLY CURRENT I (ma) OSCILLATOR FREQUEY (khz) R L = T A = o C C OSC = 0pF 0 9 LV = OPEN SUPPLY VOLTAGE (V) FIGURE. SUPPLY CURRENT AND POWER CONVERSION EFFICIEY AS A FUTION OF LOAD CURRENT FIGURE. FREQUEY OF OSCILLATION AS A FUTION OF SUPPLY VOLTAGE

6 ICL Typical Performance Curves (See Figure, Test Circuit) (Continued) SUPPLY CURRENT I (µa) K 0K OSCILLATOR FREQUEY (Hz) FIGURE. SUPPLY CURRENT AS A FUTION OF OSCILLATOR FREQUEY NOTE:. These curves include in the supply current that current fed directly into the load R L from the V (See Figure ). Thus, approximately half the supply current goes directly to the positive side of the load, and the other half, through the ICL, to the negative side of the load. Ideally, V IN, I S I L, so V IN x I S x I L. Circuit Description The ICL contains all the necessary circuitry to complete a negative voltage converter, with the exception of external capacitors which may be inexpensive 0µF polarized electrolytic capacitors. The mode of operation of the device may be best understood by considering Figure, which shows an idealized negative voltage converter. Capacitor C is charged to a voltage, V, for the half cycle when switches S and S are closed. (Note: Switches S and S are open during this half cycle.) During the second half cycle of operation, switches S and S are closed, with S and S open, thereby shifting capacitor C negatively by V volts. Charge is then transferred from C to C such that the voltage on C is exactly V, assuming ideal switches and no load on C. The lcl approaches this ideal situation more closely than existing nonmechanical circuits. In the lcl, the switches of Figure are MOS power switches; S is a PChannel device and S, S and S are hannel devices. The main difficulty with this approach is that in integrating the switches, the substrates of S and S must always remain reverse biased with respect to their sources, but not so much as to degrade their ON resistances. In addition, at circuit startup, and under output short circuit conditions ( = V), the output voltage must be sensed and the substrate bias adjusted accordingly. Failure to accomplish this would result in high power losses and probable device latchup. This problem is eliminated in the ICL by a logic network which senses the output voltage ( ) together with the level translators, and switches the substrates of S and S to the correct level to maintain necessary reverse bias. The voltage regulator portion of the ICL is an integral part of the antilatchup circuitry, however its inherent voltage drop can degrade operation at low voltages. Therefore, to improve low voltage operation the LV pin should be connected to GROUND, disabling the regulator. For supply voltages greater than 0V the LV terminal must be left open to insure latchup proof operation, and prevent device damage. C ICL C OSC (NOTE) C 0µF I L R L I S V (V) NOTE: For large value of C OSC (> 000pF) the values of C and C should be increased to 00µF. FIGURE. ICL TEST CIRCUIT

7 ICL S S V IN A N9 or similar diode placed in parallel with C will prevent the device from latching up under these conditions. (Anode pin, Cathode pin ). C Typical Applications Theoretical Power Efficiency Considerations In theory a voltage multiplier can approach 00% efficiency if certain conditions are met:. The drive circuitry consumes minimal power.. The output switches have extremely low ON resistance and virtually no offset.. The impedances of the pump and reservoir capacitors are negligible at the pump frequency. The ICL approaches these conditions for negative voltage multiplication if large values of C and C are used. ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE OCCURS. The energy lost is defined by: E = /C (V V ) S S FIGURE. IDEALIZED NEGATIVE CONVERTER C = V IN where V and V are the voltages on C during the pump and transfer cycles. If the impedances of C and C are relatively high at the pump frequency (refer to Figure ) compared to the value of R L, there will be a substantial difference in the voltages V and V. Therefore it is not only desirable to make C as large as possible to eliminate output voltage ripple, but also to employ a correspondingly large value for C in order to achieve maximum efficiency of operation. Do s and Don ts. Do not exceed maximum supply voltages.. Do not connect LV terminal to GROUND for supply voltages greater than 0V.. When using polarized capacitors, the terminal of C must be connected to pin of the ICL and the terminal of C must be connected to GROUND.. If the voltage supply driving the has a large source impedance (Ω 0Ω), then a.µf capacitor from pin to ground may be required to limit rate of rise of input voltage to less than V/µs.. User should insure that the output (pin ) does not go more positive than GND (pin ). Device latch up will occur under these conditions. Simple Negative Voltage Converter The majority of applications will undoubtedly utilize the ICL for generation of negative supply voltages. Figure shows typical connections to provide a negative supply where a positive supply of.v to 0.0V is available. Keep in mind that pin (LV) is tied to the supply negative (GND) for supply voltages below 0V. The output characteristics of the circuit in Figure A can be approximated by an ideal voltage source in series with a resistance as shown in Figure B. The voltage source has a value of (V). The output impedance (R O ) is a function of the ON resistance of the internal MOS switches (shown in Figure ), the switching frequency, the value of C and C, and the ESR (equivalent series resistance) of C and C. A good first order approximation for R O is: R O (R SW R SW ESRC ) (R SW R SW ESRC ) (f PUMP = f OSC, Combining the four R SWX terms as R SW, we see that R O x R SW R SW, the total switch resistance, is a function of supply voltage and temperature (See the Output Source Resistance graphs), typically Ω at o C and V, and Ω at o C and V. Careful selection of C and C will reduce the remaining terms, minimizing the output impedance. High value capacitors will reduce the /(f PUMP x C ) component, and low FSR capacitors will lower the ESR term. Increasing the oscillator frequency will reduce the /(f PUMP x C ) term, but may have the side effect of a net increase in output impedance when C > 0µF and there is no longer enough time to fully charge the capacitors every cycle. In a typical application where f OSC = 0kHz and C = C = C = 0µF: Since the ESRs of the capacitors are reflected in the output impedance multiplied by a factor of, a high value could potentially swamp out a low /(f PUMP x C ) term, rendering an increase in switching frequency or filter capacitance ineffective. Typical electrolytic capacitors may have ESRs as high as 0Ω. f PUMP x C ESRC R SWX = MOSFET switch resistance) f PUMP x C x ESRC ESRC Ω R O x ESRC ESRC ( x 0 x 0 x 0 ) R O 0 x ESR C Ω

8 ICL 0µF C Output Ripple ICL 0µF = V V C ESR also affects the ripple voltage seen at the output. The total ripple is determined by V, A and B, as shown in Figure. Segment A is the voltage drop across the ESR of C at the instant it goes from being charged by C (current flowing into C ) to being discharged through the load (current flowing out of C ). The magnitude of this current change is x I OUT, hence the total drop is x I OUT x ESRC V. Segment B is the voltage change across C during time t, the half of the cycle when C supplies current the load. The drop at B is I OUT x t /C V. The peaktopeak ripple voltage is the sum of these voltage drops: V R O A. B. FIGURE. SIMPLE NEGATIVE CONVERTER AND ITS OUTPUT EQUIVALENT VOUT Again, a low ESR capacitor will result in a higher performance output. Paralleling Devices Any number of ICL voltage converters may be paralleled (Figure ) to reduce output resistance. The reservoir capacitor, C, serves all devices while each device requires its own pump capacitor, C. The resultant output resistance would be approximately: R OUT = R OUT (of ICL) n (number of devices) Cascading Devices The ICL may be cascaded as shown in Figure 9 to produce larger negative multiplication of the initial supply voltage. However, due to the finite efficiency of each device, the practical limit is 0 devices for light loads. The output voltage is defined by: = n(v IN ), where n is an integer representing the number of devices cascaded. The resulting output resistance would be approximately the weighted sum of the individual ICL R OUT values. V RIPPLE f PUMP C ESRC I OUT t t B 0 (V) V A FIGURE. OUTPUT RIPPLE V ICL C C ICL N R L C FIGURE. PARALLELING DEVICES

9 ICL V 0µF ICL 0µF 0µF ICL N 0µF FIGURE 9. CASCADING DEVICES FOR IREASED OUTPUT VOLTAGE Changing the ICL Oscillator Frequency It may be desirable in some applications, due to noise or other considerations, to increase the oscillator frequency. This is achieved by overdriving the oscillator from an external clock, as shown in Figure 0. In order to prevent possible device latchup, a kω resistor must be used in series with the clock output. In the situation where the designer has generated the external clock frequency using TTL logic, the addition of a 0kΩ pullup resistor to V supply is required. Note that the pump frequency with external clocking, as with internal clocking, will be / of the clock frequency. Output transitions occur on the positivegoing edge of the clock. 0µF ICL It is also possible to increase the conversion efficiency of the ICL at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is achieved by connecting an additional capacitor, COSC, as shown in Figure. However, lowering the oscillator frequency will cause an undesirable increase in the impedance of the pump (C ) and reservoir (C ) capacitors; this is overcome by increasing the values of C and C by the same factor that the frequency has been reduced. For example, the addition of a 00pF capacitor between pin (OSC) and V will lower the oscillator frequency to khz from its nominal frequency of 0kHz (a multiple of 0), and thereby necessitate a corresponding increase in the value of C and C (from 0mF to 00mF). V kω 0µF FIGURE 0. EXTERNAL CLOCKING V CMOS GATE C ICL Positive Voltage Doubling The ICL may be employed to achieve positive voltage doubling using the circuit shown in Figure. In this application, the pump inverter switches of the ICL are used to charge C to a voltage level of V V F (where V is the supply voltage and V F is the forward voltage drop of diode D ). On the transfer cycle, the voltage on C plus the supply voltage (V) is applied through diode C to capacitor C. The voltage thus created on C becomes (V) (V F ) or twice the supply voltage minus the combined forward voltage drops of diodes D and D. The source impedance of the output ( ) will depend on the output current, but for V = V and an output current of 0mA it will be approximately 0Ω. V C OSC C FIGURE. LOWERING OSCILLATOR FREQUEY ICL V D D C C NOTE: D and D can be any suitable diode. FIGURE. POSITIVE VOLTAGE DOUBLER = (V) (V F ) 9

10 ICL C ICL C FIGURE. COMBINED NEGATIVE CONVERTER AND POSITIVE DOUBLER Combined Negative Voltage Conversion and Positive Supply Doubling Figure combines the functions shown in Figure and Figure to provide negative voltage conversion and positive voltage doubling simultaneously. This approach would be, for example, suitable for generating 9V and V from an existing V supply. In this instance capacitors C and C perform the pump and reservoir functions respectively for the generation of the negative voltage, while capacitors C and C are pump and reservoir respectively for the doubled positive voltage. There is a penalty in this configuration which combines both functions, however, in that the source impedances of the generated supplies will be somewhat higher due to the finite impedance of the common charge pump driver at pin of the device. Voltage Splitting The bidirectional characteristics can also be used to split a higher supply in half, as shown in Figure. The combined load will be evenly shared between the two sides and, a high value resistor to the LV pin ensures startup. Because the switches share the load in parallel, the output impedance is much lower than in the standard circuits, and higher currents can be drawn from the device. By using this circuit, and then the circuit of Figure 9, 0V can be converted (via V, and V) to a nominal 0V, although with rather high series output resistance (~0Ω). V D D = (nv IN V FDX ) = (V) (V FD ) (V FD ) C C Regulated Negative Voltage Supply In some cases, the output impedance of the ICL can be a problem, particularly if the load current varies substantially. The circuit of Figure can be used to overcome this by controlling the input voltage, via an ICL lowpower CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the ICLs output does not respond instantaneously to a change in input, but only after the switching delay. The circuit shown supplies enough delay to accommodate the ICL, while maintaining adequate feedback. An increase in pump and storage capacitors is desirable, and the values shown provides an output impedance of less than Ω to a load of 0mA. Other Applications Further information on the operation and use of the ICL may be found in AN0 Principles and Applications of the ICL0 CMOS Voltage Converter. R L 0µF V V = ICL 0µF R L 0µF V K 0K 00K ICL09 FIGURE. SPLITTING A SUPPLY IN HALF 0K ICL 00µF V 00Ω ICL V V 0µF 00K 0K VOLTAGE ADJUST 00µF FIGURE. REGULATING THE OUTPUT VOLTAGE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO00 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 0

DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118.

DG211. Features. SPST 4-Channel Analog Switch. Part Number Information. Functional Block Diagrams. Pinout. Data Sheet December 21, 2005 FN3118. Data Sheet FN3118.4 SPST 4-Channel Analog Switch The is a low cost, CMOS monolithic, Quad SPST analog switch. It can be used in general purpose switching applications for communications, instrumentation,