SP6828/ V Low Power Voltage Inverters V OUT C1+ SP6829 C % Voltage Conversion Efficiency +1.15V to +4.2V Input Voltage Range +1.

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Lizbeth Morgan
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1 /689 +V Low Power Voltage Inverters 99.9% Voltage Conversion Efficiency +.V to +.V Input Voltage Range +. Guaranteed Start-up Inverts Input Supply Voltage 0µA Quiescent Current for the µa Quiescent Current for the ma Output Current khz Operating Frequency for the khz Operating Frequency for the Ideal for +.6V Lithium Ion Battery Applications Reverse +.6V Lithium Ion Battery Protection -pin SOT Package Now Available in Lead Free DESCRIPTION The /689 devices are CMOS Charge Pump Voltage Inverters that can be implemented in designs requiring a negative voltage from a +V battery source. The / 689 devices are ideal for both battery-powered and board level voltage conversion applications with a typical operating current of 0µA for the and µa for the. Both devices can output ma with a voltage drop of 00mV. These devices combine a low quiescent current with high efficiency (>9% over most of its load-current range) which is ideal for designs using +.V or +.6V lithium ion batteries. Applications include cell phones PDAs medical instruments and other portable equipment. The /689 devices are available in a space-saving -pin SOT Package. C- DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

2 ABSOLUTE MAXIMUM RATGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability....+.v...-.v Short Circuit to...indefinite I...0mA Storage Temperature...-6 C to +0 C Power Dissipation (T =+70 C)...7mW Lead Temperature (Soldering)...00 o C ESD Rating...kV Human Body Model SPECIFICATIONS FOR THE /689 = +.V C=C=0µF for the C=C=.µF for the and T = - C to +8 C unless otherwise noted. Typical values are taken specifically at T =+ C. Test Circuit Figure 9 unless otherwise noted. P ARAMETER M. T YP. MAX. UNITS CONDITIONS Supply Voltage V = 0kΩ T = 0kΩ T =+ C Note =- C to +8 C Supply Current µa T T = T T = = + C R = L =- C to +8 C A MB = + C R = L =- C to +8 C A MB Output Resistance Oscillator Frequency Ω khz I I = ma T = ma T T T T T Voltage Conversion Efficiency % = Power Efficiency (Ideal) 97 % = 0kΩ NOTE =+ C =- C to +8 C =+ C =- C to +8 C =+ C =- C to +8 C Power Efficiency (Actual) 9 9 % = 0kΩ NOTE I = 0mA NOTE NOTE : = - +00mV NOTE : Power Efficiency (Ideal) = V x I -V x (-V/RL) NOTE : Power Efficiency (Actual) = V x I V x I DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

3 ABSOLUTE MAXIMUM RATGS These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability v v Short Circuit to...indefinite I...0mA Storage Temperature...-6 C to +0 C Power Dissipation (T =+70 C)...7mW Lead Temperature (Soldering)...00 o C ESD Rating...kV Human Body Model SPECIFICATIONS FOR THE - = +.0V C=C=0µF and T = - C to +8 C unless otherwise noted.typical values are taken specifically at T =+ C. Test Circuit Figure 9 unless otherwise noted. P ARAMETER M. T YP. MAX. UNITS CONDITIONS Supply Voltage V = 0kΩ T = 0kΩ T =+ C Note =- C to +8 C Supply Current 0 µa T = - C to +8 C R = L Output Resistance 0 6 Ω I I = ma T = ma T =+ C =- C to +8 C Oscillator Frequency 6 0 khz T Voltage Conversion Efficiency % = =- C to +8 C Power Efficiency (Ideal) 98 % = 0kΩ NOTE Power Efficiency (Actual) 9 9 % = 0kΩ NOTE I = 0mA NOTE NOTE : = - +00mV NOTE : Power Efficiency (Ideal) = V x I -V x (-V/RL) NOTE : Power Efficiency (Actual) = V x I V x I DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

4 P P ASSIGNMENTS Pin Inverting charge pump output. C- Pin Input to the positive power supply. Pin C- Negative terminal to the charge pump capacitor. Pin Ground reference. Pin Positive terminal to the charge pump capacitor. TYPICAL PERFORMANCE CHARACTERISTICS = +.V C = C = C = 0µF for C = C = C =.µf for and T = o C unless otherwise noted. The /689 devices use the circuit found in Figure 9 when obtaining the following typical performance characteristics (unless otherwise noted). R (Ohm) R (Ohm) V =.V V =.V V =.V V (V) Temperature ( o C) Figure. Output Resistance vs. Supply Voltage Figure. Output Resistance vs. Temperature DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

5 TYPICAL PERFORMANCE CHARACTERISTICS = +.V C = C = C = 0µF for C = C = C =.µf for and T = o C unless otherwise noted. The /689 devices use the circuit found in Figure 9 when obtaining the following typical performance characteristics (unless otherwise noted). 6 f (khz) 0 9 Pump Frequency (khz) V (V) 0 Supply Voltage (V) Figure. Charge Pump Frequency vs. Supply Voltage for the Figure. Charge Pump Frequency vs. Supply Voltage for the fpump (khz) 0 9 V =.V V =.V V =.V Pump Frequency (khz) V =.V V =.V V =.V Temperature ( o C) Temperature ( O C) 00 Figure. Charge Pump Frequency vs. Temperature for the Figure 6. Charge Pump Frequency vs. Temperature for the DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

6 TYPICAL PERFORMANCE CHARACTERISTICS = +.V C = C = C = 0µF for C = C = C =.µf for and T = o C unless otherwise noted. The /689 devices use the circuit found in Figure 9 when obtaining the following typical performance characteristics (unless otherwise noted). I (ma) V =.V; V = -.V V =.V; V = -.V V = V; V = -.V Capacitance (µf) Output Current (ma) V =.V; V = -.V V =.V; V = -.V V = V; V = -.V Capacitance (µf) Figure 7. Output Current vs. Capacitance for the Figure 8. Output Current vs. Capacitance for the Ripple (mv) V =.V; V = -.V 00 V =.V; V = -.V 00 V = V; V = -.V Capacitance (µf) Output Ripple (mvp-p) V =.V; V = -.V V = V; V = -.V V =.V; V = -.V Capacitance (µf) Figure 9. Output Voltage Ripple vs. Capacitance for the Figure 0. Output Voltage Ripple vs. Capacitance for the DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation 6

7 TYPICAL PERFORMANCE CHARACTERISTICS = +.V C = C = C = 0µF for C = C = C =.µf for and T = o C unless otherwise noted. The /689 devices use the circuit found in Figure 9 when obtaining the following typical performance characteristics (unless otherwise noted). I (µa) V (V) V (V) V = V -.0 V =.V V =.V I (ma) Figure. Supply Current vs. Supply Voltage Figure. Output Voltage vs. Output Current Power Efficiency (%) Voltage Efficiency (%) I (ma) I (ma) 0 Figure. Power Efficiency vs. Output Current Figure. Voltage Efficiency vs. Output Current DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation 7

8 TYPICAL PERFORMANCE CHARACTERISTICS = +.V C = C = C = 0µF for C = C = C =.µf for and T = o C unless otherwise noted. The /689 devices use the circuit found in Figure 9 when obtaining the following typical performance characteristics (unless otherwise noted). VEFF (%) V (V) VEFF (%) V (V) Figure. Voltage Efficiency vs. Supply Voltage with a 0kΩ load Figure 6. Voltage efficiency vs. Supply Voltage without a Load VEFF (%) =.V = -.V I L = ma =.V = -.V I L = ma V (V) Figure 7. Output Noise and Ripple for the Figure 8. Output Noise and Ripple for the DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation 8

9 C C + C- C Figure 9. /689 in its Typical Operating Circuit as a Negative Voltage Converter; this Circuit Was Used to Obtain the Typical Performance Characteristics Found in Figures Through 8 (unless otherwise noted) C C- C C Figure 0. /689 Connected as a Voltage Inverter with the load from to DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation 9

10 DESCRIPTION The /689 devices are CMOS Charge Pump Voltage Converters that can be used to invert a +.V to +.V input voltage. These devices are ideal for designs involving batterypowered and/or board level voltage conversion applications. S = -V S The typical operating frequency of the is khz. The typical operating frequency of the is khz. The has a typical operating current of 0µA and the operates at µa. Both devices can output ma with a voltage drop of 00mV. The devices are ideal for designs using +.V or +.6V lithium ion batteries such as cell phones PDAs medical instruments and other portable equipment. The /689 devices combine a high efficiency with a low quiescent current. C C S S Figure. Circuit for an Ideal Voltage Inverter THEORY OF OPERATION The /689 devices should theoretically produce an inverted input voltage. In real world applications there are small voltage drops at the output that reduce efficiency. The circuit of an ideal voltage inverter can be found in Figure. The voltage inverters require two external capacitors to store the charge. A description of the two phases follows: Phase In the first phase of the clock cycle switches S and S are opened and S and S closed. This connects the flying capacitor C from to ground. C charges up to the input voltage applied at. Phase In the second phase of the clock cycle switches S and S are closed and S and S are opened. This connects the flying capacitor C in parallel with the output capacitor C. The charge stored in C is now transferred to C. Simultaneously the negative side of C is connected to and the positive side is connected to ground. With the voltage across C smaller than the voltage across C the charge flows from C to C until the voltage at the equals -. Charge-Pump Output The output of the /689 devices is not regulated and therefore is dependent on the output resistance and the amount of load current. As the load current increases losses may slightly increase at the output and the voltage may become slightly more positive. The loss at the negative output V LOSS equals the current draw I from times the negative converter's source resistance R S : V LOSS = I x R S. The actual inverted output voltage at will equal the inverted voltage difference of and V LOSS : = -( - V LOSS ). Efficiency Theoretically the total power loss of a switched capacitor voltage converter can be summed up as follows: P LOSS = P T + P CAP + P CONV where P LOSS is the total power loss P T is the total internal loss in the IC including any losses in the MOSFET switches P CAP is the resistive loss of DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation 0

11 the charge pump capacitors and P CONV is the total conversion loss during charge transfer between the flying and output capacitors. These are the three theoretical factors that may effect the power efficiency of the /689 devices in designs. Internal losses come from the power dissipated in the IC's internal circuitry. Losses in the charge pump capacitors will be induced by the capacitors' ESR. The effects of the ESR losses and the output resistance can be found in the following equation: I x R = P CAP + P CONV and R x ( x R SWITCHES + ESR C ) + ESR C + fosc x C where I is the output current R is the circuit's output resistance R SWITCHES is the internal resistance of the MOSFET switches ESR C and ESR C are the ESR of their respective capacitors and f OSC is the oscillator frequency. This term with f OSC is derived from an ideal switchedcapacitor circuit as seen in Figure. Conversion losses will happen during the charge transfer between the flying capacitor C and the output capacitor C when there is a voltage difference between them. P CONV can be determined by the following equation: P CONV = f OSC x [ / x C x ( - ) + / x C x (V RIPPLE - x x V RIPPLE ) ]. where P = x I and P = x I where P is the power output is the output voltage I is the output current P is the power from the supply driving the / 689 devices is the supply input voltage and I is the supply input current. Ideal Efficiency The ideal efficiency is not the true power efficiency because it is not calculated relative to the input power which includes the input current losses in the charge pump. The ideal efficiency can be determined with the following equation: P Efficiency (IDEAL) = x 00% P (IDEAL) where P (IDEAL) = - x - and P is the measured power output. Both efficiencies are provided to designers for comparison. V+ f C C Actual Efficiency To determine the actual efficiency of the / 689 device operation a designer can use the following equation: P Efficiency (ACTUAL) = x 00% P V+ Requivalent Requivalent = f x C C DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation Figure. Equivalent Circuit for an Ideal Switched Capacitor

12 APPLICATION FORMATION For the following applications C = C = 0µF for the and C = C =.µf for the. Capacitor Selection Low ESR capacitors are needed to obtain low output resistance. Refer to Table for some suggested low ESR capacitors. The output resistance of the /689 devices is a function of the ESR of C and C. This output resistance can be determined by the equation previously provided in the Efficiency section: R x ( x R SWITCHES + ESR C ) + ESR C + fosc x C where R is the circuit output resistance R SWITCHES is the internal resistance of the MOSFET switches ESR C and ESR C are the ESR of their respective capacitors and f OSC is the oscillator frequency. This term with f OSC is derived from an ideal switched-capacitor circuit as seen in Figure. Minimizing the ESR of C and C will minimize the total output resistance and will improve the efficiency. Flying Capacitor Decreasing flying capacitor C values will increase the output resistance of the / 689 devices while increasing C will reduce the output resistance. There is a point where increasing C will have a negligible effect on the output resistance due to the the domination of the output resistance by the internal MOSFET switch resistance and the total capacitor ESR. Output Capacitor Increasing output capacitor C values will decrease the output ripple voltage. Reducing the ESR of C will reduce both output ripple voltage and output resistance. If higher output ripple can be tolerated in designs smaller capacitance values for C should be used with light loads. The following equation can be used to calculate the peak-to-peak ripple voltage: Input Bypass Capacitor The bypass capacitor at the input pin will reduce AC impedance and the impact of any of the /689 devices' switching noise. It is recommended that for heavy loads a bypass capacitor approximately equal to the flying capacitor C be used. For light loads the value of the bypass capacitor can be reduced. When loading the /689 devices from to the input current remains constant (disregarding any spikes due to internal switching). Implementing a 0.µF bypass capacitor should be sufficient. When loading the /689 devices from to the current from the supply will flow into the input for half of the cycle and will be zero for the other half of the cycle. Designers should implement a large bypass capacitor (C = C) if the supply has a high AC impedance. Negative Voltage Converter The typical operating circuit for the / 689 devices is a negative voltage converter. Refer to Figure 9. This circuit is used to obtain the Typical Performance Characteristics found in Figures to 8 (unless otherwise noted). Voltage Inverter with the Load from to A designer can find the most common application for the /689 devices in Figure 0 as a voltage inverter. The only external components needed are capacitors: the flying capacitor C the output capacitor C and the bypass capacitor C (if necessary). Driving Excessive Loads The output should never be pulled above ground. A designer should implement a Schottky diode (N87) from to when driving heavy loads where a higher supply is sourcing current into. Refer to Figure for this circuit connection. V RIPPLE = x I x ESR C + I f OSC x C. DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

13 N87 Figure. Protection for Heavy Loads C + D = D = N8 D D C C C- C = ( x ) - V FD - V FD = - where = positive doubled output voltage = input voltage V FD = forward bias voltage across D V FD = forward bias voltage across D and = inverted output voltage. Figure. /689 Device Connected in a Doubler/Inverter Combination Circuit DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

14 + ON OFF Shutdown Logic C C 0.µF C- C Figure. /689 Device with Shutdown Control Combining a Doubler and Inverter Circuit A designer can connect a /689 device in a combination doubler/inverter circuit as seen in Figure. The doubler uses capacitors C and C while the inverter uses C and C. Loading either output decreases both output voltages to because both the doubler and the inverter circuits use the charge pump. Designers should not allow the total current output from the doubler and the inverter to exceed ma. Implementing Shutdown If shutdown control of the /689 devices is necessary the circuit found in Figure can be implemented. The 0.µF capacitor at absorbs transient input currents. The output resistance of the devices can be determined by the following equation: R = 0 + x R BUFFER where R is the output resistance and R BUFFER is the output resistance of the buffer driving. R BUFFER can be reduced by connecting multiple buffers in parallel at. The polarity of the SHUTDOWN signal can be changed by using a noninverting buffer to drive. Connecting in Parallel A designer can parallel a number of / 689 devices to reduce the output resistance for specific designs. All devices will need their own flying capacitor C but a single output capacitor will serve all of the devices connected in parallel by increasing the capacitance of C by a factor of n where n equals the total number of devices connected. This connection can be found in Figure 6. Cascading Devices A designer can cascade /689 devices to produce a larger inverted voltage output. Refer to Figure 7 for this circuit connection. With two cascaded devices the unloaded output voltage is decreased by the output resistance of the first device multiplied by the quiescent current of the second device connected. The total output resistance is greatly increased when more than two devices are cascaded. Layout and Grounding Designers should make an effort to minimize noise by paying special attention to the circuit layout with the /689 devices. External components should be connected in close proximity to the device and a ground plane should be implemented. This will keep electrical traces short minimizing parasitic inductance and capacitance. DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

15 + C C C C- C- C- n RL = - R TOT = R n where = output voltage = input voltage R TOT = total resistance of the devices connected in parallel R = the output resistance of a single device and n = the total number of devices connected in parallel. C x n Figure 6. /689 Devices Connected in Parallel to Reduce Total Output Resistance + C C C C- C- C- n C C C = -n x where = output voltage = input voltage and n = the total number of devices connected. Figure 7. /689 Devices Cascaded to Increase Output Voltage SIPEX PART NUMBER MANUFACTURER PART NUMBER CAPACITANCE / VOLTAGE MAX 00kHz PACKAGE AVX TPSC06*0 0µ F / V 0. Ω SM Case C SPRAGUE 9D06X0 0µ F / V 0. Ω SM Case D KEMET T9C06*00 0µ F / 0V 0. Ω SM Case C SANYO-OSCON 9SC06X006C 0µ F / 6V 0.Ω Radial Case C KEMET T9B*00. µ F / 0V. Ω SM Case B SPRAGUE 9DX00. µ F / V. 0Ω SM Case C SANYO-OSCON 9SCX006A. µ F / 6V 0.Ω Radial Case A Table. Suggested Low ESR Tantalum Capacitors DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation

16 PACKAGE: SOT- b C L e E e D C L C L a 0.0 DATUM 'A' A A A C E L A A.0 SYMBOL A M 0.90 MAX. A A b C D.80.0 E E.0.7 L e e 0.9ref.90ref a 0 O 0 O DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation 6

17 ORDERG FORMATION Model Temperature Range Package Type EK C to +8 C... SOT- -EK... - C to +8 C... SOT- EK/TR... - C to +8 C... SOT- -EK/TR... - C to +8 C... SOT- EK C to +8 C... SOT- EK/TR... - C to +8 C... SOT- Please consult the factory for pricing and availability on a Tape-On-Reel option. Available in lead free packaging. To order add "-L" suffix to the part number. Example: SP6660EU/TR=Tape & Reel. SP6660EU-L/TR = lead free. Corporation SIGNAL PROCESSG EXCELLENCE Sipex Corporation Headquarters and Sales Office Linnell Circle Billerica MA 08 TEL: (978) FAX: (978) sales@sipex.com Sales Office South Hillview Drive Milpitas CA 90 TEL: (8) FAX: (8) Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. DS/ /689 +V Low Power Voltage Inverter Copyright 000 Sipex Corporation 7

PART. Maxim Integrated Products 1

PART. Maxim Integrated Products 1 9-79; Rev ; 9/ SC7 Inverting Charge Pumps General Description The / monolithic, CMOS chargepump voltage inverters in the ultra-small SC7 package feature a low Ω output resistance, permitting loads up to