Analog Integrations Corporation 4F, 9 Industry E. 9th Rd, Science-Based Industrial Park, Hsinchu, Taiwan DS

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1 Triple-Output LCD Power Supply FEATURES One Low Dropout Linear Regulator Dropout Voltage 500mV at 0.3A Output Current Dual Adjustable Charge Pump Up to +30V Positive Output Down to -0V Negative Output Power Up Sequencing and Adjustable Delay time Power-Saving Shutdown Mode (0.µA typical) Operating Supply Voltage: 2V MHz Operation Frequency Internal Current Limit and Thermal Protection built in LDO part Few External Components Required APPLICATIONS LCD Monitors Digital Still Cameras PDAs TFT-LCD DESCRIPTION, composed of dual charge pumps and a regulator, provide three independent regulated voltages designed for using in thin-film transistor (TFT) liquid crystal display (LCD). The main regulator has an adjustable output voltage and a low dropout voltage of 500mV at 300mA load current is performed. The dual charge pumps independently regulate a positive output and a negative output. has thermal shutdown capability and survives a continuous short circuit from output to ground. A unique control scheme minimizes output ripple as well as output capacitance for both charge pump. MHz-switching frequency of provides a low noise, low cost total solution. The device operates up to 5V supply voltage and is available in 4-lead SOP package. Analog Integrations Corporation 4F, 9 Industry E. 9th Rd, Science-Based Industrial Park, Hsinchu, Taiwan DS TEL: FAX:

2 TYPICAL APPLICATION CIRCUIT C 2.2µF C2 0.47uF 28V/30mA I OUT BAT54S D 2V IN C IN 0µF 0.µF D2 BAT54S Co µf CFLY 0.µF CFLY2 + R 470k Cp nf R2 22k VCC SHDN TP GND SUPP SWP OUT ADJ TN SWN FBN VREF FBP PGND Cn 4.7nF CFLY3 R3 90k 0.µF I OUT3 0V/300mA + Co3 R4 0µF 30k R5 240k D3 BAT54S R6 33k C4 0.22µF I OUT2-9V/30mA Co2 µf C IN, C O3 : HER-MEI Electrolysis Capacitor, LER00MCD or TAIYO YUDEN Ceramic Capacitor, EMK325BJ06MN-B (0µF/6V) C FLY, C FLY2 : TAIYO YUDEN Ceramic Capacitor, UMK22BJ04KG (0.µF/50V) C FLY3 : TAIYO YUDEN Ceramic Capacitor, EMK07BJ04KA (0.µF/6V) C O : TAIYO YUDEN Ceramic Capacitor, UMK22F05ZG (µf/50v) C O2 : TAIYO YUDEN Ceramic Capacitor, EMK22F05KG (µf/6v) D ~D 3 : WTE Schottky Diode, BAT54S ORDERING INFORMATION Fig. TFT-LCD Power Application CX XX PACKING TYPE TB: TUBE TR: TAPING & REEL PACKAGING TYPE S: SO-4 PIN CONFIGURATION TOP VIEW ADJ 4 GND OUT 2 3 VREF Example: CSTR in SO-4 Package & Taping & Reel Packing Type FBP SHDN VCC FBN TP TN SUPP 6 9 SWN SWP 7 8 PGND 2

3 ABSOLUTE MAXIMUM RATINGS VCC, SHDN to GND -0.3V to 8V FBN, FBP, VREF, ADJ, TN, TP -0.3V to 8V SWN, SWP -0.3V to (Vcc+0.3V) PGND to GND ±0.3V Operating Temperature -40 C to 85 C Storage Temperature Range -65 C to 50 C Lead Temperature (Soldering, 0 sec) 260 C Thermal Resistance, θ JA (Junction to Ambient) 00 C/W Note: Any stress beyond Absolute Maximum Ratings above may cause eternal damage to the device. TEST CIRCUIT Refer to TYPICAL APPLICATION CIRCUIT. ELECTRICAL CHARACTERISTICS (V IN =2V, C O =C O2 =µf, C O3 =0µF, C FLY =C FLY2 =C FLY3= 0.µF, T A =25 C, unless otherwise specified.) PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT Input Voltage Range V Quiescent Current V SHDN =2.4V, I OUT = 0mA ma Standby Current V SHDN =0.6V,Output OFF µa Thermal Shutdown Temperature 55 C LOW DROPOUT LINEAR REGULATOR TERMINAL SPECIFICATION Adjustable Voltage V Line Regulation V IN =2~5V, V OUT3 =0V, % I OUT3 =ma Load Regulation V IN =2V, I OUT3 =0.~300mA % Continuous Output Current V IN =2V 300 ma Current Limit V IN =2V, V OUT3=0V (Note) ma Dropout Voltage I OUT3 =300mA 500 mv 3

4 ELECTRICAL CHARACTERISTICS (Continued) PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT CHARGE PUMP TERMINAL SPECIFICATION FBP Threshold V FBN Threshold mv VREF Voltage I REF =250µA V Continuous Output Current V IN =2V 30 ma TP/TN Bias Current µa TP/TN Input Threshold V Switching Frequency MHz SUPP switch 5 0 Internal Switch On-Resistance SWP switch 5 0 Ω SWN switch 5 0 SHUTDOWN TERMINAL SPECIFICATIONS SHDN Pin Current V SHDN =2.4V 0. µa SHDN Pin Voltage Output ON 2.4 Output OFF 0.6 V Note: Current limit is measured by pulse testing. Note2: Specifications are guaranteed by Statistical Quality Controls (SQC), with no production test proved, when operating temperature ranges from -40 C to 85 C. 4

5 SHDN LDO Negative Charge Pump 0 Shutdown exit Delay time 0 0 0% 90% T 90% T2 Positive Charge Pump 0 T set by C N T2 set by C P Fig. 2 Power Up Sequencing TYPICAL PERFORMANCE CHARACTERISTICS V SHDN = 0~3V V O2=-0V, I O2=30mA VCC=2V Vo Vo3 V O =30V, I O =30mA Vo2 Fig. 3 Power- Up Sequence Fig 4. Ripple Voltage Waveforms 5

6 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) V CC =2V, V O3 =0V, C O3 =0µF, Io3=300mA V O3 I O3 VCC-VOUT (mv) VCC=2V Fig. 5 LDO Load Transient Response I OUT (ma) Fig. 6 Dropout Voltage vs. LDO Load VCC-VOUT (mv) I OUT =300mA Current Limit (ma) Temperature ( C) Fig. 7 LDO Dropout Voltage vs. Temperature Temperature ( C) Fig. 8 LDO Current Limit vs. Temperature VCC-VOUT (mv) I OUT =300mA V CC (V) Fig. 9 LDO Dropout Voltage vs. Input Voltage TN/TP Bias Current (µa) Temperature ( C) Fig. 0 TN/TP Bias Current vs. Temperature 6

7 TYPICAL PERFORMANCE CHARACTERISTICS (Continued) VREF (V) VNEG (V) V CC =V V CC =2V Temperature ( C) Fig. V REF vs. Temperature -0.4 V CC =3V I NEG (ma) Fig. 2 Negative Charge-Pump vs. Load Current VPOS (V) V CC =V V CC =2V V CC =3V Efficiency (%) V NEG =-0V V CC =V V CC =2V V CC =3V I POS (ma) Fig. 3 Positive Charge Pump vs. Load Current I NEG (ma) Fig. 4 Negative Charge-Pump vs. Load Current V POS =30V V CC =V V CC =2V Efficiency (%) V CC =3V I POS (ma) Fig. 5 Positive Charge-Pump Efficiency vs. Load Current 7

8 BLOCK DIAGRAM ADJ TP FBP FBN VREF EA EA EA SHDN Shutdown SUPP 7 SWP VCC VCC 90%VREF 5µA 5µA 5V 0%VREF 5V OSC 2 FBN Current OUT 2 ADJ.25V Reference Voltage Limit Shutdown Thermal GND VREF TP TN SWN PGND 5 VCC FBP 4 3 COMP - + COMP - + Q Q2 Q3 Q4 Q5 Q6 Q7 8

9 PIN DESCRIPTIONS PIN : ADJ - Providing V ADJ =.25V (typ.) for adjustable V OUT. PIN 2: OUT - Adjustable LDO regulator output. PIN 3: FBP - Positive charge pump feedback input. Regulates to.25v typical. PIN 4: SHDN - Active-Low logic level shutdown PIN 5: VCC PIN 6: SUPP PIN 7: SWP PIN 8: PGND PIN 9: SWN PIN 0: TN input. Connecting SHDN to VCC for typical operation. - Supply input. - Positive charge pump supply pin. It monitors negative charge pump. - Positive charge pump driver output. Output high level is VCC, and low level is GND. - Power ground. Connecting to GND. - Negative charge pump driver output. Output high level is VCC, and low level is GND. - Programmable delay time pin. PIN : TP PIN 2: FBN The capacitor on this pin sets negative charge pump to provide independent time control. Or TN connects to high level directly if it is not in use for programming delay time. - Programmable delay time pin. The capacitor on this pin sets positive charge pump to provide independent time control. Or TP connects to high level directly if it is not in use for programming delay time. - Negative charge pump feedback input. Regulates to 0V typical. PIN 3: VREF - Internal reference bypass terminal. Connecting a 0.22µF capacitor to ground. Providing a positive voltage greater than negative feedback voltage to obtain a positive voltage for FBN. PIN 4: GND - Ground. Tie GND pin directly to local ground plane to obtain best performance. APPLICATION INFORMATIONS Introduction is composed of dual charge pumps and a regulator to provide three independent regulated voltages exclusively designed for thin-film transistor (TFT) liquid crystal display (LCD) applications. LDO regulator has an adjustable output voltage with a low dropout voltage of 500mV at 300mA load current. Two independent charge pumps regulate a positive output and a negative output by using a MHz switching frequency, and a pulse-width-modulation (PWM) architecture. provides a start-up sequence function with an adjustable start-up delay time. In shutdown mode, it only consumes 0.µA supply current. also features an internal current limit and thermal shutdown protection. Operation As Fig. 6 shows, two internal MOSFETs - Q2, Q3, and external components comprise a positive charge pump, whose output is three times as much as input voltage. After delay time, which determined by C P, Q turns on. During on state, which indicates 9

10 Q2 is at off stage and Q3 at on stage, C FLY connects V CC and PGND and is charged by V CC. During off state, Q2 at on stage and Q3 off stage, voltage of C2 is the addition of V CC and V CFLY. And then go back to on state with voltage of C FLY2 equal to V C2, which is twice as much voltage as V CC. Lastly, the system goes to off state, voltage of Co is the addition of V CC and C FLY2, that is, three times as much voltage as V CC. VCC SWN Q4 CFLY3 3 Q5 FBN VREF D3 2 R5 R6 C5 Vn - Co2 + Fig.7 shows the structure of a negative charge pump. During on state, which represents Q4 at on stage and Q5 at off stage, voltage of C FLY3 is equal to V CC. During off state, indicating Q4 at off stage and Q5 on stage, SWN pin connects to PGND directly, and voltage of Co2 equals to -V CC. 2V IN VCC Q D SUPP Q2 CFLY C SWP 3 2 FBP Q3 D2 C2 PGND CFLY2 3 2 Vp + - Co R R2 C3 Fig.6 Structure of Positive Charge Pump PGND C4 Fig. 7 Structure of Negative Charge Pump Power-Up Sequence And Adjustable Delay Time For thin-film transistor (TFT) liquid crystal display applications, power-up sequence of three output voltages is required. Fig. 3 indicates the power-up sequence of. After shutdown exit delay time, output of LDO starts rising. When it reaches to 90% of normal voltage, which is determined by an external resistor divider, C N starts being charged from 5µA current source (referring to BLOCK DIAGRAM). The charging time of C N, defined as T, can be calculated as VTH,n T = Cn () I n where V TH,η = negative threshold voltage,.25v, In = negative bias current, 5µA Afterwards, while negative output voltage starts decreasing from 0V, V FBN decreases from.v to 0V proportionally. As V FBN decreases to 0% of V REF, Q7 turns off and Cp starts being charged from 5µA current source (referring to BLOCK DIAGRAM). The charging time of C P, defined as T2, can be calculated as 0

11 VTH,P T 2 = Cp (2) I P where V TH,P = positive threshold voltage,.25v I P = positive bias current, 5µA Current Limit And Thermal Protection To protect devices from damage caused by short circuit, provides current limit and thermal protection. When short circuit occurs, output current is clamped at the current limit. Due to power dissipation of LDO is defined as P DISSIPATION = I OUT * (V IN -V OUT ) (3) Under short circuit condition, the temperature rising, which is caused by power dissipation, gets to thermal shutdown temperature and shuts down. As the temperature gets lower than the thermal shutdown temperature, the device will resume. The pattern of temperature of the device recycles until the short circuit condition is removed. The waveform under short circuit condition is shown as Fig.8. Shutdown shuts off all devices and consumes only 0.µA supple current when SHDN gets lower than 0.6V. This pin can be pulled high to 2.4V for normal operation. Due to high impedance of SHDN pin, it can t be floating. Components Selection. Determining The Number Of Charge Pump Stages The number of charge pump stages to regulate is determined by output voltage, supply voltage, switching frequency, load current, forward voltage of diodes, on-resistor of internal MOSFET, and value of ceramic capacitor. For positive charge pump, the number of required stages can be calculated as N POS VPOS Vcc + RTH Iout (4) Vcc 2V D Current Limit I OUT where V POS = output of positive charge pump R TH = equivalent output impedance of charge pump V D = forward voltage of diodes Vcc = input voltage V OUT Thermal Shutdown The following equation approximates R TH R TH = (RDS,ON(P) + RDS,ON(N ) + ( ) + ( ) C F C F 2 ) FLY SW O SW Fig.8 Current Limit Waveform of (5) where R DS, ON(P) is on-resistor of internal P-channel MOSFET, R DS, ON(N) means on-resistor of internal N-channel MOSFET, and F SW is switching frequency of (referring to ELECTRIVAL CHARACTERISTICS).

12 For negative charge pump, the number of negative charge pump can be determined by N NEG V R3 = VADJ ( ) (0) R4 LDO + RTH Iout VNEG (6) where V Vcc 2V LDO = output voltage of LDO D V ADJ = adjustable voltage of LDO, the where V NEG = output of negative charge pump recommended R4 is 30kΩ. Example To obtain V POS =28V/30mA, V NEG =-9V/30mA from V CC =2V, C FLY =0.µF, the number of positive and negative charge pumps can be calculated as follows R TH = 2(R DS,ON(P) + R DS,ON(N) ) + ( C FLY = 2(0 + 0) + ( F SW ) + ( C ) + ( 0 6 O F SW 0 =5 (7) N POS V POS Vcc + R Vcc 2V TH D Iout ( = =.59 (8) N NEG R TH Iout V Vcc 2VD = 0.96 NEG 3 ( ) ( 9) = (9) Thus, the number of positive charge pump is two, and the negative one requires one charge pump. 2. Output Voltage Selection 2. Output voltage of LDO A resistor divider, determining output voltage of LDO, connects to OUT, GND, and ADJ (referred to TYPICAL APPLICATION CIRCUIT). Values of resistors can be calculated by equation (0). 6 3 ) ) ) 2.2. Output Voltage Of Positive Charge Pump Output voltage of positive charge pump is determined by connecting a resistor divider to output terminal of positive charge pump, GND, and FBP (referred to TYPICAL APPLICATION CIRCUIT). The values of resistor divider can be calculated as equation (). V R = VFBP ( ) () R2 POS + where V POS = output voltage of positive charge pump V FBP = feedback voltage of positive charge pump,.25v. The recommended R2 is 22kΩ 2.3 Output voltage of negative charge pump Since comparator input of negative charge pump, FBN, is referenced to 0V, a positive reference voltage, which can be obtained by adding a 0.22µF bypass capacitor between VREF and GND, is needed (referred to TYPICAL APPLICATION CIRCUIT). The value of resistor dividers can be calculated as equation (2). V R5 = VREF (2) R6 NEG where V NEG represents output voltage of negative charge pump, and V REF means reference voltage,.25v. The recommended R6 is 33kΩ. 2

13 3. Flying Capacitor Selection A flying capacitor plays an important role in charge pump strength. Increase of flying capacitor value results in a rise of output capability with smaller ripple voltage. Normal voltage of flying capacitor must comply with the following conditions, as equation (3). V CFLY (POS) = V CFLY (NEG) >.5 x [V CC x (N)]...(3) Where V CFLY(POS) is the normal voltage of positive charge pump flying capacitor, V CFLY(NEG) represents the normal voltage of negative charge pump flying capacitor, and N means the number of charge pump stages Besides, ceramic capacitors composed by different materials, such as X7R, X5R, Z5U and Y5V, have different tolerance in temperature, and result in different capacitance loss. A capacitor, which is made of X7R or X5R, is recommended for applications. 4. Input-Output Capacitor Selection maintain stability. The recommended values for both input and output capacitors are 0µF. Because of the material, X5R or X7R, ceramic capacitor has low ESR and excellent electrical characteristics in over temperature. That makes ceramic capacitor suitable for output and input capacitors of. 4.2 Charge Pump A ceramic capacitor of a value, which is 0 times of flying capacitor, is suitable for the output capacitor of charge pump. In order to maintain a stable output voltage, make sure to place the capacitor as close to IC as possible. 5. Rectifier Diode Selection A Schottky diode with a current rating equal to or greater than two times of average charge pump input current, and a voltage rating at least.5 times of V CC, is recommended. Table indicates the recommended components for applications. 4. LDO needs input and output capacitors to Table. Bill of Materials List Designator Part Type Description Vender Phone C IN 0µF/6V Ceramic capacitor, EMK325BJ06MN-B Taiyo Yuden C FLY 0.µF/50V Ceramic capacitor, UMK22BJ04KG Taiyo Yuden C FLY2 0.µF/50V Ceramic capacitor, UMK22BJ04KG Taiyo Yuden C FLY3 0.µF/6V Ceramic capacitor, EMK07BJ04KA Taiyo Yuden C O µf/50v Ceramic capacitor, UMK22F05ZG Taiyo Yuden C O2 µf/6v Ceramic capacitor, EMK22F05KG Taiyo Yuden C O3 0µF/6V Ceramic capacitor, EMK325BJ06MN-B Taiyo Yuden D~D3 BAT54SW Surface mount Schottky barrier diode WTE U Triple Adjustable Output DC/DC Converter with a LDO AIC

and maximum width of trace for best performance.

14 Layout Consideration Due to the switching frequency of, careful PCB layout is necessary. Place components as close to one another as possible and maintain each connection of minimum length and maximum width of trace for best performance. Make sure each device connect to its immediate ground plane. Fig 9, 20 and 2 represent recommended layouts. Fig. 9 Top Layer Fig. 20 Bottom Layer Fig. 2 Top-over Layer 4

15 PHYSICAL DIMENSIONS (unit: mm) 4 LEAD PLASTIC SO (CS) B D e A E A H C L SYMBOL MIN MAX A A B C D E e.27(typ) H L Note: Information provided by AIC is believed to be accurate and reliable. However, we cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in an AIC product; nor for any infringement of patents or other rights of third parties that may result from its use. We reserve the right to change the circuitry and specifications without notice. Life Support Policy: AIC does not authorize any AIC product for use in life support devices and/or systems. Life support devices or systems are devices or systems which, (I) are intended for surgical implant into the body or (ii) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5

Analog Integrations Corporation Si-Soft Research Center DS-1533G A1, No.1, Li-Hsin Rd. I, Science Park, Hsinchu 300, Taiwan, R.O.C.

Analog Integrations Corporation Si-Soft Research Center DS-1533G A1, No.1, Li-Hsin Rd. I, Science Park, Hsinchu 300, Taiwan, R.O.C. Triple-Output LCD Power Supply FEATURES One Low Dropout Linear Regulator Dropout Voltage 500mV at 0.3A Output Current Dual Adjustable Charge Pump Up to +30V Positive Output Down to -0V Negative Output