DATASHEET CD4015BMS. Pinout. Features. Functional Diagram. Applications. Description

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1 ATASHEET CBMS CMOS ual -Stage Static Shift egister With Serial Input/Parallel Output FN39 ev. Features Pinout High-Voltage Type (V ating) Medium Speed Operation MHz (typ.) Clock ate at V - VSS = OCK B CBMS TOP VIEW V Fully Static Operation B ATA B 8 Master-Slave Flip-Flops Plus Input and Output Buffering 3A 3 ESET B % Tested For uiescent Current at V A 3 B V, and V Parametric atings Standardized Symmetrical Output Characteristics Maximum Input Current of A at 8V Over Full Package-Temperature ange; na at 8V and o C A ESET A ATA A VSS B 3B A OCK A Noise Margin (Full Package-Temperature ange) = - V at V = V - V at V = -.V at V = V Meets All equirements of JEEC Tentative Standard No. 3B, Standard Specifications for escription of B Series CMOS evices Functional iagram V Applications Serial-Input/Parallel-Output ata ueueing Serial to Parallel ata Conversion General-Purpose egister escription CBMS consists of two identical, independent, -stage serial-input/parallel output registers. Each register has independent OCK and ESET inputs as well as a single serial ATA input. outputs are available from each of the four stages on both registers. All register stages are type, master-slave flip-flops. The logic level present at the ATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. esetting of all stages is accomplished by a high level on the reset line. egister expansion to 8 stages using one CBMS package, or to more than 8 stages using additional CBMS s is possible. ATA A OCK A ESET A ATA B OCK B ESET B 7 9 STAGE STAGE 8 VSS 3 3 A A 3A A B B 3B B The CBMS is supplied in these lead outline packages: Braze Seal IP Frit Seal IP Ceramic Flatpack HX HF HW FN39 ev. Page of 8

2 CBMS Absolute Maximum atings C Supply Voltage ange, (V) V to +V (Voltage eferenced to VSS Terminals) Input Voltage ange, All Inputs V to V +.V C Input Current, Any One Input ma Operating Temperature ange to + o C Package Types, F, K, H Storage Temperature ange (TSTG) o C to + o C Lead Temperature (uring Soldering) o C At istance / /3 Inch (.9mm.79mm) from case for s Maximum eliability Information Thermal esistance ja jc Ceramic IP and FIT Package o C/W o C/W Flatpack Package o C/W o C/W Maximum Package Power issipation (P) at + o C For TA = to + o C (Package Type, F, K) mw For TA = + o C to + o C (Package Type, F, K)..... erate Linearity at mw/ o C to mw evice issipation per Output Transistor mw For TA = Full Package Temperature ange (All Package Types) Junction Temperature o C TABLE. C ELECTICAL PEFOMANCE CHAACTEISTICS GOUP A PAAMETE SYMBOL CONITIONS (NOTE ) SUBGOUPS TEMPEATUE MIN MAX UNITS Supply Current I V = V, VIN = V or GN + o C - A + o C - A V = 8V, VIN = V or GN 3 - A Input Leakage Current IIL VIN = V or GN V = + o C - - na + o C - - na V = 8V na Input Leakage Current IIH VIN = V or GN V = + o C - na + o C - na V = 8V 3 - na Output Voltage VOL V = V, No Load,, 3 + o C, + o C, - mv Output Voltage VOH V = V, No Load (Note 3),, 3 + o C, + o C,.9 - V Output Current (Sink) IOL V = V, VOUT =.V + o C.3 - ma Output Current (Sink) IOL V =, VOUT =.V + o C. - ma Output Current (Sink) IOL V = V, VOUT =.V + o C 3. - ma Output Current (Source) IOHA V = V, VOUT =.V + o C ma Output Current (Source) IOHB V = V, VOUT =.V + o C ma Output Current (Source) IOH V =, VOUT = 9.V + o C - -. ma Output Current (Source) IOH V = V, VOUT = 3.V + o C ma N Threshold Voltage VNTH V =, ISS = - A + o C V P Threshold Voltage VPTH VSS = V, I = A + o C.7.8 V Functional F V =.8V, VIN = V or GN 7 + o C VOH > VOL < V V = V, VIN = V or GN 7 + o C V/ V/ V = 8V, VIN = V or GN 8A + o C V = 3V, VIN = V or GN 8B Input Voltage Low (Note ) VIL V = V, VOH >.V, VOL <.V,, 3 + o C, + o C, -. V Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) NOTES: VIH V = V, VOH >.V, VOL <.V,, 3 + o C, + o C, 3. - V VIL VIH V = V, VOH > 3.V, VOL <.V V = V, VOH > 3.V, VOL <.V. All voltages referenced to device GN, % testing being implemented.. Go/No Go test with limits applied to inputs,, 3 + o C, + o C, - V,, 3 + o C, + o C, - V 3. For accuracy, voltage is measured differentially to V. Limit is.v max. FN39 ev. Page of 8

3 CBMS TABLE. AC ELECTICAL PEFOMANCE CHAACTEISTICS GOUP A PAAMETE SYMBOL CONITIONS (NOTE, ) SUBGOUPS TEMPEATUE MIN MAX UNITS Propagation elay TPHL V = V, VIN = V or GN 9 + o C - 3 ns Clock To TPLH, + o C, - 3 ns Propagation elay TPHL V = V, VIN = V or GN 9 + o C - ns eset To, + o C, - ns Transition Time TTHL V = V, VIN = V or GN 9 + o C - ns TTLH, + o C, - 7 ns Maximum Clock Input F V = V, VIN = V or GN 9 + o C 3 - MHz Frequency, + o C, 3/.3 - MHz NOTES:. = pf, L = K, Input T, TF < ns.. and + o C limits guaranteed, % testing being implemented. TABLE 3. ELECTICAL PEFOMANCE CHAACTEISTICS PAAMETE SYMBOL CONITIONS NOTES TEMPEATUE MIN MAX UNITS Supply Current I V = V, VIN = V or GN,, + o C - A + o C - A V =, VIN = V or GN,, + o C - A + o C - 3 A V = V, VIN = V or GN,, + o C - A + o C - A Output Voltage VOL V = V, No Load, + o C, + o C, - mv Output Voltage VOL V =, No Load, + o C, + o C, - mv Output Voltage VOH V = V, No Load, + o C, + o C,.9 - V Output Voltage VOH V =, No Load, + o C, + o C, V Output Current (Sink) IOL V = V, VOUT =.V, + o C.3 - ma. - ma Output Current (Sink) IOL V =, VOUT =.V, + o C.9 - ma. - ma Output Current (Sink) IOL V = V, VOUT =.V, + o C. - ma. - ma Output Current (Source) IOHA V = V, VOUT =.V, + o C ma - -. ma Output Current (Source) IOHB V = V, VOUT =.V, + o C - -. ma - -. ma Output Current (Source) IOH V =, VOUT = 9.V, + o C ma - -. ma Output Current (Source) IOH V =V, VOUT = 3.V, + o C - -. ma - -. ma Input Voltage Low VIL V =, VOH > 9V, VOL < V, + o C, + o C, - 3 V Input Voltage High VIH V =, VOH > 9V, VOL < V, + o C, + o C, +7 - V FN39 ev. Page 3 of 8

4 CBMS Propagation elay Clock To Propagation elay eset To Transition Time Maximum Clock Input Frequency Minimum ata Setup Time Clock ise and Fall Time Minimum Clock Pulse Width TABLE 3. ELECTICAL PEFOMANCE CHAACTEISTICS (Continued) PAAMETE SYMBOL CONITIONS NOTES TEMPEATUE TPHL TPLH V =,, 3 + o C - ns V = V,, 3 + o C - ns TPHL V =,, 3 + o C - ns V = V,, 3 + o C - ns TTHL V =,, 3 + o C - ns TTLH V = V,, 3 + o C - 8 ns F V =,, 3 + o C - MHz V = V,, 3 + o C 8. - MHz TS V = V,, 3 + o C - 7 ns V =,, 3 + o C - ns V = V,, 3 + o C - 3 ns T V = V,, 3 + o C - s TF V =,, 3 + o C - s V = V,, 3 + o C - s TW V = V,, 3 + o C - 8 ns V =,, 3 + o C - 8 ns V = V,, 3 + o C - ns Minimum eset Pulse TW V = V, 3 + o C - ns Width V =, 3 + o C - 8 ns V = V, 3 + o C - ns Input Capacitance CIN Any Input, + o C - 7. pf NOTES:. All voltages referenced to device GN.. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. = pf, L = K, Input T, TF < ns. MIN MAX UNITS TABLE. POST IAIATION ELECTICAL PEFOMANCE CHAACTEISTICS PAAMETE SYMBOL CONITIONS NOTES TEMPEATUE MIN MAX UNITS Supply Current I V = V, VIN = V or GN, + o C - A N Threshold Voltage VNTH V =, ISS = - A, + o C V N Threshold Voltage VNTH V =, ISS= - A, + o C - V elta P Threshold Voltage VPTH VSS = V, I = A, + o C..8 V P Threshold Voltage VPTH VSS = V, I = A, + o C - V elta Functional F V = 8V, VIN = V or GN V = 3V, VIN = V or GN + o C VOH > V/ Propagation elay Time TPHL TPLH NOTES:. All voltages referenced to device GN.. = pf, L = K, Input T, TF < ns. VOL < V/ V = V,, 3, + o C -.3 x + o C Limit 3. See Table for + o C limit.. ead and ecord V ns FN39 ev. Page of 8

5 CBMS TABLE. BUN-IN AN LIFE TEST ELTA PAAMETES + O C PAAMETE SYMBOL ELTA LIMIT Supply Current - MSI- I. A Output Current (Sink) IOL % x Pre-Test eading Output Current (Source) IOHA % x Pre-Test eading TABLE. APPLICABLE SUBGOUPS CONFOMANCE GOUP MIL-ST-883 METHO GOUP A SUBGOUPS EA AN ECO Initial Test (Pre Burn-In) %, 7, 9 I, IOL, IOHA Interim Test (Post Burn-In) %, 7, 9 I, IOL, IOHA Interim Test (Post Burn-In) %, 7, 9 I, IOL, IOHA PA (Note ) %, 7, 9, eltas Interim Test 3 (Post Burn-In) %, 7, 9 I, IOL, IOHA PA (Note ) %, 7, 9, eltas Final Test %, 3, 8A, 8B,, Group A Sample,, 3, 7, 8A, 8B, 9,, Group B Subgroup B- Sample,, 3, 7, 8A, 8B, 9,,, eltas Subgroups,, 3, 9,, Subgroup B- Sample, 7, 9 Group Sample,, 3, 8A, 8B, 9 Subgroups, 3 NOTE:. % Parameteric, 3% Functional; Cumulative for Static and. TABLE 7. TOTAL OSE IAIATION MIL-ST-883 TEST EA AN ECO CONFOMANCE GOUPS METHO PE-IA POST-IA PE-IA POST-IA Group E Subgroup, 7, 9 Table, 9 Table TABLE 8. BUN-IN AN IAIATION TEST CONNECTIONS OSCILLATO FUNCTION OPEN GOUN V 9V -.V khz khz Static Burn-In Note Static Burn-In Note ynamic Burn- In Note Irradiation Note -, - 3, - 9,, -, - 3 8,, 7, 9, - -, 8, -, - 3, 9 7, -, - 3 8,, 7, 9, - NOTE:. Each pin except V and GN will have a series resistor of K %, V = 8V.V. Each pin except V and GN will have a series resistor of 7K %; Group E, Subgroup, sample size is dice/wafer, failures, V =.V FN39 ev. Page of 8

6 CBMS Logic iagram 3 () () 3 (3) () ATA * (7) OCK * (9) ESET * () V p n p n VSS *ALL INPUTS AE POTECTE BY CMOS POTECTION NETWOK p n FIGUE. CBMS LOGIC IAGAM p n TUTH TABLE ± n n- n- X n (No Change) X X X = on t care Case Copyright Intersil Americas LLC 999. All ights eserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN39 ev. Page of 8

7 CBMS Typical Performance Characteristics OUTPUT LOW (SINK) CUENT (IOL) (ma) 3 GATE-TO-SOUCE VOLTAGE (VGS) = V V AIN-TO-SOUCE VOLTAGE (VS) (V) FIGUE. TYPICAL OUTPUT LOW (SINK) CUENT CHAACTEISTICS OUTPUT LOW (SINK) CUENT (IOL) (ma). 7.. V GATE-TO-SOUCE VOLTAGE (VGS) = -V AIN-TO-SOUCE VOLTAGE (VS) (V) FIGUE 3. MINIMUM OUTPUT LOW (SINK) CUENT CHAACTEISTICS AIN-TO-SOUCE VOLTAGE (VS) (V) GATE-TO-SOUCE VOLTAGE (VGS) = -V - -V OUTPUT HIGH (SOUCE) CUENT (IOH) (ma) AIN-TO-SOUCE VOLTAGE (VS) (V) GATE-TO-SOUCE VOLTAGE (VGS) = -V - -V OUTPUT HIGH (SOUCE) CUENT (IOH) (ma) FIGUE. TYPICAL OUTPUT HIGH (SOUCE) CUENT CHAACTEISTICS FIGUE. MINIMUM OUTPUT HIGH (SOUCE) CUENT CHAACTEISTICS TANSITION TIME (tthl, ttlh) (ns) SUPPLY VOLTAGE (V) = V V 8 LOA CAPACITANCE () (pf) POPAGATION ELAY TIME (tphl, tplh) (ns) SUPPLY VOLTAGE (V) = V 8 LOA CAPACITANCE () (pf) V FIGUE. TYPICAL TANSITION TIME AS A FUNCTION OF LOA CAPACITANCE FIGUE 7. TYPICAL POPAGATION ELAY TIME AS A FUNCTION OF LOA CAPACITANCE FN39 ev. Page 7 of 8

8 CBMS Typical Performance Characteristics (Continued) POWE ISSIPATION (P) ( W) SUPPLY VOLTAGE (V) = V V = pf = pf tr, tf = ns L = k OCK INPUT FEUENCY (f) (khz) FIGUE 8. TYPICAL POWE ISSIPATION AS A FUNCTION OF FEUENCY Chip imensions and Pad Layout 8 3 METALLIZATION: Thickness: kå kå, AL. PASSIVATION:.kÅ -.kå, Silane BON PAS:. inches X. inches MIN IE THICKNESS:.98 inches -.8 inches 3 98 IE SIZE: X = 8 (77-8) = (.9 -.9) Y = 98 (9-3) = (.3 -.) imensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( -3 inch) FN39 ev. Page 8 of 8

DATASHEET CD4020BMS, CD4024BMS, CD4040BMS. Pinouts. Features. Applications. Description. CMOS Ripple-Carry BinaryCounter/Dividers

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