DATASHEET. Features. Pin Configuration HS1-1840ARH, HS1-1840AEH, HS1-1840BRH, HS1-1840BEH (28 LD SBDIP) CDIP2-T28 TOP VIEW

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1 DTSHEET HS-0H, HS-0EH, HS-0BH, HS-0BEH ad-hard Channel BiCOS nalog ultiplexer with High-Z nalog Input Protection FN ev.00 The HS-0H, HS-0EH, HS-0BH and HS-0BEH are radiation hardened, monolithic channel multiplexers constructed with the Intersil ad-hard Silicon Gate, bonded wafer, Dielectric Isolation process. They are designed to provide a high input impedance to the analog source if device power fails (open), or the analog signal voltage inadvertently exceeds the supply by up to V, regardless of whether the device is powered on or off. Excellent for use in redundant applications, since the secondary device can be operated in a standby unpowered mode affording no additional power drain. ore significantly, a very high impedance exists between the active and inactive devices preventing any interaction. One of sixteen channel selections is controlled by a -bit binary address plus an Enable-Inhibit input which conveniently controls the ON/OFF operation of several multiplexers in a system. ll inputs have electrostatic discharge protection. The HS-0H, HS-0EH, HS-0BH and HS-0BEH are processed and screened in full compliance with IL-PF- and QL standards. The devices are available in a Ld SBDIP and a Ld Ceramic Flatpack. Specifications for ad Hard QL devices are controlled by the Defense Logistics gency Land and aritime (DL). The SD numbers listed here must be used when ordering. Features Electrically screened to SD # -0 QL qualified per IL-PF- requirements Pin-to-pin for Intersil s HS-0H and HS-0/S Improved radiation performance - Gamma dose ( ) x0 D(Si) Improved r DS(ON) Linearity Improved access time.µs (ax) over temp and post rad High analog input impedance 00 during power loss (open) V input overvoltage protection (power on or off) Dielectrically isolated device islands Excellent in Hi-el redundant systems Break-before-make switching No latch-up Detailed Electrical Specifications for these devices are contained in SD -0. Pin Configuration HS-0H, HS-0EH, HS-0BH, HS-0BEH ( LBDIP) CDIP-T TOP VIEW +V S IN IN IN IN IN IN IN 0 0 IN (+V S ) V EF DD IN IN IN IN IN IN IN IN ENBLE DD 0 DD DD HS-0H, HS-0EH, HS-0BH, HS-0BEH ( LD FLTPCK) CDFP-F TOP VIEW +V S IN IN IN IN IN IN IN 0 IN (+V S ) V EF DD 0 IN IN IN IN IN IN IN IN ENBLE DD 0 DD DD FN ev.00 Page of

2 HS-0H, HS-0EH, HS-0BH, HS-0BEH Ordering Information ODEING NUBE (Note ) INTENL KT. NUBE PT KING NO. TEP. NGE ( C) PCKGE (ohs Compliant) F00QXC HS-0H- Q F 00QXC - to + Ld SBDIP F00QYC HS-0H- Q F 00QYC - to + Ld Flatpack F00VXC HS-0H-Q Q F 00VXC - to + Ld SBDIP F00VYC HS-0H-Q Q F 00VYC - to + Ld Flatpack HS0-0H/SPLE HS0-0H/SPLE Die - to + HS-0H/POTO HS-0H/POTO HS- 0H /POTO - to + Ld SBDIP HS-0H/POTO HS-0H/POTO HS- 0H /POTO - to + Ld Flatpack 00TXC HS-0H-T Q 00TXC - to + Ld SBDIP F00V HS0-0H-Q Die - to + F00V HS0-0EH-Q Die - to + F00VXC HS-0EH-Q Q F 00VXC - to + Ld SBDIP F00VYC HS-0EH-Q Q F 00VYC - to + Ld Flatpack F00V HS0-0BEH-Q Die - to + F00VXC HS-0BEH-Q Q F 00VXC - to + Ld SBDIP F00VYC HS-0BEH-Q Q F 00VYC - to + Ld Flatpack F00QXC HS-0BH- Q F 00QXC - to + Ld SBDIP F00QYC HS-0BH- Q F 00QYC - to + Ld Flatpack F00VXC HS-0BH-Q Q F 00VXC - to + Ld SBDIP F00VYC HS-0BH-Q Q F 00VYC - to + Ld Flatpack HS-0BH/POTO HS-0BH/POTO HS- 0BH /POTO - to + Ld SBDIP HS-0BH/POTO HS-0BH/POTO HS- 0BH /POTO - to + Ld Flatpack F00V HS0-0BH-Q Die - to + HS0-0BH/SPLE HS0-0BH/SPLE Die - to + F00VZC HSG-0H-Q (Note ) Q F 00VZC - to + Ld Flatpack HSG-0H/POTO HSG-0H/POTO (Note ) HSG-0H/POTO - to + Ld Flatpack. These Intersil Pb-free Hermetic packaged products employ 00% u plate - e termination finish, which is ohs compliant and compatible with both SnPb and Pb-free soldering operations.. The lid of these packages are connected to the ground pin of the device. FN ev.00 Page of

3 HS-0H, HS-0EH, HS-0BH, HS-0BEH Functional Diagram V DD 0 IN DIGITL DDESS INSWITCH EN IN INSWITCH DDESS INPUT BUFFE ND LEVEL SHIFTE DECODES ULTIPLEX SWITCHES NOTE: INSWITCH INXX: SWITCH ON, BODY TIED TO SOUCE SWITCH OFF, BODY TIED TO VCC-0.V TBLE. TUTH TBLE 0 EN ON CHNNEL X X X X H None L L L L L L L L H L L L H L L L L H H L L H L L L L H L H L L H H L L L H H H L H L L L L H L L H L 0 H L H L L H L H H L H H L L L H H L H L H H H L L H H H H L FN ev.00 Page of

4 HS-0H, HS-0EH, HS-0BH, HS-0BEH Burn-In/Life Test Circuits +V S F 0 F F F F +V S V 0 NOTE: V S + = +.V ±0.V, V S - = -.V ±0.V. = kω ±%. C = C = 0.0µF ±0%, ECH PE SOCKET, INIU. D = D = N00, ECH PE BOD, INIU. INPUT SIGNLS: SQUE WVE, 0% DUTY CYCLE, 0V TO V PEK ±0%. F = 00kHz; F = F/; F = F/; F = F/; F = F/. FIGUE. DYNIC BUN-IN ND LIFE TEST CICUIT NOTE: = kω ±%, /W. C = C = 0.0µF INIU, ECH PE SOCKET, INIU. V S + =.V ±0.V, V S - = -.V ±0.V, V =. ±0.V FIGUE..STTIC BUN-IN TEST CICUIT. The above test circuits are utilized for all package types.. The Dynamic Test Circuit is utilized for all life testing. Irradiation Circuit HS-0H, HS-0EH, HS-0BH, HS-0BEH +V -V k +V 0 +V NOTE:. ll irradiation testing is performed in the lead CEDIP package. FN ev.00 Page of

5 HS-0H, HS-0EH, HS-0BH, HS-0BEH Die Characteristics DIE DIENSIONS: (µmx00µm x µm. m) milsx milsx mils mil INTEFCE TEILS: Glassivation: Type: PSG (Phosphorus Silicon Glass) Thickness:.0kÅ kå Top etallization: Type: lsicu Thickness:.0kÅ kå Backside Finish: Silicon SSEBLY ELTED INFOTION: Substrate Potential: Unbiased (DI) DDITIONL INFOTION: Worst Case Current Density: odified SE Transistor Count: 0 Process: adiation Hardened Silicon Gate, DI Wafer, Dielectric Isolation etallization ask Layout HS-0H, HS-0BH IN IN IN IN IN IN IN IN ENBLE -V 0 +V V EF IN IN IN IN IN IN IN0 IN FN ev.00 Page of

6 HS-0H, HS-0EH, HS-0BH, HS-0BEH Ceramic Dual-In-Line etal Seal Packages (SBDIP) BSE PLNE SETING PLNE S b ccc bbb S b C - B S C - B D e S. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. Dimensions b and c apply to lead base metal only. Dimension applies to lead plating and finish thickness.. Corner leads (, N, N/, and N/+) may be configured with a partial lead paddle. For this configuration dimension b replaces dimension b.. Dimension Q shall be measured from the seating plane to the base plane.. easure dimension S at all four corners.. easure dimension S from the top of the ceramic body to the nearest metallization or lead.. N is the maximum number of terminal positions.. Braze fillets shall be concave. 0. Dimensioning and tolerancing per NSI Y. -.. Controlling dimension: IH. E c L e/ LED FINISH BSE ETL b (b) SECTION - -D- -- S Q -C- e -Baaa C - B S c (c) D. IL-STD- CDIP-T (D-0, CONFIGUTION C) LED CEIC DUL-IN-LINE ETL SEL PCKGE IHES ILLIETES SYBOL IN X IN X NOTES b b b b c c D E e 0.00 BSC. BSC - e 0.00 BSC. BSC - e/ 0.00 BSC. BSC - L Q S S o 0 o 0 o 0 o - aaa bbb ccc N ev. 0 // Copyright Intersil mericas LLC 0-. ll ights eserved. ll trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO00 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. ccordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN ev.00 Page of

7 HS-0H, HS-0EH, HS-0BH, HS-0BEH Ceramic etal Seal Flatpack Packages (Flatpack) -Hb e H - B Q SETING ND BSE PLNE L c S E PIN NO. ID E E E E LED FINISH BSE ETL b (b) 0.0 H - B SECTION -. Index area: notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. lternately, a tab (dimension k) may be used to identify pin one.. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimensions b and c apply to lead base metal only. Dimension applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. N is the maximum number of terminal positions.. easure dimension S at all four corners.. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads.. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.00 inch (0.0mm) maximum when solder dip lead finish is applied.. Dimensioning and tolerancing per NSI Y Controlling dimension: IH. E (c) L S C S -D- -C- -B- D K. IL-STD- CDFP-F (F-, CONFIGUTION B) LED CEIC ETL SEL FLTPCK PCKGE IHES ILLIETES SYBOL IN X IN X NOTES b b c c D E E E E e 0.00 BSC. BSC - k L Q S N - ev. 0 // FN ev.00 Page of