DATASHEET CD4017BMS, CD4022BMS. Features. Applications. Pinouts. Functional Diagrams. CMOS Counter/Dividers. FN3297 Rev 0.00 Page 1 of 10.

Transcription

1 ATASHEET BMS, BMS MOS ounter/ividers BMS - ecade ounter with ecoded Outputs BMS - Octal ounter with 8 ecoded Outputs BMS and BMS are -stage and -stage Johnson counters having and 8 decoded outputs, respectively. Inputs include a LOK, a ESET, and a LOK INHIBIT signal. Schmitt trigger action in the LOK input circuit provides pulse shaping that allows unlimited clock input pulse rise and fall times. These counters are advanced one count at the positive clock signal transition if the LOK INHIBIT signal is low. ounter advancement via the clock line is inhibited when the LOK INHIBIT signal is high. A high ESET signal clears the counter to its zero count. Use of the Johnson counter configuration permits high speed operation, -input decode gating and spike-free decoded outputs. Anti-lock gating is provided, thus assuring proper counter sequence. The decoded output are normally low and go high only at their respective decoded time slot. Each decoded output remains high for one full clock cycle. A AY- signal completes one cycle every clock input cycles in the BMS or every 8 clock input cycles in the BMS and is used to ripple-clock the succeeding device in a multi-device counting chain. The BMS and BMS series types are supplied in these lead outline packages Braze Seal IP *HW HX Frit Seal IP *HF HE eramic Flatpack HW *B Only B Only Functional iagrams LOK LOK INHIBIT ESET V = VSS = 8 LOK LOK INHIBIT ESET V = VSS = 8 BMS 9 BMS 8 9 AY AY EOE EIMAL EOE Features FN9 ev. High Voltage Types (V ating) Fully Static Operation Medium-Speed Operation MHz (Typ) at V = V Standardized Symmetrical Output haracteristics % Tested for Quiescent urrent at V V, V and V Parametric atings Meets All equirements of JEE Tentative Standard Number A, Standard Specifications for escription of B Series MOS evices Applications ecade ounter/ecimal ecode isplay (BMS) Binary ounter/ecoder Frequency ivision ounter ontrol/timers ivide-by-n ounting For Further Application Information, See IAN- OS/MOS MSI ounter and egister esign and Applications Pinouts N = NO ONNETION N = NO ONNETION VSS N VSS 8 8 BMS TOP VIEW BMS TOP VIEW V ESET LOK LOK INHIBIT AY V ESET LOK LOK INHIBIT AY 9 N FN9 ev. Page of

2 BMS, BMS Absolute Maximum atings Supply Voltage ange, (V) V to +V (Voltage eferenced to VSS Terminals) Input Voltage ange, All Inputs V to V +.V Input urrent, Any One Input ma Operating Temperature ange o to + o Package Types, F, K, H Storage Temperature ange (TSTG) o to + o Lead Temperature (uring Soldering) o At istance / / Inch (.9mm.9mm) from case for s Maximum eliability Information Thermal esistance ja jc eramic IP and FIT Package o /W o /W Flatpack Package o /W o /W Maximum Package Power issipation (P) at + o For TA = - o to + o (Package Type, F, K).....mW For TA = + o to + o (Package Type, F, K).... erate Linearity at mw/ o to mw evice issipation per Output Transistor mW For TA = Full Package Temperature ange (All Package Types) Junction Temperature o TABLE. ELETIAL PEFOMANE HAATEISTIS GOUP A LIMITS PAAMETE SYMBOL ONITIONS (NOTE ) SUBGOUPS TEMPEATUE MIN MAX UNITS Supply urrent I V = V, VIN = V or GN + o - A + o - A V = 8V, VIN = V or GN - o - A Input Leakage urrent IIL VIN = V or GN V = + o - - na + o - - na V = 8V - o - - na Input Leakage urrent IIH VIN = V or GN V = + o - na + o - na V = 8V - o - na Output Voltage VOL V = V, No Load,, + o, + o, - o - mv Output Voltage VOH V = V, No Load (Note ),, + o, + o, - o.9 - V Output urrent (Sink) IOL V = V, V =.V + o. - ma Output urrent (Sink) IOL V = V, V =.V + o. - ma Output urrent (Sink) IOL V = V, V =.V + o. - ma Output urrent (Source) IOHA V = V, V =.V + o - -. ma Output urrent (Source) IOHB V = V, V =.V + o ma Output urrent (Source) IOH V = V, V = 9.V + o - -. ma Output urrent (Source) IOH V = V, V =.V + o - -. ma N Threshold Voltage VNTH V = V, ISS = - A + o V P Threshold Voltage VPTH VSS = V, I = A + o..8 V Functional F V =.8V, VIN = V or GN + o VOH > VOL < V V = V, VIN = V or GN + o V/ V/ V = 8V, VIN = V or GN 8A + o V = V, VIN = V or GN 8B - o Input Voltage Low (Note ) VIL V = V, VOH >.V, VOL <.V,, + o, + o, - o -. V Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) NOTES: VIH V = V, VOH >.V, VOL <.V,, + o, + o, - o. - V VIL VIH V = V, VOH >.V, VOL <.V V = V, VOH >.V, VOL <.V. All voltages referenced to device GN, % testing being implemented.. Go/No Go test with limits applied to inputs,, + o, + o, - o - V,, + o, + o, - o - V. For accuracy, voltage is measured differentially to V. Limit is.v max. FN9 ev. Page of

3 BMS, BMS TABLE. A ELETIAL PEFOMANE HAATEISTIS GOUP A LIMITS PAAMETE SYMBOL ONITIONS (Note, ) SUBGOUPS TEMPEATUE MIN MAX UNITS Propagation elay TPHL V = V, VIN = V or GN 9 + o - ns lock to ecode Out TPLH, + o, - o - 88 ns Propagation elay TPHL V = V, VIN = V or GN 9 + o - ns lock to arry Out TPLH, + o, - o - 8 ns Propagation elay TPHL V = V, VIN = V or GN 9 + o - ns eset to Out TPLH, + o, - o - ns Transition Time TTHL V = V, VIN = V or GN 9 + o - ns TTLH, + o, - o - ns Maximum lock Input Frequency FL V = V, VIN = V or GN 9 + o. - MHz, + o, - o.8 - MHz NOTES:. L = pf, L = K, Input T, TF < ns.. - o and + o limits guaranteed, % testing being implemented. TABLE. ELETIAL PEFOMANE HAATEISTIS LIMITS PAAMETE SYMBOL ONITIONS NOTES TEMPEATUE MIN MAX UNITS Supply urrent I V = V, VIN = V or GN, - o, + o - A + o - A V = V, VIN = V or GN, - o, + o - A + o - A V = V, VIN = V or GN, - o, + o - A + o - A Output Voltage VOL V = V, No Load, + o, + o, - - mv o Output Voltage VOL V = V, No Load, + o, + o, - - mv o Output Voltage VOH V = V, No Load, + o, + o, V o Output Voltage VOH V = V, No Load, + o, + o, V o Output urrent (Sink) IOL V = V, V =.V, + o. - ma - o. - ma Output urrent (Sink) IOL V = V, V =.V, + o.9 - ma - o. - ma Output urrent (Sink) IOL V = V, V =.V, + o. - ma - o. - ma Output urrent (Source) IOHA V = V, V =.V, + o - -. ma - o - -. ma Output urrent (Source) IOHB V = V, V =.V, + o - -. ma - o - -. ma Output urrent (Source) IOH V = V, V = 9.V, + o ma - o - -. ma Output urrent (Source) IOH V =V, V =.V, + o - -. ma - o - -. ma Input Voltage Low VIL V = V, VOH > 9V, VOL < V, + o, + o, - - V o Input Voltage High VIH V = V, VOH > 9V, VOL < V, + o, + o, - - V o FN9 ev. Page of

4 BMS, BMS Propagation elay lock to ecode Out Propagation elay lock to arry Out Propagation elay eset to out Transition Time Maximum lock Input Frequency Minimum Setup Time lock Inhibit to lock Setup Minimum eset Pulse Width TABLE. ELETIAL PEFOMANE HAATEISTIS (ontinued) PAAMETE SYMBOL ONITIONS NOTES TEMPEATUE TPHL TPLH TPHL TPLH TPHL TPLH TTHL TTLH V = V,, + o - ns V = V,, + o - ns V = V,, + o - ns V = V,, + o - ns V = V,, + o - ns V = V,, + o - ns V = V,, + o - ns V = V,, + o - 8 ns FL V = V,, + o. - MHz V = V,, + o. - MHz TS V = V,, + o - ns V = V,, + o - ns V = V,, + o - ns TW V = V,, + o - ns V = V,, + o - ns V = V,, + o - ns Minimum lock Pulse TW V = V,, + o - ns Width V = V,, + o - 9 ns V = V,, + o - ns Input apacitance IN Any Input, + o -. pf NOTES:. All voltages referenced to device GN.. The parameters listed on Table are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.. L = pf, L = K, Input T, TF < ns. MIN LIMITS MAX UNITS TABLE. POST IAIATION ELETIAL PEFOMANE HAATEISTIS LIMITS PAAMETE SYMBOL ONITIONS NOTES TEMPEATUE MIN MAX UNITS Supply urrent I V = V, VIN = V or GN, + o - A N Threshold Voltage VTN V = V, ISS = - A, + o V N Threshold Voltage VTN V = V, ISS = - A, + o - V elta P Threshold Voltage VTP VSS = V, I = A, + o..8 V P Threshold Voltage VTP VSS = V, I = A, + o - V elta Functional F V = 8V, VIN = V or GN V = V, VIN = V or GN + o VOH > V/ Propagation elay Time TPHL TPLH NOTES:. All voltages referenced to device GN.. L = pf, L = K, Input T, TF < ns. VOL < V/ V = V,,, + o -. x + o Limit. See Table for + o limit.. ead and ecord TABLE. BUN-IN AN LIFE TEST ELTA PAAMETES + O PAAMETE SYMBOL ELTA LIMIT Supply urrent - MSI- I. A Output urrent (Sink) IOL % x Pre-Test eading Output urrent (Source) IOHA % x Pre-Test eading V ns FN9 ev. Page of

5 BMS, BMS TABLE. APPLIABLE SUBGOUPS ONFOMANE GOUP MIL-ST-88 METHO GOUP A SUBGOUPS EA AN EO Initial Test (Pre Burn-In) %,, 9 I, IOL, IOHA Interim Test (Post Burn-In) %,, 9 I, IOL, IOHA Interim Test (Post Burn-In) %,, 9 I, IOL, IOHA PA (Note ) %,, 9, eltas Interim Test (Post Burn-In) %,, 9 I, IOL, IOHA PA (Note ) %,, 9, eltas Final Test %,, 8A, 8B,, Group A Sample,,,, 8A, 8B, 9,, Group B Subgroup B- Sample,,,, 8A, 8B, 9,,, eltas Subgroups,,, 9,, Subgroup B- Sample,, 9 Group Sample,,, 8A, 8B, 9 Subgroups, NOTE:. % Parameteric, % Functional; umulative for Static and. TABLE. TOTAL OSE IAIATION MIL-ST-88 TEST EA AN EO ONFOMANE GOUPS METHO PE-IA POST-IA PE-IA POST-IA Group E Subgroup,, 9 Table, 9 Table TABLE 8. BUN-IN AN IAIATION TEST ONNETIONS OSILLATO FUNTION OPEN GOUN V 9V -.V khz khz PAT NUMBE BMS AN B Static Burn-In -, 9-8,,, Note Static Burn-In -, 9-8,,, Note ynamic Burn- - 8,, -, In Note Irradiation -, Note NOTE:. Each pin except V and GN will have a series resistor of K %, V = 8V.V. Each pin except V and GN will have a series resistor of K %; Group E, Subgroup, sample size is dice/wafer, failures, V = V.V FN9 ev. Page of

6 BMS, BMS Logic iagram AY Q Q Q Q Q Q Q Q Q Q *ESET *LOK V *LOK INHIBIT VSS * All Inputs Protected by MOS Protection Network FIGUE. BMS opyright Intersil Americas LL 999. All ights eserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see FN9 ev. Page of

7 BMS, BMS Logic iagram (ontinued) AY Q Q Q Q Q Q Q Q *ESET V *LOK *LOK INHIBIT * All Inputs Protected by MOS Protection Network VSS Timing iagram FIGUE. BMS LOK LOK ESET LOK INHIBIT ESET LOK INHIBIT 8 9 AY 8 9 AY FIGUE. BMS FIGUE. BMS FN9 ev. Page of

8 BMS, BMS Typical Performance haracteristics PUT LOW (SINK) UENT (IOL) (ma) AMBIENT TEMPEATUE (T A ) = + o GATE-TO-SOUE VOLTAGE (VGS) = V V V PUT LOW (SINK) UENT (IOL) (ma)... AMBIENT TEMPEATUE (T A ) = + o V GATE-TO-SOUE VOLTAGE (VGS) = -V V AIN-TO-SOUE VOLTAGE (VS) (V) AIN-TO-SOUE VOLTAGE (VS) (V) FIGUE. TYPIAL PUT LOW (SINK) UENT HAATEISTIS FIGUE. MINIMUM PUT LOW (SINK) UENT HAATEISTIS AIN-TO-SOUE VOLTAGE (VS) (V) AMBIENT TEMPEATUE (T A ) = + o GATE-TO-SOUE VOLTAGE (VGS) = -V -V - -V PUT HIGH (SOUE) UENT (IOH) (ma) AIN-TO-SOUE VOLTAGE (VS) (V) AMBIENT TEMPEATUE (T A ) = + o -V - -V - GATE-TO-SOUE VOLTAGE (VGS) = -V PUT HIGH (SOUE) UENT (IOH) (ma) FIGUE. TYPIAL PUT HIGH (SOUE) UENT HAATEISTIS FIGUE 8. MINIMUM PUT HIGH (SOUE) UENT HAATEISTIS TANSITION TIME (tthl, ttlh) (ns) AMBIENT TEMPEATUE (T A ) = + o SUPPLY VOLTAGE (V) = V V V 8 LOA APAITANE (L) (pf) POPAGATION ELAY TIME (tplh, tphl) (ns) AMBIENT TEMPEATUE (T A ) = + o SUPPLY VOLTAGE (V) = V V V 8 9 LOA APAITANE (L) (pf) FIGUE 9. TYPIAL TANSITION TIME AS A FUNTION OF LOA APAITANE FIGUE. TYPIAL POPAGATION ELAY TIME AS A FUNTION OF LOA APAITANE (LOK TO EOE PUT) FN9 ev. Page 8 of

9 BMS, BMS Typical Performance haracteristics (ontinued) POPAGATION ELAY TIME (tplh, tphl) (ns) AMBIENT TEMPEATUE (T A ) = + o SUPPLY VOLTAGE (V) = V V V 8 9 LOA APAITANE (L) (pf) POWE ISSIPATION (P) ( W) LOA APAITANE L = pf L = pf SUPPLY VOLTAGE (V) = V V AMBIENT TEMPEATUE (T A ) = + o INPUT tr = tf = ns V V LOK INPUT FEQUENY (fl) (khz) FIGUE. TYPIAL POPAGATION ELAY TIME AS A FUNTION OF LOA APAITANE (LOK TO AY ) FIGUE. TYPIAL YNAMI POWE ISSIPATION AS A FUNTION OF LOK INPUT FEQUENY LOK LOK INHIBIT ESET EOE -9 PUT TS TPLH TPHL TPHL LOK LOK INHIBIT BMS O BMS... N N EOE PUTS O EOE PUTS FO N f = LOK N ALTENATE FO N = TO f = LOK N EOE O AY PUT TPHL TPLH elays Measured Between % levels on All Waveforms FIGUE. POPAGATION ELAY, SETUP, AN ESET EMOVAL TIME WAVEFOMS FIGUE. IVIE BY N OUNTE (N ) WITH N EOE PUTS E BMS Q Q... Q8 Q9 E BMS Q Q... Q8 Q9 E BMS Q Q... Q8 Q9 9 EOE PUTS 8 EOE PUTS 8 EOE PUTS LOK FIST STAGE INTEMEIATE STAGE FIGUE. ASAING THE BMS LAST STAGE When the N th decoded output is reached (N th clock pulse) the S- flip-flop (constructed from two NO gates of the B) generates a reset pulse which clears the BMS or BMS to its zero count. At this time, if the N th decoded output is greater than or equal to in the BMS or in the BMS, the line goes high to clock the next BMS or BMS counter section. The decoded output also goes high at this time. oincidence of the clock low and decoded output low resets the S- flip-flop to enable the BMS or BMS. If the N th decoded output is less than (BMS) or (BMS), the line will not go high and, therefore, cannot be used. In this case decoded output may be used to perform the clocking function for the next counter. FN9 ev. Page 9 of

10 BMS, BMS hip imensions and Pad Layouts BMSH imensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( - inch) BMSH METALLIZATION: Thickness: kå kå, AL. PASSIVATION:.kÅ -.kå, Silane BON PAS:. inches X. inches MIN IE THIKNESS:.98 inches -.8 FN9 ev. Page of