MARKING DIAGRAMS DIP PIN ASSIGNMENT ORDERING INFORMATION TRUTH TABLE CDIP 16 L SUFFIX CASE 620 MC10165L AWLYYWW

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Susan McGee
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The M0 is a device designed to encode eight inputs to a binary coded output. The output code is that of the highest order input. Any input of lower priority is ignored.

1 The M0 is a device designed to encode eight inputs to a binary coded output. The output code is that of the highest order input. Any input of lower priority is ignored. Each output incorporates a latch allowing synchronous operation. When the clock is low the outputs follow the inputs and latch when the clock goes high. This device is very useful for a variety of applications in checking system status in control processors, peripheral controllers, and testing systems. The input is active when high, (e.g., the three binary outputs are low when input is high). The Q output is high when any input is high. This allows direct extension into another priority encoder when more than eight inputs are necessary. The M0 can also be used to develop binary codes from random logic inputs, for addressing ROMs, RAMs, or for multiplexing data. PD = mw typ/pkg (No Load) tpd =. ns typ (Data to Output) tr, tf = ns typ (0% 0%) DIP PIN ASSIGNMENT DIP L SUFFIX ASE 0 PDIP P SUFFIX ASE MARKING DIAGRAMS M0L M0P V V PL 0 FN SUFFIX ASE 0 Q LOK D D D A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week D VEE Pin assignment is for Dual in Line Package. For PL pin assignment, see the Pin onversion Tables on page. TRUTH TABLE DATA INPUTS OUTPUTS D D D D D D Q H X X X X X X X H L L L L H X X X X X X H L L H L L H X X X X X H L H L L L L H X X X X H L H H L L L L H X X X H H L L L L L L L H X X H H L H L L L L L L H X H H H L L L L L L L L H H H H H L L L L L L L L L L L L 0 9 D D ORDERING INFORMATION Device Package Shipping M0L DIP Units / Rail M0P PDIP Units / Rail M0FN PL 0 Units / Rail Semiconductor omponents Industries, LL, 000 March, 000 Rev. Publication Order Number: M0/D

2 M0 LOGI DIAGRAM V = PIN V = PIN VEE = PIN D D D 0 D D D 9 Q 9

3 M0 ELETRIAL HARATERISTIS haracteristic Symbol Test Limits Pin Under Test Min Max Min Typ Max Min Max Unit Power Supply Drain urrent IE 0 madc Input urrent IinH IinL Output Voltage Logic VOH Output Voltage Logic 0 VOL Threshold Voltage Logic VOHA Threshold Voltage Logic 0 VOLA Switching Times (0Ω Load) Propagation DelayData Input Setup Time Hold Time lock Input t++ t t++ t++ t++ t + t t + t tsetuph tsetupl tholdh tholdl (.) (.) (.) (.) Rise Time (0 to 0%) t Fall Time (0 to 0%) t The same limit applies for all D type input pins. To test input currents for other D inputs, individually apply proper voltage to pin under test.. Output latched to low state prior to test.. Output latched to high state prior to test. * To preserve reliable performance, the M0P (plastic packaged device only) is to be operated in ambient temperatures above 0 only when 00 lfpm blown air or equivalent heat sinking is provided µadc µadc ns 0

4 M0 ELETRIAL HARATERISTIS (continued) TEST VOLTAGE VALUES (Volts) Test Temperature VIHmax VILmin VIHAmin VILAmax VEE Symbol Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW Under Test VIHmax VILmin VIHAmin VILAmax VEE Power Supply Drain urrent IE Input urrent IinH IinL Output Voltage Logic VOH Output Voltage Logic 0 VOL Threshold Voltage Logic VOHA Threshold Voltage Logic 0 VOLA (.) Switching Times (0Ω Load) +.V +0.V Pulse In Pulse Out. V + Propagation Delay Data Input t++ t t++ t++ t++ lock Input t + t t + t Setup Time tsetuph tsetupl Hold Time tholdh tholdl (.) (.) (.) (.) Rise Time (0 to 0%) t+ Fall Time (0 to 0%) t (.) (V) Gnd. The same limit applies for all D type input pins. To test input currents for other D inputs, individually apply proper voltage to pin under test.. Output latched to low state prior to test.. Output latched to high state prior to test. * To preserve reliable performance, the M0P (plastic packaged device only) is to be operated in ambient temperatures above 0 only when 00 lfpm blown air or equivalent heat sinking is provided. Each MEL 0,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 00 linear fpm is maintained. Outputs are terminated through a 0 ohm resistor to volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.,,,,

5 M0 APPLIATION INFORMATION A typical application of the M0 is the decoding of system status on a priority basis. A line priority encoder is shown in the figure below. System status lines are connected to this encoder such that, when a given condition exists, the respective input will be at a logic high level. This scheme will select the one of different system conditions, as represented at the encoder inputs, which has priority in determining the next system operation to be performed. The binary code showing the address of the highest priority input present will appear at the encoder outputs to control other system logic functions. LINE PRIORITY ENODER LSB Z Z Z M0 M0 M0 System lock Highest Priority Input / M0 M0 M0 Q Q X X A B X X A B X X A B MSB Six bit output word yielding number of highest priority channel present at input M0 Q M0 Q M0 Q M0 Q M0 Q Lowest Priority Input M0 Q

MARKING DIAGRAMS DIP PIN ASSIGNMENT ORDERING INFORMATION FUNCTION TABLE CDIP 16 L SUFFIX CASE 620 MC10136L AWLYYWW

MARKING DIAGRAMS DIP PIN ASSIGNMENT ORDERING INFORMATION FUNCTION TABLE CDIP 16 L SUFFIX CASE 620 MC10136L AWLYYWW The MC16 is a high speed synchronous counter that can count up, count down, preset, or stop count at frequencies exceeding 1 MHz. The flexibility of this device allows the designer to use one basic counter