CD4510BMS, CD4516BMS. CMOS Presettable Up/Down Counters. Features. Applications. Functional Diagram. Pinout. Data Sheet December 1992 File Number 3338

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1 Data Sheet December File Number MOS resettable Up/Down ounters DBMS resettable BD Up/Down ounter and the DBMS resettable Binary Up/Down counter consist of four synchronously clocked D-type flip-flops (with a gating structure to provide -type flip-flop capability) connected as counters. hese counters can be cleared by a high level on the line, and can be preset to any binary number present on the jam inputs by a high level on the ENABLE line. he DBMS will count out of non-bd counter states in a maximum of two clock pulses in the up mode, and a maximum of four clock pulses in the down mode. If the AY IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the of a less significant stage to the AY IN of a more significant stage. he DBMS and DBMS can be cascaded in the ripple mode by connecting the to the clock of the next stage. If the U/DOWN input changes during a terminal count, the must be gated with the clock, and the U/DOWN input must change while the clock is high. his method provides a clean clock signal to the subsequent counting stage. (See Figures,.) hese devices are similar to types M and M. he DBMS and DBMS are supplied in these -lead outline packages: Braze Seal DI *HW H Frit Seal DI *FBF HF eramic Flatpack HW *DB Only DB Only Features High Voltage ypes (V ating) DBMS - BD ype DBMS - Binary ype Medium Speed Operation - fl = MHz yp. at V Synchronous Internal arry ropagation eset and reset apability % ested for uiescent urrent at V V, V and V arametric atings Standardized Symmetrical Output haracteristics Maximum Input urrent of µa at V Over Full ackage emperature ange; na at V and + o Noise Margin (Over Full ackage/emperature ange) - V at VDD = V - V at VDD = V -.V at VDD = V Meets All equirements of JEDE entative Standard No. B, Standard Specifications for Description of B Series MOS Devices Applications Up/Down Difference ounting Multistage Synchronous ounting Multistage ipple ounting Synchronous Frequency Dividers inout Functional Diagram O VIEW ENABLE ENABLE VDD AY IN VSS U/DOWN U/DOWN AY IN VDD = VSS = AUION: hese devices are sensitive to electrostatic discharge; follow proper I Handling rocedures. --INESIL or -- opyright Intersil orporation

2 Absolute Maximum atings D Supply Voltage ange, (VDD) V to +V (Voltage eferenced to VSS erminals) Input Voltage ange, All Inputs V to VDD +.V D Input urrent, Any One Input ±mA Operating emperature ange o to + o ackage ypes D, F, K, H Storage emperature ange (SG) o to + o Lead emperature (During Soldering) o At Distance / ± / Inch (.mm ±.mm) from case for s Maximum eliability Information hermal esistance θ ja θ jc eramic DI and FI ackage.... o /W o /W Flatpack ackage o /W o /W Maximum ackage ower Dissipation (D) at + o For A = - o to + o (ackage ype D, F, K)......mW For A = + o to + o (ackage ype D, F, K)..... Derate Linearity at mw/ o to mw Device Dissipation per Output ransistor mw For A = Full ackage emperature ange (All ackage ypes) Junction emperature o ABLE. D ELEIAL EFOMANE HAAEISIS GOU A LIMIS AAMEE SYMBOL ONDIIONS (NOE ) SUBGOUS EMEAUE MIN MAX UNIS Supply urrent IDD VDD = V, VIN = VDD or GND + o - µa + o - µa VDD = V, VIN = VDD or GND - o - µa Input Leakage urrent IIL VIN = VDD or GND VDD = + o - - na + o - - na VDD = V - o - - na Input Leakage urrent IIH VIN = VDD or GND VDD = + o - na + o - na VDD = V - o - na Output Voltage VOL VDD = V, No Load,, + o, + o, - o - mv Output Voltage VOH VDD = V, No Load (Note ),, + o, + o, - o. - V Output urrent (Sink) IOL VDD = V, VOU =.V + o. - ma Output urrent (Sink) IOL VDD = V, VOU =.V + o. - ma Output urrent (Sink) IOL VDD = V, VOU =.V + o. - ma Output urrent (Source) IOHA VDD = V, VOU =.V + o - -. ma Output urrent (Source) IOHB VDD = V, VOU =.V + o - -. ma Output urrent (Source) IOH VDD = V, VOU =.V + o - -. ma Output urrent (Source) IOH VDD = V, VOU =.V + o - -. ma N hreshold Voltage VNH VDD = V, ISS = -µa + o V hreshold Voltage VH VSS = V, IDD = µa + o.. V Functional F VDD =.V, VIN = VDD or GND + o VOH > VOL < V VDD = V, VIN = VDD or GND + o VDD/ VDD/ VDD = V, VIN = VDD or GND A + o VDD = V, VIN = VDD or GND B - o Input Voltage Low (Note ) VIL VDD = V, VOH >.V, VOL <.V,, + o, + o, - o -. V Input Voltage High (Note ) Input Voltage Low (Note ) Input Voltage High (Note ) NOES: VIH VDD = V, VOH >.V, VOL <.V,, + o, + o, - o. - V VIL VIH VDD = V, VOH >.V, VOL <.V VDD = V, VOH >.V, VOL <.V. All voltages referenced to device GND, % testing being implemented.. Go/No Go test with limits applied to inputs.,, + o, + o, - o - V,, + o, + o, - o - V. For accuracy, voltage is measured differentially to VDD. Limit is.v max.

3 ABLE. A ELEIAL EFOMANE HAAEISIS AAMEE SYMBOL ONDIIONS (NOE, ) lock to Output reset or eset to lock to arry Out arry In to arry Out reset or eset to arry Out ransition ime HL LH HL LH HL LH HL LH HL LH GOU A SUBGOUS EMEAUE MIN LIMIS MAX UNIS VDD = V, VIN = VDD or GND + o - ns, + o, - o - ns VDD = V, VIN = VDD or GND + o - ns, + o, - o - ns VDD = V, VIN = VDD or GND + o - ns, + o, - o - ns VDD = V, VIN = VDD or GND + o - ns, + o, - o - ns VDD = V, VIN = VDD or GND (Note ) + o - ns, + o, - o - ns HL VDD = V, VIN = VDD or GND + o - ns LH, + o, - o - ns Maximum lock Input Frequency FL VDD = V, VIN = VDD or GND + o - MHz, + o, - o. - MHz NOES:. L = pf, L = K, Input, F < ns.. - o and + o limits guaranteed, % testing being implemented.. eset to arry Out (LH) only. ABLE. ELEIAL EFOMANE HAAEISIS LIMIS AAMEE SYMBOL ONDIIONS NOES EMEAUE MIN MAX UNIS Supply urrent IDD VDD = V, VIN = VDD or GND, - o, + o - µa + o - µa VDD = V, VIN = VDD or GND, - o, + o - µa + o - µa VDD = V, VIN = VDD or GND, - o, + o - µa + o - µa Output Voltage VOL VDD = V, No Load, + o, + o, - - mv o Output Voltage VOL VDD = V, No Load, + o, + o, - o Output Voltage VOH VDD = V, No Load, + o, + o, - o Output Voltage VOH VDD = V, No Load, + o, + o, - o - mv. - V. - V Output urrent (Sink) IOL VDD = V, VOU =.V, + o. - ma - o. - ma Output urrent (Sink) IOL VDD = V, VOU =.V, + o. - ma - o. - ma Output urrent (Sink) IOL VDD = V, VOU =.V, + o. - ma - o. - ma Output urrent (Source) IOHA VDD = V, VOU =.V, + o - -. ma - o - -. ma

4 Output urrent (Source) IOHB VDD = V, VOU =.V, + o - -. ma - o - -. ma Output urrent (Source) IOH VDD = V, VOU =.V, + o - -. ma - o - -. ma Output urrent (Source) IOH VDD =V, VOU =.V, + o - -. ma - o - -. ma Input Voltage Low VIL VDD = V, VOH > V, VOL < V, + o, + o, - o - V Input Voltage High VIH VDD = V, VOH > V, VOL < V, + o, + o, - o lock to Output reset or eset to lock to arry Out arry In to arry Out reset or eset to arry Out ransition ime Maximum lock Input Frequency Minimum Hold ime reset Enable to JN Minimum Data Setup ime reset Enable to JN Minimum Data Hold ime lock to arry In ABLE. ELEIAL EFOMANE HAAEISIS (ontinued) AAMEE SYMBOL ONDIIONS NOES EMEAUE HL LH HL LH HL LH HL LH HL LH LH HL LIMIS + - V VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,,, + o - ns VDD = V,,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns FL VDD = V, + o - MHz VDD = V, + o. - MHz H VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns S VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns H VDD = V,, + o - ns VDD = V,, + o - ns VDD = V,, + o - ns Minimum lock Hold ime H VDD = V,, + o - ns lock to Up/Down VDD = V,, + o - ns VDD = V,, + o - ns Input apacitance IN Any Input, + o -. pf NOES:. All voltages referenced to device GND.. he parameters listed on able are controlled via design or process and are not directly tested. hese parameters are characterized on initial design release and upon design changes which would affect these characteristics.. L = pf, L = K, Input, F < ns.. eset to arry Out (LH) only. MIN MAX UNIS

5 ABLE. OS IADIAION ELEIAL EFOMANE HAAEISIS LIMIS AAMEE SYMBOL ONDIIONS NOES EMEAUE MIN MAX UNIS Supply urrent IDD VDD = V, VIN = VDD or GND, + o - µa N hreshold Voltage VNH VDD = V, ISS = -µa, + o V N hreshold Voltage VN VDD = V, ISS = -µa, + o - ± V Delta hreshold Voltage V VSS = V, IDD = µa, + o.. V hreshold Voltage V VSS = V, IDD = µa, + o - ± V Delta Functional F VDD = V, VIN = VDD or GND VDD = V, VIN = VDD or GND + o VOH > VDD/ ime HL LH NOES:. All voltages referenced to device GND.. L = pf, L = K, Input, F < ns. VOL < VDD/ VDD = V,,, + o -. x + o Limit. See able for + o limit.. ead and ecord V ns ABLE. BUN-IN AND LIFE ES DELA AAMEES + o AAMEE SYMBOL DELA LIMI Supply urrent - MSI- IDD ±.µa Output urrent (Sink) IOL ± % x re-est eading Output urrent (Source) IOHA ± % x re-est eading ABLE. ALIABLE SUBGOUS ONFOMANE GOU MIL-SD- MEHOD GOU A SUBGOUS EAD AND EOD Initial est (re Burn-In) %,, IDD, IOL, IOHA Interim est (ost Burn-In) %,, IDD, IOL, IOHA Interim est (ost Burn-In) %,, IDD, IOL, IOHA DA (Note ) %,,, Deltas Interim est (ost Burn-In) %,, IDD, IOL, IOHA DA (Note ) %,,, Deltas Final est %,, A, B,, Group A Sample,,,, A, B,,, Group B Subgroup B- Sample,,,, A, B,,,, Deltas Subgroups,,,,, Subgroup B- Sample,, Group D Sample,,, A, B, Subgroups, NOE:. % arameteric, % Functional; umulative for Static and. ABLE. OAL DOSE IADIAION MIL-SD- ES EAD AND EOD ONFOMANE GOUS MEHOD E-IAD OS-IAD E-IAD OS-IAD Group E Subgroup,, able, able

6 ABLE. BUN-IN AND IADIAION ES ONNEIONS FUNION OEN GOUND VDD V ± -.V DBMS Static Burn-In (Note ) Static Burn-In (Note ) Dynamic Burn- In (Note ) Irradiation (Note ) NOES:,,,,, -, -,,,,,,,, -,,,,,, OSILLAO khz khz -,,,,,,,,,,,,,,,, -,,,,,,. Each pin except VDD and GND will have a series resistor of K ± %, VDD = V ±.V. Each pin except VDD and GND will have a series resistor of K ± %; Group E, Subgroup, sample size is dice/wafer, failures, VDD = V ±.V Logic Diagrams * * * * * * ENABLE * E E E E AY IN* U/DOWN* U/D U/D VDD U/D U/D U/D U/D U/D U/D U/D VSS * ALL INUS AE OEED BY MOS OEION NEWOK FIGUE. DBMS

7 Logic Diagrams (ontinued) * * * * * * ENABLE * E E E E AY IN* U/DOWN* U/D U/D VDD U/D U/D U/D U/D U/D U/D VSS * ALL INUS AE OEED BY MOS OEION NEWOK FIGUE. DBMS UH ABLE L I U/D E AION X X NO OUN OUN U OUN DOWN X X X X X X X X = DON AE

8 ypical erformance haracteristics OUU LOW (SINK) UEN (IOL) (ma) AMBIEN EMEAUE ( A ) = + o GAE-O-SOUE VOLAGE (VGS) = V V V OUU LOW (SINK) UEN (IOL) (ma) AMBIEN EMEAUE ( A ) = + o GAE-O-SOUE VOLAGE (VGS) = V V V DAIN-O-SOUE VOLAGE (VDS) (V) DAIN-O-SOUE VOLAGE (VDS) (V) FIGUE. YIAL OUU LOW (SINK) UEN HAAEISIS FIGUE. MINIMUM OUU LOW (SINK) UEN HAAEISIS DAIN-O-SOUE VOLAGE (VDS) (V) AMBIEN EMEAUE ( A ) = + o GAE-O-SOUE VOLAGE (VGS) = -V -V -V OUU HIGH (SOUE) UEN (IOH) (ma) DAIN-O-SOUE VOLAGE (VDS) (V) AMBIEN EMEAUE ( A ) = + o GAE-O-SOUE VOLAGE (VGS) = -V -V -V OUU HIGH (SOUE) UEN (IOH) (ma) FIGUE. YIAL OUU HIGH (SOUE) UEN HAAEISIS FIGUE. MINIMUM OUU HIGH (SOUE) UEN HAAEISIS ANSIION IME (tlh) (ns) AMBIEN EMEAUE ( A ) = + o SULY VOLAGE (VDD) = V V V LOAD AAIANE (L) (pf) OAGAION DELAY IME (tlh, thl) (ns) AMBIEN EMEAUE ( A ) = + o SULY VOLAGE (VDD) = V V V LOAD AAIANE (L) (pf) FIGUE. YIAL ANSIION IME vs LOAD AAIANE FIGUE. YIAL OAGAION DELAY IME vs LOAD AAIANE FO -O- OUUS

9 ypical erformance haracteristics (ontinued) MAXIMUM INU FEUENY (fl MAX) (MHz) AMBIEN EMEAUE ( A ) = + o LOAD AAIANE (L) = pf SULY VOLAGE (VDD) OWE DISSIAION E GAE (D) (µw) AMBIEN EMEAUE ( A ) = + o tr, tf = ns SULY VOLS (VDD) = V V V V L = pf L = pf INU FEUENY (fl) (khz) FIGUE. YIAL MAXIMUM INU FEUENY vs SULY VOLAGE FIGUE. YIAL DYNAMI OWE DISSIAION vs FEUENY est ircuit and Waveform µf ID µf L L L L L ULSE GENEAO ns % % VAIABLE WIDH ns VDD % VSS FIGUE. OWE DISSIAION ES IUI AND INU WAVEFOM Acquisition System ANALOG DAA INUS HANNEL MULILEXE D SELE INUS AMLI- FIE SAMLE AND HOLD ONVESION LOGI SA END BI A/D ONVEE AALLEL DAA OUUS INUS DBMS NOE: his acquisition system can be operated in the random access mode by jamming in the channel number at the present inputs, or in the sequential mode by clocking the DBMS. ENABLE FIGUE. YIAL HANNEL, BI DAA AUISIION SYSEM

10 iming Diagrams AY IN U/DOWN E OUN FIGUE. DBMS AY IN U/DOWN E VDD VSS OUN FIGUE. DBMS

11 U/DOWN ENABLE AALLEL ING U/D E J J J J I D/BMS O U/D E J J J J U/D E J J J J I D/BMS O I D/BMS O * L L L * lines at the nd, rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different D/BMS I S. hese negative going glitches do not affect proper DBMS operation. However, if the signals are used to trigger other edgesensitive logic devices, such as FF S or counters, the signals should be gated with the clock signal using a -input O gate such as DBMS. U/DOWN ENABLE ILE ING U/D E J J J J U/D E J J J J U/D E J J J J I D/BMS O I D/BMS O I D/BMS O L L L / DB ipple locking Mode: he up/down control can be changed at any count. he only restriction on changing the up/down control is that the clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the O gates are not required between stages, and O is connected directly to the L input of the next stage with I grounded. FIGUE. ASADING OUNE AKAGES All Intersil semiconductor products are manufactured, assembled and tested under ISO quality systems certification. Intersil semiconductor products are sold by description only. Intersil orporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil orporation and its products, see web site Sales Office Headquarters NOH AMEIA Intersil orporation. O. Box, Mail Stop - Melbourne, FL EL: () - FAX: () - EUOE Intersil SA Mercure enter, ue de la Fusee Brussels, Belgium EL: ().. FAX: ()... ASIA Intersil (aiwan) Ltd. F-, No. Fu Hsing North oad aipei, aiwan epublic of hina EL: () FAX: ()

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