DATASHEET CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS. Features. Pinouts. Description. CMOS NOR Gate. FN3289 Rev 0.00 Page 1 of 9.

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1 TST 000MS, 00MS, 00MS, 0MS MOS NOR ate N Rev 0.00 November eatures Piouts igh-voltage Tyes (0V Ratig) Proagatio elay Time = 0s (ty.) at L = 0, = V N 000MS TOP VIW uffered Iuts ad Oututs N Stadard Symmetrical Outut haracteristics 0% Tested for Maximum Quiescet urret at 0V V, V ad V Parametric Ratigs Maximum Iut urret of at V Over ull Package-Temerature Rage; 0 at V ad + o Noise Margi (Over ull Package Temerature Rage): - V at = V - V at = V -.V at = V = MS TOP VIW K = + + L = N = NO ONNTION Meets ll Requiremets of J Tetative Stadards No., Stadard Secificatios for escritio of Series MOS evice s J = + K = + M = + escritio L = + 000MS - ual Plus Iverter 00MS 00MS 0MS - Quad Iut - ual Iut - Trile Iut 00MS TOP VIW N = NO ONNTION 000MS, 00MS, 00MS, ad 0MS NOR gates rovide the system desiger with direct imlemetatio of the NOR fuctio ad sulemet the existig family of MOS gates. ll iuts ad oututs are buffered. J = K = The 000MS, 00MS, 00MS ad the 0MS is sulied i these lead outlie ackages: N N raze Seal IP X Q Q Q N = NO ONNTION rit Seal IP 0MS TOP VIW eramic latack W W W W I L = + + I K = + + J = + + N = NO ONNTION N Rev 0.00 Page of November

2 000MS, 00MS, 00MS, 0MS uctioal iagrams N K = + + J = + M = + N J K = + K M K L = + + L L = L = + 000MS 00MS J J = K L = + + I I L N K K = + + J K = N J = MS 0MS N Rev 0.00 Page of November

3 000MS, 00MS, 00MS, 0MS bsolute Maximum Ratigs Suly Voltage Rage, () V to +0V (Voltage Refereced to Termials) Iut Voltage Rage, ll Iuts V to +0.V Iut urret, y Oe Iut m Oeratig Temerature Rage o to + o Package Tyes,, K, Storage Temerature Rage (TST) o to +0 o Lead Temerature (urig Solderig) o t istace / / Ich (.mm 0.mm) from case for s Maximum Reliability Iformatio Thermal Resistace ja jc eramic IP ad RIT Package o /W 0 o /W latack Package o /W 0 o /W Maximum Package Power issiatio (P) at + o or T = - o to +0 o (Package Tye,, K) mW or T = +0 o to + o (Package Tye,, K)..... erate Liearity at mw/ o to 00mW evice issiatio er Outut Trasistor mW or T = ull Package Temerature Rage (ll Package Tyes) Juctio Temerature o TL. LTRIL PRORMN RTRISTIS ROUP PRMTR SYMOL ONITIONS (NOT ) SUROUPS TMPRTUR MIN MX UNITS Suly urret I = 0V, VIN = or N + o o - 0 = V, VIN = or N - o - 0. Iut Leakage IIL VIN = or N = 0 + o o = V - o -0 - Iut Leakage II VIN = or N = 0 + o o - 00 = V - o - 0 Outut Voltage VOL = V, No Load,, + o, + o, - o - 0 mv Outut Voltage VO = V, No Load (Note ),, + o, + o, - o. - V Outut urret (Sik) IOL = V, VOUT = 0.V + o 0. - m Outut urret (Sik) IOL = V, VOUT = 0.V + o. - m Outut urret (Sik) IOL = V, VOUT =.V + o. - m Outut urret (Source) IO = V, VOUT =.V + o m Outut urret (Source) IO = V, VOUT =.V + o - -. m Outut urret (Source) IO = V, VOUT =.V + o - -. m Outut urret (Source) IO = V, VOUT =.V + o - -. m N Threshold Voltage VNT = V, ISS = - + o V P Threshold Voltage VPT = 0V, I = + o 0.. V uctioal =.V, VIN = or N + o VO > VOL < V = 0V, VIN = or N + o / / = V, VIN = or N + o = V, VIN = or N - o Iut Voltage Low (Note ) VIL = V, VO >.V, VOL < 0.V,, + o, + o, - o -. V Iut Voltage igh (Note ) Iut Voltage Low (Note ) Iut Voltage igh (Note ) NOTS: VI = V, VO >.V, VOL < 0.V,, + o, + o, - o. - V VIL VI = V, VO >.V, VOL <.V = V, VO >.V, VOL <.V. ll voltages refereced to device N, 0% testig beig imlemeted.. o/no o test with limits alied to iuts,, + o, + o, - o - V,, + o, + o, - o - V. or accuracy, voltage is measured differetially to. Limit is 0.00V max. N Rev 0.00 Page of November

4 000MS, 00MS, 00MS, 0MS TL. LTRIL PRORMN RTRISTIS ROUP PRMTR SYMOL ONITIONS (NOT, ) SUROUPS TMPRTUR MIN MX UNITS Proagatio elay TPL = V, VIN = or N + o - 0 s TPL, + o, - o - s Trasitio Time TTL = V, VIN = or N + o - 00 s TTL, + o, - o - 0 s NOTS:. L = 0, RL = 00K, Iut TR, T < 0s.. - o ad + o limits guarateed, 0% testig beig imlemeted. TL. LTRIL PRORMN RTRISTIS PRMTR SYMOL ONITIONS NOTS TMPRTUR MIN MX UNITS Suly urret I = V, VIN = or N, - o, + o o -. = V, VIN = or N, - o, + o o -. = V, VIN = or N, - o, + o o -.0 Outut Voltage VOL = V, No Load, + o, + o, - 0 mv - o Outut Voltage VOL = V, No Load, + o, + o, - 0 mv - o Outut Voltage VO = V, No Load, + o, + o,. - V - o Outut Voltage VO = V, No Load, + o, + o,. - V - o Outut urret (Sik) IOL = V, VOUT = 0.V, + o 0. - m - o 0. - m Outut urret (Sik) IOL = V, VOUT = 0.V, + o 0. - m - o. - m Outut urret (Sik) IOL = V, VOUT =.V, + o. - m - o. - m Outut urret (Source) IO = V, VOUT =.V, + o m - o m Outut urret (Source) IO = V, VOUT =.V, + o - -. m - o m Outut urret (Source) IO = V, VOUT =.V, + o m - o - -. m Outut urret (Source) IO =V, VOUT =.V, + o - -. m - o - -. m Iut Voltage Low VIL = V, VO > V, VOL < V Iut Voltage igh VI = V, VO > V, VOL < V Proagatio elay TPL TPL Trasitio Time TTL TTL, + o, + o, - o, + o, + o, - o - V - V = V,, + o - s = V,, + o - 0 s = V,, + o - 0 s = V,, + o - 0 s N Rev 0.00 Page of November

5 000MS, 00MS, 00MS, 0MS PRMTR SYMOL ONITIONS NOTS TMPRTUR MIN MX UNITS Iut aacitace IN y Iut, + o -. NOTS:. ll voltages refereced to device N.. The arameters listed o Table are cotrolled via desig or rocess ad are ot directly tested. These arameters are characterized o iitial desig release ad uo desig chages which would affect these characteristics.. L = 0, RL = 00K, Iut TR, T < 0s. TL. POST IRRITION LTRIL PRORMN RTRISTIS PRMTR SYMOL ONITIONS NOTS TMPRTUR MIN MX UNITS Suly urret I = 0V, VIN = or N, + o -. N Threshold Voltage VNT = V, ISS = -, + o V N Threshold Voltage VNT = V, ISS = -, + o - V elta P Threshold Voltage VPT = 0V, I =, + o 0.. V P Threshold Voltage VPT = 0V, I =, + o - V elta uctioal = V, VIN = or N + o VO > VOL < V = V, VIN = or N / / Proagatio elay Time TPL TPL = V,,, + o -. x + o Limit s NOTS: TL. LTRIL PRORMN RTRISTIS (otiued). ll voltages refereced to device N.. L = 0, RL = 00K, Iut TR, T < 0s.. See Table for + o limit.. Read ad Record TL. URN-IN N LI TST LT PRMTRS + O PRMTR SYMOL LT LIMIT Suly urret - SSI I 0. Outut urret (Sik) IOL 0% x Pre-Test Readig Outut urret (Source) IO 0% x Pre-Test Readig TL. PPLIL SUROUPS ONORMN ROUP MIL-ST- MTO ROUP SUROUPS R N ROR Iitial Test (Pre ur-i) 0% 00,, I, IOL Iterim Test (Post ur-i) 0% 00,, I, IOL Iterim Test (Post ur-i) 0% 00,, I, IOL P (Note ) 0% 00,,, eltas Iterim Test (Post ur-i) 0% 00,, I, IOL, IO P (Note ) 0% 00,,, eltas ial Test 0% 00,,,,, rou Samle 00,,,,,,,, rou Subgrou - Samle 00,,,,,,,,, eltas Subgrous,,,,, Subgrou - Samle 00,, rou Samle 00,,,,, Subgrous, NOT:. % Parameteric, % uctioal; umulative for Static ad. TL. TOTL OS IRRITION MIL-ST- TST R N ROR ONORMN ROUPS MTO PR-IRR POST-IRR PR-IRR POST-IRR rou Subgrou 00,, Table, Table N Rev 0.00 Page of November

6 000MS, 00MS, 00MS, 0MS TL. URN-IN N IRRITION TST ONNTIONS OSILLTOR UNTION OPN ROUN V -0.V 0kz kz PRT NUMR 000MS Static ur-i,,,, -,,, - Note Static ur-i,,,, -,, - Note yamic ur-,,, -,, - I Note Irradiatio Note,,,, -,, - PRT NUMR 00MS Static ur-i Note,,,,, -,, Static ur-i Note yamic ur- I Note Irradiatio Note,,,,,,,,, - -,,,,,,,,,,,,,,,,,,, - PRT NUMR 00MS Static ur-i,,, -,, - Note Static ur-i,,, -, -, Note yamic ur-,, -, - I Note Irradiatio Note,,, -, -, PRT NUMR 0MS Static ur-i,, -,,, - Note Static ur-i,, -,, - Note yamic ur- -,, -,, - I Note Irradiatio,, -,, - Note NOT:. ach i excet ad N will have a series resistor of K %, = V 0.V. ach i excet ad N will have a series resistor of K %; rou, Subgrou, samle size is dice/wafer, 0 failures, = V 0.V oyright Itersil mericas LL. ll Rights Reserved. ll trademarks ad registered trademarks are the roerty of their resective owers. or additioal roducts, see Itersil roducts are maufactured, assembled ad tested utilizig ISO00 quality systems as oted i the quality certificatios foud at Itersil roducts are sold by descritio oly. Itersil may modify the circuit desig ad/or secificatios of roducts at ay time without otice, rovided that such modificatio does ot, i Itersil's sole judgmet, affect the form, fit or fuctio of the roduct. ccordigly, the reader is cautioed to verify that datasheets are curret before lacig orders. Iformatio furished by Itersil is believed to be accurate ad reliable. owever, o resosibility is assumed by Itersil or its subsidiaries for its use; or for ay ifrigemets of atets or other rights of third arties which may result from its use. No licese is grated by imlicatio or otherwise uder ay atet or atet rights of Itersil or its subsidiaries. or iformatio regardig Itersil ororatio ad its roducts, see N Rev 0.00 Page of November

7 000MS, 00MS, 00MS, 0MS Schematic ad Logic iagrams *LL INPUTS R PROTT Y MOS PROTTION NTWORK * () * () * () () * INVRTR N O TS (NUMRS IN PRNTSS R TRMINL NUMRS OR SON T) * (,, ) V (,, ) () () () * (,, ) V SS O TS (NUMRS IN PRNTSS R TRMINL NUMRS OR OTR TS) () LOI IRM (,,) 000MS (,, ) LOI IRM 00MS (,, ) V * () * () * () * () () * (, ) * (, ) * (, ) V (, ) O TS (NUMRS IN PRNTSS R TRMINL NUMRS OR SON T) () V SS O TS (NUMRS IN PRNTSS R TRMINL NUMRS OR OTR TS) V SS () () () (, ) (, ) (, ) () LOI IRM (, ) LOI IRM 00MS 0MS N Rev 0.00 Page of November

8 000MS, 00MS, 00MS, 0MS Tyical Performace haracteristics OUTPUT VOLT (VO) (V) MINT TMPRTUR (T ) = + o SUPPLY VOLT () = V V V 0 0 INPUT VOLT (VI) (V) IUR. TYPIL VOLT TRNSR RTRISTIS POWR ISSIPTION PR T (P) ( W) MINT TMPRTUR (T ) = + o SUPPLY VOLT () = V V V V L = 0 L = INPUT RQUNY (fi) (kz) IUR. TYPIL POWR ISSIPTION vs RQUNY MINT TMPRTUR (T ) = + o MINT TMPRTUR (T ) = + o OUTPUT LOW (SINK) URRNT (IOL) (m) 0 0 V T-TO-SOUR VOLT (VS) = V V OUTPUT LOW (SINK) URRNT (IOL) (m)... T-TO-SOUR VOLT (VS) = V V V 0 RIN-TO-SOUR VOLT (VS) (V) IUR. TYPIL OUTPUT LOW (SINK) URRNT RTRISTIS 0 RIN-TO-SOUR VOLT (VS) (V) IUR. MINIMUM OUTPUT LOW (SINK) URRNT RTRISTIS RIN-TO-SOUR VOLT (VS) (V) MINT TMPRTUR (T ) = + o T-TO-SOUR VOLT (VS) = -V -V -V OUTPUT I (SINK) URRNT (IO) (m) RIN-TO-SOUR VOLT (VS) (V) MINT TMPRTUR (T ) = + o T-TO-SOUR VOLT (VS) = -V -V -V OUTPUT I (SINK) URRNT (IO) (m) IUR. TYPIL OUTPUT I (SOUR) URRNT RTRISTIS IUR. MINIMUM OUTPUT I (SOUR) URRNT RTRISTIS N Rev 0.00 Page of November

9 000MS, 00MS, 00MS, 0MS Tyical Performace haracteristics (otiued) MINT TMPRTUR (T ) = + o 00 MINT TMPRTUR (T ) = + o TRNSITION TIM (ttl, ttl) (s) SUPPLY VOLT () = V V V PROPTION LY TIM PR T (tpl, tpl) (s) SUPPLY VOLT () = V V V LO PITN (L) () IUR. TYPIL TRNSITION TIM vs LO PITN hi imesios ad Pad Layouts LO PITN (L) () IUR. TYPIL PROPTION LY TIM vs LO PITN 000MS 00MS 00MS 0MS imesios i aretheses are i millimeters ad are derived from the basic ich dimesios as idicated. rid graduatios are i mils ( - ich) N Rev 0.00 Page of November

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