Statistical Gate Delay Model for Multiple Input Switching. Takayuki Fukuoka, Akira Tsuchiya and Hidetoshi Onodera Kyoto University

Transcription

1 Statistical Gate Delay Model for Multiple Input Switching Takayuki Fukuoka, Akira Tsuchiya and Hidetoshi Onodera Kyoto University 1

2 Outline Motivation Effect of Multiple Input Switching on the gate delay Gate Delay Model for Multiple Input Switching Experimental results Conclusions 2

3 Motivation Technology scaling Increasing significance of process variations Corner-based timing analysis become too pessimistic Statistical Static timing analysis (SSTA) Statistical Max operation Multiple input switching 3

4 Multiple Input Switching Single Input Switching (SIS) Only one of inputs switches SIS assumption is correct when one input transition is away from the other A OUT =MAX(A A +D A, A B +D B ) Multiple Input switching (MIS) Two inputs switch at the same time Gate delay is different from that of SIS We propose gate delay model considering MIS effect 4

5 Outline Motivation Effect of Multiple Input Switching on the gate delay Gate Delay Model for Multiple Input Switching Experimental results Conclusions 5

6 SIS Multiple Input Switching One p-channel transistor turns on MIS Inputs A and B rise simultaneously Two P-channel transistors turn on Actual gate delay becomes smaller than that of SIS 6

7 Example of MIS effect Output rise when input A or B fall D B D A A A /A B : Arrival time of input A / B S AB : Separation between A A and A B SIS: D A 49ps D B 53ps Input transition time: 100ps Output capacitance: FO4 Actual gate delay changes by S AB up to 34% 7

8 Example of MIS effect Output fall when both inputs A and B rise D B D A Actual gate delay increases as S AB gets close to 0 MIS also affects output transition time It is necessary to consider MIS effect 8

9 Outline Motivation Effect of Multiple Input Switching on the gate delay Gate Delay Model for Multiple Input Switching Experimental results Conclusions 9

10 Proposed Gate Delay Model Replace conventional gate delay with the proposed gate delay Proposed gate delay model as a function of S AB D A S AB D A (S AB ) S AB Other parts are not changed (e.g. Max operation) 10

11 Estimation of proposed gate delay Proposed gate delay is a function of S AB We estimate the proposed gate delay from SPICE results SPICE results: A OUT =MAX(A A +D A, A B +D B ) When A A + D A > A B + D B, D A = A out A A When A A + D A < A B + D B, D A =? We assume D A (S AB ) is symmetric to S AB =0 11

12 µ and σ of Gate delay model Assume that all variations are normally distributed Calculate the mean and variance of D A (S AB ), D B (S AB ) µ D D ( S ) p( S ) ds ( A) = A AB AB AB D A (S AB ) 2 2 σ ( D A) = ( DA( S AB ) µ ( DA)) p( S AB ) ds AB Probability density function of S AB : p( S AB ) 1 ( S exp µ AB AB = 2 2πσ AB 2σ AB ) 2 A OUT = MAX( A A + proposed D A, A B + proposed D B ) MAX is calculated by Clark s method 12

13 Proposed method under gate length variations, etc. Canonical gate delay model can handle the effect of gate length variations, etc Conventional gate delay D A = µ A + α A, j j r j µ A r j : mean of ~ N(0,1) D A Gate length variations, etc Proposed gate delay D A ' + + = µ A' γ A, jrj β A, j j j γ = µ ' α A A, j A, j µ A r S AB variations j 13

14 Estimation of output transition time Output transition time T OUT = p T OUT,A + (1-p) T OUT,B p = P(A A +D A > A B +D B ) Proposed method Similar way to the proposed gate delay model T OUT,A proposed T OUT,A (S AB ) T OUT,B proposed T OUT,B (S AB ) 14

15 Outline Motivation Effect of Multiple Input Switching on the gate delay Gate Delay Model for Multiple Input Switching Experimental results Result1 : only Sab is a statistical parameter Result2 : Sab, Gate length, input transition time are statistical parameters Conclusions 15

16 Experimental setup Comparison with SPICE-based Monte Carlo Sim. Conventional method A OUT = MAX/MIN( A A +D A, A B +D B ) Proposed method A OUT = MAX/MIN( A A + proposed D A, A B + proposed D B ) S AB : statistical parameter with normal distribution e.g. S AB N(0, 10), N(10,10) and so on A A D A A out Input transition time 50ps, 100ps, 200ps, 400ps A B D B FO1, FO4, FO16 16

17 Example of experimental result SPICE Mean of S AB [ps] Proposed method % error in µ % error in σ % error in µ+3σ % error in µ w/o MIS % error in σ % error in µ+3σ Proposed method 43.7% Conventional method (w/o MIS) Proposed method SPICE Conventional method (w/o Rise delay Input transition time: 100ps Output capacitance: FO4 17

18 Result1 Input transition time: 50ps, 100ps, 200ps, 400ps Output capacitance: FO1, FO4, FO16 large error: 35% ~55% 10% ~10% Conventional method Proposed method Proposed method reduces the error 18

19 Result2 Rise delay Gate length: ±20%, Input transition time: ±20% large error: 10% ~70% 10% ~10% Conventional method Proposed method MIS have a significant effect on gate delay and output transition time Proposed method reduces the error by considering MIS effect 19

20 Conclusions Ignoring MIS cases the large error in statistical maximum operation in SSTA We propose the gate delay model considering MIS We show the proposed method reduce the error from 70% to 10% Future works We need to reduce cell characterization cost 20