Design and Calibration Techniques for SAR and Pipeline ADCs

Transcription

1 Erik Jonsson School of Engineering & Computer Science Design and Calibration Techniques for SAR and Pipeline ADCs Yun Chiu Erik Jonsson Distinguished Professor Texas Analog Center of Excellence University of Texas at Dallas

2 Course Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital-Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-adc, sub-dac, input) Two-ADC Equalization (ref.-adc, split-adc, ODC) Energy Efficiency and Trend Summary IN2P3, 5/20/15-2- Y. Chiu

3 Course Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital-Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-adc, sub-dac, input) Two-ADC Equalization (ref.-adc, split-adc, ODC) Energy Efficiency and Trend Summary IN2P3, 5/20/15-3- Y. Chiu

4 What is A/D Conversion? ref CT, CA in out DT, DA Analog Input Digital Output f s V Vin t N Vin nt FS s LSB = =, Dout n = = 2 N 2 VFS t=nt s Quantization = division + normalization + truncation V FS is the Full-Scale range of ADC determined by V ref. IN2P3, 5/20/15-4- Y. Chiu

5 Quantization Error (or Noise) N = 3 D out N is large V in >>, V in is active ε is uniformly distributed P ε V FS V FS 2 V in 1/ /2 0 /2 ε - ε 2 2 / σ ε = ε dε = 12 - /2 "Random" quantization error is usually regarded as noise. Ref. [1] IN2P3, 5/20/15-5- Y. Chiu

6 Flash ADC Exhaustive Search V FS V i Strobe f s Massive parallelism Very fast Encoder D out Reference ladder consists of 2 N equal size resistors Input is compared to 2 N -1 reference voltages Throughput = f s 2 N -1 comparators Complexity = 2 N Flash ADC is rarely used for beyond 6-8 bits due to complexity. IN2P3, 5/20/15-6- Y. Chiu

7 Long Division (Decimal Case) = 183 r 3 Dividend Divisor Quotient Remainder Step 1: 1 st bit Step 2: 2 nd bit Step 3: 3 rd bit IN2P3, 5/20/15-7- Y. Chiu

8 Quantization (Binary Case) N = 3, FS = 1000, = 1000/8 = 125, V in = 735 D = o V in = 1,0,1 r 110 Vin LSB QN Do Step 1: 1 st bit Step 2: 2 nd bit Step 3: 3 rd bit The procedure is also known as "binary search". IN2P3, 5/20/15-8- Y. Chiu

9 Successive-Approximation (SAR) ADC SAR = 1 comparator + 1 DAC + digital logic IN2P3, 5/20/15-9- Y. Chiu

10 Binary Search MSB Cycle 0.735V N = 3, FS = 1 V, = V, V in = V 0.5V... Sampling V X = V i 0.5V; if V X > 0, MSB = 1, keep current V X V X ; otherwise, MSB = 0, restore V X V X + 0.5V; IN2P3, 5/20/ Y. Chiu

11 Binary Search MSB-1 Cycle 0.235V N = 3, FS = 1 V, = V, V in = V 0.25V... Sampling V X = V X 0.25V; if V X > 0, MSB-1 = 1, keep current V X V X ; otherwise, MSB-1 = 0, restore V X V X V; IN2P3, 5/20/ Y. Chiu

12 Binary Search MSB-2 Cycle 0.235V N = 3, FS = 1 V, = V, V in = V 0.125V... Sampling V X = V X 0.125V; if V X > 0, MSB-2 = 1, keep current V X V X ; otherwise, MSB-2 = 0, restore V X V X V; IN2P3, 5/20/ Y. Chiu

13 Quantization (Binary) Modified N = 3, FS = 1000, = 1000/8 = 125, V in = 735 D = o V in = 1,0,1 r 110 Vin LSB QN Do Step 1: 1 st bit Step 2: 2 nd bit Step 3: 3 rd bit Always use the same divisor but amplify the residue. IN2P3, 5/20/ Y. Chiu

14 Algorithmic (Cyclic) ADC Fixed comparison threshold (V FS /2) + 1-b DAC + Residue Amplifier Modified "Binary Search" IN2P3, 5/20/ Y. Chiu

15 Bit Cycles V o V FS b j =0 b j =1 0 V FS /2 V FS V X Comparison if V X < V FS /2, then b j = 0; otherwise, b j = 1 Residue generation V o = 2 (V X -b j V FS /2) IN2P3, 5/20/ Y. Chiu

16 Pipelined ADC Algorithmic ADC loop unrolled pipeline enables high throughput IN2P3, 5/20/ Y. Chiu

17 Presentation Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital-Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-adc, sub-dac, input) Two-ADC Equalization (ref.-adc, split-adc, ODC) Energy Efficiency and Trend Summary IN2P3, 5/20/ Y. Chiu

18 What happens with circuit offsets? Ideal RA offset CMP offset V o V o V o V FS b=0 b=1 V FS b=0 b=1 V os V FS b=0 b=1 V os 0 V FS /2 V FS V i 0 V FS /2 V FS V i 0 V FS /2 V FS V i D o D o D o 0 V FS /2 V FS V i V FS /2 V i 0 V FS 0 V FS /2 V FS V i Nearly zero tolerance on circuit offset errors!! IN2P3, 5/20/ Y. Chiu

19 Over-range & Under-range Comparators V o V o V FS b j =0 b j =1 V FS b j =0 b j =1 B j+1 =2 B j+1 =1 B j+1 =1 V FS /2 V FS /2 B j+1 =0 B j+1 =0 0 V FS /2 V FS V i 0 V FS /2 V FS V i B j+1 =-1 D o D o V FS /2 V FS V i 00 0 V FS /2 V FS V i 1 CMP 3 CMPs IN2P3, 5/20/ Y. Chiu

20 Redundancy (a.k.a. DEC or RSD) Original w/ Redundancy V o V o V FS b=0 b=1 b=-1 b=0 b=1 b=2 0 V FS /2 V FS V i 0 V FS /2 V FS V i 4-level (2-bit) DAC required instead of 2-level (1-bit) DAC IN2P3, 5/20/ Y. Chiu

21 Complementary Analog-Digital Information V o V FS b j =0 b j =1 V FS /2 0 V FS /2 V FS D o bit 1 FS 0 V FS /2 V FS V i V i B j+1 =2 B j+1 =1 B j+1 =0 B j+1 =-1 Max tolerance of comparator offset is ±V FS /4 simple comparators Key to understand redundancy: Vo b j =0 2 V V V= i b FS o j IN2P3, 5/20/ Y. Chiu

22 From 1-bit to 1.5-bit Architecture ½ FS ½ bit 1-bit No redundancy Vo b =0 2 IN2P3, 5/20/ Y. Chiu

23 From 1-bit to 1.5-bit Architecture ½ bit ½ FS ½ bit ½ FS Vo b =0 2 Vo b =0 2 IN2P3, 5/20/ Y. Chiu

24 From 1-bit to 1.5-bit Architecture Vo b =0 2 Vo b =0 2 Center the two thresholds optimal symmetric offset tolerance IN2P3, 5/20/ Y. Chiu

25 The 1.5-bit Architecture V =2V - b-1 V o i R 3 decision levels ENOB = log 2 3 = 1.58 Max tolerance of comparator offset is ±V R /4 An implementation of the Sweeny-Robertson-Tocher (SRT) division principle The conversion accuracy relies on the loop-gain error, i.e., the gain error and nonlinearity A 3-level DAC is required Can the same technique be applied to SAR? Ref. [2] IN2P3, 5/20/ Y. Chiu

26 1.5-bit Multiplier DAC (MDAC) Φ 2 V i Φ 1 C 1 Φ 1 C 2 -V R /4 A V o V R /4 Φ 1e -V R 0 V R Decoder Φ 2 V o C C C Vi b 1 V R 1 C C 1 V =2 V - b-1 V o i R 2X gain + 3-level DAC + subtraction all integrated Can be generalized to n.5-bit architectures IN2P3, 5/20/ Y. Chiu

27 2.5-bit Multiplier DAC (MDAC) Φ 2 Φ 1 C 1 V R V o V i b=0 b=1 b=2 b=3 b=4 b=5 b=6 Φ 1 C 2 V R /2 V R 1 V R 6 Φ 1 C 3 0 V i 6 CMP s b Φ 1 C 4 -V R /2 A V o -V R Φ 2 Φ 1e 0 V R Decoder Φ 2 Φ 2 -V R -5V R /8-3V R /8 -V R /8 V R /8 3V R /8 5V R /8 V R V =4 V - b-3 V o i R 4X gain + 7-level DAC + subtraction all integrated IN2P3, 5/20/ Y. Chiu

28 Residue Transfer Function (2.5b MDAC) V o V R V R /2 b=-3 b=-2 b=-1 b=0 b=1 b=2 b=3 overflow range 0 normal range -V R /2 -V R V R V R 1 V R 2 V R 3 V R 4 V R 5 V R 6 underflow range V i Only half of the internal dynamic range is used under ideal condition! IN2P3, 5/20/ Y. Chiu

29 With comparator offset V o V R V R /2 b=-3 b=-2 b=-1 b=0 b=1 b=2 b=3 overflow range 0 normal range -V R /2 -V R V R V R 1 V R 2 V R 3 os V R 4 V R 5 V R 6 underflow range V i IN2P3, 5/20/ Y. Chiu

30 Internal Redundancy V o V R V R / overflow range 0 normal range -V R /2 -V R V R V R 1 V R 2 V R 3 V R 4 V R 5 V R 6 underflow range V i Comparator and amplifier offsets tolerated by internal redundancy. IN2P3, 5/20/ Y. Chiu

31 How does Redundancy work in SAR? Binary search is efficient, but displays zero error tolerance. IN2P3, 5/20/ Y. Chiu

32 Binary Search Revisited +FS in -FS X When everything is ideal IN2P3, 5/20/ Y. Chiu

33 Binary Search w/ Dynamic Error +FS in -FS X Settling error, comparator hysteresis etc. IN2P3, 5/20/ Y. Chiu

34 Overlapping Search Ranges +FS 1111 X in FS 0000 Results indicate decision trajectory, no longer binary-coded. IN2P3, 5/20/ Y. Chiu

35 Redundancy of Sub-binary Search +FS in -FS X Dynamic errors absorbed by redundancy. IN2P3, 5/20/ Y. Chiu

36 SAR Redundancy Redundant conversion consumes more bit cycles, but can recover intermediate decision errors. Redundancy can be exploited to expedite conversion progress or to save power. DAC levels (matching) still need to be accurate. (will come back to this later ) IN2P3, 5/20/ Y. Chiu

37 Presentation Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital-Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-adc, sub-dac, input) Two-ADC Equalization (ref.-adc, split-adc, ODC) Energy Efficiency and Trend Summary IN2P3, 5/20/ Y. Chiu

38 Pipelined ADC Errors (I) 1.5b MDAC Capacitor mismatch Op-amp finite-gain error and nonlinearity Charge injection and clock feed-through (S/H) Settling error V =2 V -d V o i R V o C1 C2 C2 t fs Vi dv C1C2 C1C2 C1 C1 A V A V o /H R o IN2P3, 5/20/ Y. Chiu

39 Pipelined ADC Errors (II) 2.5b MDAC DAC bit-encoding scheme d j d j, d j, d j, d j = d j,1 + d j,2 + d j,3 V j C1 C2 C C = dj, 1 + dj,2 + dj,3 Vr + Vj + 1 C C C C A C V j+1 IN2P3, 5/20/ Y. Chiu

40 RA Gain Error and Nonlinearity R o o R i R R R R R R i R IN2P3, 5/20/ Y. Chiu

41 RA Gain Error and Nonlinearity R o o R i R R R R R R i R Raw accuracy is usually limited to bits w/o error correction. IN2P3, 5/20/ Y. Chiu

42 RA Gain Error and Nonlinearity R o o R i R R R R R R i R Raw accuracy is usually limited to bits w/o error correction. IN2P3, 5/20/ Y. Chiu

43 The Basic Idea of Digital Calibration ADC Digital Computation Unknown System System Inversion Calibration = efficient digital processing to undo certain analog errors e.g., SC amplifier: Analog soln: Vo C Vi C2 βa match C 1 and C 2 make βa very large Digital soln: any constant C 1 and C 2 any constant A is fine IN2P3, 5/20/ Y. Chiu

44 Two Essential Components of Dig. Cal. 1. A digital-domain technique (e.g. equation) to recover accurate analog information from raw digital output Treat analog precision or linearity only Neglect small consequence on SNR A CL - C C2 βa =# 2. An algorithm to identify the error parameters Foreground vs. Background techniques IN2P3, 5/20/ Y. Chiu

45 Linear MDAC Correction Analog residue function: C1 C2 C3 C 4 + C A V j,1 j,2 j,3 j = d + d + d Vr + Vj+ 1 C C C C Normalized residue function: Vj C1 C2 C3 Vj+1 C 4 + C A = dj,1 + dj,2 + dj,3 + Vr C C C Vr C Vj 1 Vj Vj+1 1 = dj,1 + dj,2 + dj, 3 + = dj + V 4 V 4 4 V 4 r Digital representation: D = d β + d β + d β + D α j j,1 j,1 j,2 j,2 j,3 j, 3 j+1 j = k d β + D α j,k j, k j+ 1 r j r ideal residue function error parameters: { α j, β j,k } IN2P3, 5/20/ Y. Chiu

46 Bit-Weight (Radix) Correction For 1-b or 1.5-b MDAC: D =D 1 in j j j+1 j+1 j+2 j+2 j+1 j j-1... =...+ d β + d β + d β +... α α α =...+d jγj+d j+1γj+1+d j+ 2 γj weighted sum of ALL bits! (bit weight or radix error) Alternatively, D =D 1 in dj dj+1 dj+2 = j j + 1+ j+1 j j+ 2 j d+ j dj j d j+1+ dj+1 j+1 d j+2+ dj+2 j+2 = j j+1 j segmental offset IN2P3, 5/20/ Y. Chiu

47 Bit-Weight (Radix) Correction d 1 =-1 d 1 =0 d 1 =1 d 1 =-1 d 1 =0 d 1 =1 d 1 =-1 d 1 =0 d 1 =1 D o D o D o -V R V i V R -V R V i V R -V R V i V R 1.5b MDAC residue nonlinearity radix error: needs multiplication segmental offset: addition only IN2P3, 5/20/ Y. Chiu

48 Nonlinear MDAC Correction Analog representation: V j V V C1 C2 C3 C 4 + = dj, 1 + dj,2 + dj,3 Vr + Vj+ 1 C C C Normalized analog representation: C1 C2 C3 V C 4 + C A = dj,1 + dj,2 + dj,3 + C C C Vr C j j+1 r C A V C j+1 V j+1 Digital representation: D dj,1 β j,1 + dj,2 β j,2 + dj,3 βj,3 D m dj,k β j,k + Dj+1 αj,m = +f j j+1 k m error parameters: { α j,m, β j,k } Next problem: how to determine {α j,m, β j,k } precisely? IN2P3, 5/20/ Y. Chiu

49 Let s try to push this Correcting nonlinearity: "Give me a place to stand on, and I will move the Earth " L Drawn 0.15μm V DD 1.2V Corrected w/ 9th-order power series -70 dbfs Archimedes, 200 BC IN2P3, 5/20/ Y. Chiu

50 On nonlinear correction Memory-less polynomial computation is efficient A few coefficients fits/predicts full-range nonlinearity (requiring digital multipliers and adders mostly) Caveat 1: coefficients depend on signal statistics! Caveat 2: coefficients depend on PVT variations! Piecewise-linear or lookup table can be useful Memory, digital power, and cost Complexity and convergence time (esp. tracking speed in background mode) Solution needs to be practical after all IN2P3, 5/20/ Y. Chiu

51 SAR Redundancy Forms (I) +FS Vin -FS Radix: 0 3/8 1/8 9/32 3/ Unit-Element DAC Best matching Arbitrary decision threshold arbitrary radix each bit DAC resolution slightly higher Binary-to-Thermo encoder (slow) Ref. [3] IN2P3, 5/20/ Y. Chiu

52 SAR Redundancy Forms (II) +FS Vin -FS Radix: 0 1/2 1/4 1/2 3/ Binary DAC Good matching Periodic redundancy non-uniform radix selective bits SAR logic slightly more complex Can also use UE DAC Ref. [4] IN2P3, 5/20/ Y. Chiu

53 SAR Redundancy Forms (III) +FS Vin -FS Radix: Sub-binary DAC Poor matching Uniform redundancy uniform radix each bit Simple layout, simple SAR logic (fast) Cannot use UE DAC Must calibrate DAC Ref. [5] IN2P3, 5/20/ Y. Chiu

54 Sub-binary DAC Construction Hard-coded in analog form No B2T encoder Simple layout V i V DAC DAC V X d 0 D o d N-1 e.g., Radix = 1.86 C N-1 C N-2 C N-3 C N-4 C N-1 C N-2 C N-3 C N-4 Ref. [5] IN2P3, 5/20/ Y. Chiu

55 Sub-binary DAC Transfer Function 2 N D o Redundant region MSB = 0 N = 14 2 N Do MSB = 1 V i 0 V L V H FS = V H = V L Note: only one transition edge shows up May 20, IN2P3 Summer IN2P3, 5/20/ Y. Chiu

56 Sub-binary DAC Quantization Vi d o = V N-1 C j 2dj -1 j=0 Cj = N-1 j=0 FS w j 3 2d -1 Q =V C 2d -1 DAC R j j j=0 V i 3 j=0 C j j V i V DAC d 3 = 1 C 3 C DAC Radix = 1.86 d 2 = 0 C 2 V X d 0 d N-1 d 1 = C 1 C C Ref. [5] C 0 C 0 D o d 0 = 1 IN2P3, 5/20/ Y. Chiu

57 Sub-binary DAC Digital Correction V i d o = = VFS N-1 j=0 w j 2d -1 j w j = bit weights N raw = 14 N net = 12 Do do Next problem: how to determine {w j } precisely? IN2P3, 5/20/ Y. Chiu

58 Presentation Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital-Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-adc, sub-dac, input) Two-ADC Equalization (ref.-adc, split-adc, ODC) Energy Efficiency and Trend Summary IN2P3, 5/20/ Y. Chiu

59 Error-Parameter Identification Techniques (BG) With PRBS test-signal injection (dither) Sub-ADC injection (comparator dither) Sub-DAC injection (DAC dither) Input injection (Independent Component Analysis) With two-adc equalization (test signal free) Reference-ADC equalization (training sequence) Split-ADC equalization (blind) Offset double conversion (ODC) (blind, single ADC) Parameter extraction is what the game is all about IN2P3, 5/20/ Y. Chiu

60 Recent BG Digital Calibration Techniques PRBS injection (Dither) T(n) V in ADC x(n) Adaptive DPP y(n) e(n) Temes [6,7], Lewis [8], Galton [9,10] Two-ADC equalization V in ADC 1 x 1 (n) Adaptive DPP y 1 (n) Adaptive ADC 2 x 2 (n) DPP y 2 (n) e(n) Lewis [11], Chiu [12], McNeill [13] IN2P3, 5/20/ Y. Chiu

61 PRBS Test-Signal Injection IN2P3, 5/20/ Y. Chiu

62 Comparison of PRBS Injection Techniques Sub-ADC injection considered as dynamic comparator offset, no removal needed higher sub-adc resolution (injection and ADC matching not req d) works only with busy input Sub-DAC injection needs to be removed in digital output higher sub-dac resolution (injection and DAC matching req d) can work with quiet input Input injection (sub-dac + sub-adc) needs to be removed in digital output No impact on sub-adc or sub-dac resolution works only with busy input IN2P3, 5/20/ Y. Chiu

63 PRBS Test-Signal Injection (Sub-ADC Injection) IN2P3, 5/20/ Y. Chiu

64 Sub-ADC Injection Comparator Dither residue path D 1 T=0 In steady state, analog gain (G 1 ) and digital gain (G 1-1 ) cancel exactly. 2 -k ¼ to avoid overflow in residue output. No need to match injection scaling factor (2 -k ) to the sub-adc thresholds. IN2P3, 5/20/ Y. Chiu

65 Sub-ADC Injection Comparator Dither d 1 =1 d 1 =2 V R V R /2 ¼ bit ½ bit V R /2 -V R typ. k = 2 Converge@ D 1 T=0 In steady state, analog gain (G 1 ) and digital gain (G 1-1 ) cancel exactly. 2 -k ¼ to avoid overflow in residue output. No need to match injection scaling factor (2 -k ) to the sub-adc thresholds. IN2P3, 5/20/ Y. Chiu

66 Exploiting Internal Redundancy Ref. [14] Input falling in shaded region randomly sees one of two RTF s dithering. Decision threshold needs not to be accurate or matched to each other. Digitization outcome is independent of PRBS when ADC is ideal!! IN2P3, 5/20/ Y. Chiu

67 Identifying Residue Gain Error Segmental offset : D 1= 1 d+d 1 1δ1+ 1 d 1 2+ d If V 1 { region 1 } and T = +1, D 1 = D ideal; if T = -1, D 1 = Dideal - δ1 If V 1 { region 2} and T = +1, D 1 = D ideal +δ 1; if T=-1, D 1 =Dideal IN2P3, 5/20/ Y. Chiu

68 Identifying Residue Gain Error Calculating correlation: 1 1 D 1T = Dideal - Pr V 1{ region 1 } -D Pr V 1{ region 2 } ideal 1 ideal = δ1pr V 1{ region 1 } δ1pr V 1{ region 2 } = δ1 Pr V 1 { region 1 or 2 } 2 D -δ D +δ ideal LMS learning: δ n+1= δ n+μd ntn D δ removedt Correlation reveals information about segmental offset. Exact size of shaded region is not important (only affects Pr(.)). Key observation: if ADC is ideal, D 1 must be uncorrelated to T. IN2P3, 5/20/ Y. Chiu

69 PRBS Test-Signal Injection (Sub-DAC Injection) IN2P3, 5/20/ Y. Chiu

70 Sub-DAC Injection DAC Dither residue path Dˆ 2 Converge@ ˆ 2 D T=0 In steady state, analog gain (G 1 ) and digital gain (G -1 1 ) cancel exactly. 2 -k ¼ to avoid overflow in residue output, DAC adds 2 bits minimum. Injection bit scaling factor (2 -k ) must match to the sub-dac unit elements. IN2P3, 5/20/ Y. Chiu

71 Sub-DAC Injection DAC Dither d 1 =1 d 1 =2 V R V R /2 ¼ bit ½ bit V R /2 Dˆ 2 -V R Converge@ typ. k = 2 In steady state, analog gain (G 1 ) and digital gain (G 1-1 ) cancel exactly. 2 -k ¼ to avoid overflow in residue output, DAC adds 2 bits minimum. Injection bit scaling factor (2 -k ) must match to the sub-dac unit elements. ˆ 2 T=0 DIN2P3, 5/20/ Y. Chiu

72 Signal-Dependent DAC Dither PRBS Injection Table V j (V R ) T = +1 T = ⅜ 0 0 -⅜ -⅛ 0 V R -⅛ ⅛ -½ V R ½ V R ⅛ ⅜ -V R 0 ⅜ PRBS only injected when input falls within the shaded region. Extra comparators needed to instrument the SD dither. Ref. [15] IN2P3, 5/20/ Y. Chiu

73 Opportunistic DAC Dither Vres/VR V =4V -V D res in R Vres/VR V =4V -V D+PN res in R Gap 0 4Vin - VR D'+PN, Vin V V res = 4Vin - VR D, o.w. Vres/VR V th V th V th Gap 1 0 th V in /V R V in /V R -2 When redundancy is not ample, blind injection requires large DR. Without additional comparators, detecting V th vicinity is difficult. IN2P3, 5/20/ Y. Chiu

74 Exploiting Comparator Metastability DFF Q+ Q- Ready Comparator resolving time T 0 V in -V th small V in -V th large Metastable output Q+, Q- Q+, Q- Ready=1 Time Normal output Ready=0 0 V in -V th Time Comparator resolving time indicates proximity of input. Proximity detector also functions as metastabilty detector/resolver. IN2P3, 5/20/ Y. Chiu

75 12b 160MS/s CMOS Prototype (40nm) (5b + 8b) synchronous two-step pipelined SAR architecture. First-stage capacitor weights identified w/ opportunistic DAC dither. IN2P3, 5/20/ Y. Chiu

76 Die Photo Clock Sub- & ADC1 PN Gen. Sub- ADC2 300μm Sub- ADC3 Sub- ADC4 Sub- ADC5 139μm Integrator + DAC MDAC1 MDAC2 MDAC3 MDAC4 40nm low-leakage CMOS process (active area = 0.042mm 2 ) Ref. [16] IN2P3, 5/20/ Y. Chiu

77 Measured ADC Dynamic Performance 90 Fs = 160MHz after cal. 90 Fin = 25MHz after cal Fin = 80MHz Fs = 160MHz db 70 db SNDR SFDR Fin [MHz] 60 SNDR SFDR Fs [MHz] IN2P3, 5/20/ Y. Chiu

78 Power Consumption Ref. [16] Analog 1.1V 2.8mW (53.6%) Digital 1.1V 2.2mW (42.2%) Total power is 4.96mW at 160MS/s operation. IN2P3, 5/20/ Y. Chiu

79 PRBS Test-Signal Injection (Input Injection) IN2P3, 5/20/ Y. Chiu

80 Direct Input Injection Algorithm works reliant on the independence b/t input and T. Multi-parameter extraction is possible by Independent Component Analysis. IN2P3, 5/20/ Y. Chiu

81 Independent Component Analysis (ICA) 1 o i D o =αd+β 1 D2-kT 2 ICA Algorithm Only two parameters need to be identified. Hérault-Jutten (HJ) stochastic de-correlation: α = α -μ g D g T n+1 n α 1 o 2 β = β -μ g D g T n+1 n β 2 o 1 In our simulation, we picked g 1 (x) = x and g 2 (x) = x 3. Ref. [17] IN2P3, 5/20/ Y. Chiu

82 Simulation Results H-J Learning Trajectory Before ENOB= After ENOB= / Typical learning pattern of the H-J algorithm Steady-state coefficient fluctuation causing low-level spurs IN2P3, 5/20/ Y. Chiu

83 ICA extended to nonlinear treatment Error model: 2 3 V = f V a +a V +a V +a V +... o i 0 1 i 2 i 3 i Update equations: j b n+1 =b n -μ D n T n j =1,...,5 j j j o Ref. [17] IN2P3, 5/20/ Y. Chiu

84 An ICA Approach for SAR Calibration Digital Post-Processing ˆd T: PRBS dˆ i T ICA recovers 2X speed at the cost of slower convergence. ALL bit weights {w j } are learned simultaneously! IN2P3, 5/20/ Y. Chiu

85 Prototype SAR ADC w/ ICA Sub-binary DAC Ref. [18] IN2P3, 5/20/ Y. Chiu

86 Prototype SAR ADC w/ ICA ICA Ref. [18] 90nm CMOS, 0.05mm 2 12b, 50MS/s in BG mode ( )mW power (45fJ/step) CICC Best Paper Award IN2P3, 5/20/ Y. Chiu

87 Measurement Results Dynamic Performance SFDR / SNDR [db] SFDR w/ cal. SNDR w/ cal. SFDR w/o cal. SNDR w/o cal. ENOB [bit] f in [MHz] Learning Curve Gear shifting helps stabilize the steady-state fluctuations. IN2P3, 5/20/ Y. Chiu

88 Two-ADC Equalization IN2P3, 5/20/ Y. Chiu

89 Two-ADC Equalization Techniques Reference-ADC equalization Slow-Fast two-adc architecture to accomplish accuracy and throughput simultaneously using adaptive equalization Two (different) ADC s needed, subject to skew error without SHA Split-ADC equalization Two almost identical ADC s employed for blind equalization Two ADC s needed, subject to skew error without SHA Offset double conversion (ODC) Self-equalization by digitizing every sample twice with opposite DC offsets injected to the input Single ADC with modified timing in background mode Conversion throughput halved in background mode IN2P3, 5/20/ Y. Chiu

90 Two-ADC Equalization (Reference-ADC) IN2P3, 5/20/ Y. Chiu

91 Reference-ADC Equalization Ref. [11,12] Concept inspired by adaptive equalization in digital comm. receivers Divide-and-conquer approach to achieve analog speed and accuracy IN2P3, 5/20/ Y. Chiu

92 EQZ of Time-Interleaved ADC Array 1X Ref. ADC D r Digital Cal. Ф r ADC 1 ADF 1 D 1 V in T/H 1X Ф 1 Ф Ф DLL Ф 1 ADC 10 D 10 ADF 10 Ф 10 Ф 10 ALL paths are aligned to the unique ref. ADC after equalization. IN2P3, 5/20/ Y. Chiu

93 Prototype 10-way TI-ADC Array Die photo Performance Comparison time of publication) Time CMOS Process Speed [MS/s] SFDR [db] FoM [fj/step] ISSCC µm ISSCC µm VLSI08 65nm ISSCC µm The 2009 DAC/ISSCC Student Design Contest Award Ref. [5] IN2P3, 5/20/ Y. Chiu

94 ADC Array EQZ Measured Spectra SNDR=31.2dB SFDR=33.0dB HD3 2fs/10 4fs/ SNDR=46.7dB SFDR=65.2dB After Cal SNDR=42.2dB SFDR=60.5dB Ref. ADC fs/10 3fs/ HD HD frequency [MHz] frequency [MHz] frequency [khz] (f s = 600MS/s, f in = 7.8MHz, A in = 0.9FS, 16k samples) IN2P3, 5/20/ Y. Chiu

95 Two-ADC Equalization (Split-ADC) IN2P3, 5/20/ Y. Chiu

96 Split-ADC Equalization Ref. [13] V o ADC A V i V o ADC B V i Blind equalization w/o reference possible by offsetting the RTFs Fast convergence due to zero-forcing equalization IN2P3, 5/20/ Y. Chiu

97 Zero Forcing ε = d B d A ε = 0 d B d A d B d A V in V in Error observation Radix correction Zero-forcing EQZ IN2P3, 5/20/ Y. Chiu

98 Two-ADC Equalization (Offset Double Conversion) IN2P3, 5/20/ Y. Chiu

99 Offset Double Conversion (ODC) for SAR Digital Post-Processing ODC enables zero-forcing self-equalization. ALL bit weights {w j } are learned simultaneously! IN2P3, 5/20/ Y. Chiu

100 How to determine Bit Weights? Is the transfer curve shift-invariant? IN2P3, 5/20/ Y. Chiu

101 How to determine Bit Weights? Is the transfer curve shift-invariant? IN2P3, 5/20/ Y. Chiu

102 How to determine Bit Weights? Is the transfer curve shift-invariant? IN2P3, 5/20/ Y. Chiu

103 How to determine Bit Weights? Shift-invariant ONLY when the transfer curve is completely linear! Non-constant difference b/t D + and D reveals bit weight information. IN2P3, 5/20/ Y. Chiu

104 Prototype SAR ADC w/ ODC Sub-binary DAC ODC Aux. DAC Ref. [19] V X CLK CMP n Ready CLK C 13 C 1 C 0 C 0 C C 13,d C 6,d CMP p d 13 d 1 d 0 +V R V R SAR Logic ACLK V in 0.13µm CMOS, 0.06mm 2 12b, 45MS/s in FG mode 3mW power (36.3 fj/step) Most read JSSC article Nov IN2P3, 5/20/ Y. Chiu

105 Measurement ADC Spectra (BG Mode) 0-20 SNDR = 60.2dB SFDR = 66.4dB THD = -61.7dB 0-20 SNDR = 70.7dB SFDR = 94.6dB THD = -89.1dB Before Cal. After Cal. db -60 db Freq [MHz] Freq [MHz] IN2P3, 5/20/ Y. Chiu

106 Convergence Time (BG Mode) e [LSB] e [LSB] e [LSB] Number for samples x Number for samples x Number for samples x MS/s 1ms IN2P3, 5/20/ Y. Chiu

107 Comparison with 12b ADCs 10 1 (@ time of publication) FoM (pj/conv. step) MS/s 45MS/s Year Total Power: 3.0mW Active area (mm 2 ) mm Year IN2P3, 5/20/ Y. Chiu

108 Summary of Dig. BG Cal. Techniques Method Parameter Test signal Injection point Reference DNC + GEC { β j,k, α j,m } multi PRBS sub-dac [9,10,20-24] Split capacitor { j } 1 PRBS sub-dac [25,26] Sig.-dep. dither { γ j } 1 PRBS sub-dac [15,16] GEC + SA { γ j } 2 PRBS sub-adc [27,28] Statistics { α j,m } 1 PRBS sub-adc [29,30] Fast GEC { γ j } 1 PRBS sub-adc [31] ICA { γ j }, { α j,m } 1 PRBS input [17,18,32,33] Ref. ADC { β j,k, α j,m } n/a n/a [5,11,12,34-36] Virtual ADC { β j,k, α j,m } offset sub-dac [37,38] Split ADC { α j,m } n/a n/a [13,39] { β j,k, α j,m } n/a n/a [40] ODC { γ j } offset input [19] { β j,k, α j,m } offset input [41] References are furnished at the end of the slides. IN2P3, 5/20/ Y. Chiu

109 Presentation Outline Principles of Multistep A/D Conversion Architectural Redundancy Error Mechanisms and Digital-Domain Calibration Error-Parameter Identification PRBS Test-Signal Injection (sub-adc, sub-dac, input) Two-ADC Equalization (ref.-adc, split-adc, ODC) Energy Efficiency and Trend Summary IN2P3, 5/20/ Y. Chiu

110 ADC Figure-of-Merit (FoM) Walden FoM: FoM W P Joule ENOB 2BW 2 Conversion - Step "Energy Efficiency" Schreier FoM: ENOB 2BW 4 FoMS 10log10 db P P: power consumption ENOB: effective number of bits BW: min{f s /2, ERBW} ERBW: effective resolution BW Walden FoM is intuitive but penalizes noise/matching-limited designs. Schreier FoM is more fair to high dynamic range designs. IN2P3, 5/20/ Y. Chiu

111 Performance, Efficiency, and Power Performan ce =2BWα ENOB HzStep Performance = Speed SNR α/2 Energy Efficiency P J α/2 2BW α ENOB Step Note: Performance Efficiency ENOB P =2BW α = Power ENOB 2BW α α=2-4 IN2P3, 5/20/ Y. Chiu

112 Performance Efficiency (PE) Chart 1E+17 1E+16 Constant performance Performance = 2 BW 3 ENOB 1E+15 1E+14 (log scale) 1E+13 1E+12 1E+11 1E+10 Constant efficiency 1E+09 1E-18 1E-17 1E-16 1E-15 1E-14 1E-13 1E-12 (log scale) X Y = Power α=3 Energy Efficiency = Power/(2 BW 3 ENOB ) IN2P3, 5/20/ Y. Chiu

113 PE Chart: Pipelined ADC (<2005) 1E+15 1E+14 Pipeline (<2005) Performance 1E+13 1E+12 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IN2P3, 5/20/ Y. Chiu

114 PE Chart: Pipelined ADC ( ) 1E+15 Pipeline (<2005) 1E+14 Pipeline ( ) Performance 1E+13 1E+12 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IN2P3, 5/20/ Y. Chiu

115 PE Chart: Pipelined ADC ( ) 1E+15 Pipeline (<2005) 1E+14 Pipeline ( ) Pipeline ( ) Performance 1E+13 1E+12 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IN2P3, 5/20/ Y. Chiu

116 PE Chart: SAR ADC (<2005) 1E+15 1E+14 SAR (<2005) Performance 1E+13 1E+12 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IN2P3, 5/20/ Y. Chiu

117 PE Chart: SAR ADC ( ) 1E+15 SAR (<2005) 1E+14 SAR ( ) Performance 1E+13 1E+12 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IN2P3, 5/20/ Y. Chiu

118 PE Chart: SAR ADC ( ) 1E+15 SAR (<2005) 1E+14 12b,160MS/s 5mW SAR ( ) SAR ( ) Performance 1E+13 1E+12 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IN2P3, 5/20/ Y. Chiu

119 PE Chart: Both ADCs (<2014) 1E+15 1E+14 Industry ADCs Pipeline (<2005) Pipeline ( ) Pipeline ( ) SAR (<2005) SAR ( ) SAR ( ) Performance 1E+13 1E+12 University ADCs 10W 1E+11 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IN2P3, 5/20/ Y. Chiu

120 PE Chart: Both ADCs (<2014) 1E+15 1E+14 ADI TI KENET NSC BCM Agilent Pipeline (<2005) Pipeline ( ) Pipeline ( ) SAR (<2005) SAR ( ) SAR ( ) Performance 1E+13 OSU IMEC 1E+12 NCTU NCKU OSU AKM Panasonic MIT Michigan Fujitsu ADI 10W 1E+11 EUT 1W 10μW 100μW 1mW 10mW 100mW 1E+10 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 Efficiency ISSCC & VLSI data IN2P3, 5/20/ Y. Chiu

121 To conclude Thank you for your attendance! IN2P3, 5/20/ Y. Chiu

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