EE 505 Lecture 8. Clock Jitter Statistical Circuit Modeling

Transcription

1 EE 505 Lecture 8 Clock Jitter Statistical Circuit Modeling

2 Spectral Characterization of Data Converters Distortion Analysis Time Quantization Effects of DACs of ADCs Amplitude Quantization Effects of DACs of ADCs Clock Jitter

3 Effects of Jitter on Spectral Performance

4 Model of Jitter T S Ideal Clock Jittery Clock t Jk Assume t Jk are uncorrelated uniformly distributed random variables θ θ tjk U- T S, TS ote: there can also be jitter in the ideal clock or there may be no ideal clock so zero crossings may be modeled as a random walk or a sum of a random walk and uniform jitter. Analysis is more complicated in these cases.

5 Analytical Characterization of Clock Jitter Assume the input can be expressed as V I VEF VEF = + sinωt+θ ather than assuming that the clock has jitter and the input has no jitter, it will be assumed that the clock has no jitter but the input contains the jitter. This should provide the same jitter-based sampling errors. Thus, it will be assume that the time variable in the input can be expressed as t t t where t the nominal time and t is the random time (that has been added to the input rather than the clock) The input can be expanded in a Taylor s series as V V V = I I I VI t 0 t t t! t t 0 t 0 Truncating after first-order terms we have V I V I t 0 V + t I t 0 t

6 Analytical Characterization of Clock Jitter V I V I t 0 V + t I It now follows from the expression from the input that Thus V t I t 0 V EF t 0 t ωcos ω t +θ VEF VEF VEF VI sinωt +θ + ωcosω t +θ I_Sig I_jitter The signal and noise jitter components can be identified as V V VEF VEF sinωt +θ VEF ωcosω t+θt t

7 Analytical Characterization of Clock Jitter V V I_Sig I_jitter Will now obtain the S Jitter VEF VEF sinωt +θ VEF ωcosω t+θt Observe the jitter noise can be expressed as VEF VI_jitter ωcosω t+θ Consider the following theorem: t Theorem: If X (t) is a zero-mean random process and X (t) is a periodic deterministic function where the MS value of X is X MS and the MS value ofx is X M S,then the MS value of the product is given by the expression X M S=X MS X MS

8 Analytical Characterization of Clock Jitter VEF VI_jitterMS ωcosω t+θ MS t MS ecall it has been assumed that at the zero crossings of the sampling clock ecall another theorem VEF VEF ωcosω t +θ θ θ t U- T S, TS MS Theorem: If n(t) is a random process and <n(kt S )> is a sequence of samples of n(t) then for large T/T S, t +T V = n t dt = σ +μ MS T n kts n kt t t MS t θt S Thus the MS value of the jitter time sequence obtained by sampling the jitter at multiples of the nominal sampling period T can be expressed as S

9 Analytical Characterization of Clock Jitter VEF VI_jitterMS ωcosω t+θ MS t MS We thus have V I_jitterMS V EF t For full-signal input, the MS value is given by V I_SigMS V EF It thus follows that the S is given by S Jitter V EF VEF t t

10 Analytical Characterization of Clock Jitter Or in db we thus have S S S Jitter 0log f Jitter _ db t t log f Jitter _ db t For small f or σ t the right-most term is large and positive This can be compared to the quantization noise S Quant _ 6.0n.76 db As the f σ t product gets large, the jitter will dramatically degrade performance

11 Combined Quantization and Jitter oise ecall Thus V V QuantMS SigMS Alternately V V V noisems VLSB VEF n VEF S S S Jitter Quant Jitter Quant Jitter QuantdB QuantMS I_jitterMS VEF V 8 EF t V 3 EF t n S S Jitter Quant 0log S S Jitter Quant n

12 Combined Quantization and Jitter oise S Jitter Quant t 8 3 n Crossover Frequency f t n n 3 t

13 Model of Jitter Assume t Jk are uncorrelated uniformly distributed random variables θ θ tjk U- T S, TS Consider θ=.0,.00,.000,.0000 Observe: If T S is a 00MHz clock, then T S =0nsec and θ=.000 corresponds to psec (±0.5psec) of symmetric jitter

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18 Statistical Characterization of Electronic Components and Circuits ecall: Almost all data converter structures work perfectly if components are ideal Major challenges in data converter design Parasitic esistances and Capacitances onlinearity in components Statistical variation in components and circuits Model uncertainties Power supply variability

19 Consider a flash ADC V EF V I Thermometer to Binary Decoder n X OUT esistor values and offset voltages of Comparators are all random variables at design level Variations of these Vs affect the break point and thus the yield

20 Consider Current-Steering DAC V DD I I / I /4 I /8 b 3 b b b 0 F V OUT Ideally n - b i OUT F n-i i=0 V = -I

21 Consider Current-Steering DAC V DD V DD M EF M n- M M 0 I I / I /4 I /8 b 3 b b b 0 F V I n- I I 0 V OUT I EF b n- M (n-)s M S b0 b M 0S Basic Implementation of Current Sources Ideally Actually I μc W V -V OX k k Tp L k L k=l0 k- W k= W0 I μc W V -V k OXk k k Tpk L k I k is a random variables and is a function of the model parameters μ k, C OXk, W k, L k, and V Tpk μ k, C OXk, W k, L k, and V Tpk are all random variables

22 ecall from previous lecture How important is statistical analysis? Example: 7-bit FLASH ADC with -string DAC V EF V I Assume -string is ideal, V EF =V and V OS for each comparator must be at most +/- ½ LSB Case Standard deviation is 5mV Case P COMP = Y =3. 0 ADC -3 Thermometer to Binary Decoder n X OUT Standard deviation is mv P COMP Y =0.988 ADC Statistics play a key role in the performance and consequently yield of a data converter

23 Statistical Analysis Strategy Will first focus on statistical characterization of resistors, then extend to capacitors and transistors Every resistor can be expressed as = + P + W + D + GAD + L where is the nominal value of the resistor and the remaining terms are all random variables P : andom process variations W : andom wafer variations D : andom die variations GAD : andom gradient variations L : Local andom Variations

24 Statistical Analysis Strategy = + P + W + D + GAD + L P : andom process variations W : andom wafer variations D : andom die variations P W D GAD : andom gradient variations L : Local andom Variations All variables uncorrelated For good common-centroid layouts gradient effects can be neglected Local random variations often much smaller than P, W, and D though not necessarily Area dominantly determines σ L, has little effect on other variables At the resistor-level on a die, P, W and D highly correlated thus cause no mismatch Major challenge in data converter design is managing D effects All zero mean and approximately Gaussian (truncated) For notational convenience, assume = + includes P, W and D, GAD neglected, = L

25 esistor Characterization esistors are generally made of thin films of conductive or semiconductor materials L W Film Characterized by esistivity : ρx,y,z h Generally h is very small compared to L and W Films are often characterized by Sheet esistance Ideally ρ(x,y,z) is independent of position as is (x,y) L L In the ideal case = = h W W ρ x,y,z x,y = h x,y

26 esistor Characterization esistors are generally made of thin films of conductive or semiconductor materials Ideally A L W B = L W ρ = h

27 esistor Characterization Ideally A L W y Actually A L B B W x H Boundary of resistor varies ρ(x,y,z) varies with position Thickness (H(x,y)) varies with position Properties of resistor vary with position and temperature

28 Ideally esistor Characterization A Actually y L B W L x B W Boundary of resistor varies ρ(x,y,z) varies with position These variations will define

29 Consider the following resistor circuits A = + Statistical Model A B Series esistor Connection mean 0 standard deviation Distribution: Truncated Gaussian = + = + Ser = + + ~ 0, B Compare the standard deviation of the resistance of the series combination with that of a single resistor

30 Consider the following Theorem: Theorem: If X, X n are uncorrelated random variables and a,.. a n are real numbers, then the random variable Y defined by Y = has mean and variance given by where μ i and σ i are the mean and variance of X i for i=, n. n i= n a X μ = a μ Y Y i= n i i i σ = a σ i= i i i

31 Series esistor Connection A = + Ser= + + = + From Theorem = Ser ~ 0, B Extending to n-resistors that are nominally identical A n =n + Sern = n Sern k ~ 0, n k n B

32 Summary of esults Structure ominal esistance Standard Deviation ormalized Standard Deviation Ser n n n ote increasing the resistance by a factor of n increased the standard deviation by n

33 ormalized Statistical Characterization From previous theorem: =? For single resistor = = For series connection of n ideally identical resistors n k n EQ k n EQ EQorm= n n n k n k k k n n = = = n n k k EQ EQ n = n ote increasing the resistance by a factor of n dropped the normalized standard deviation by n

34 Summary of esults Structure ominal esistance Standard Deviation ormalized Standard Deviation = Ser n n n n ote increasing the resistance by a factor of n increased the standard deviation by n ote increasing the resistance by a factor of n decreased the normalized standard deviation by n

35 Parallel esistor Connection = + = Par = + + = Par Par A B Par The random variable Par is highly nonlinear in and Some very good approximations of Par can be made that linearize the expression

36 = + = + Parallel esistor Connection Par A ecall that for x small, Thus x x Par B From Theorem Par Par 8 For n in parallel, it follows that A Parn 3 n B n

37 Consider normalized variance Parallel esistor Connection Par = A From Theorem Par + Par orm + Par 4 4 Par orm Par Par orm And for n in parallel Parn Parnorm n = Par n n ote decreasing the resistance by a factor of n dropped the standard deviation by n Par 8 A B B n

38 Summary of esults Structure ominal esistance Standard Deviation ormalized Standard Deviation = Ser n n n n Par n n n 3 n ote increasing or decreasing the resistance by a factor of n decreased the normalized standard deviation by n ote increasing the area by a factor of n decreased the normalized standard deviation by n What is the relationship between resistance, area, and standard deviation?

39 Consider parallel/series combination of 4 nominally identical resistors A 3 4 EQ EQ EQ B ote making no change in the resistance reduced the standard deviation by ote increasing the area by a factor of 4 dropped the standard deviation by

40 Structure Ser n Summary of esults ominal esistance n Standard Deviation n ormalized Standard Deviation n Par n Ser Par n n 3 8 n Ser 4 4 Par Par/Ser 4

41 Observation: In all cases, increasing the area by a factor of n decreases the normalized standard deviation by sqrt (n)

42 Have considered in previous examples the following scenarios Current density is uniform in each structure Aspect ratio plays no role in normalized performance esistance value plays no role in normalized performance Only factor in normalized performance is area For a given resistance, each factor of reduction in σ requires a factor of 4 increase in area

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45 Counter example showing limitations of standard assumptions Assume sheet resistance constant in yellow region of value ρ and constant in purple region of value ρ A W ε W L ρ ρ W X If ε is small and W X large, ρ = EQ B L AB ρ W ρx,ydxdy A ρ +ρ A If ρ and ρ are not equal, then ρ EQ ρ Though errors can be big, in practical processes the assumptions are probably pretty good!

46 Consider a square reference resistor of width µm Assume the standard deviation of this reference resistor, due to local random variations, is σ EF µ B B Consider now a resistor of length L and width W B Define the equivalent resistivity of this resistor: EQ EQ is a random variable with a nominal value of and standard deviation that satisfies the expression EQ W L A EF EF It follows that the value of the resistor is given by the expression Thus L W EQ EQ L W L W B L EF EF L W W L W A=W L 3

47 Consider a resistor of width W and length L B L EF EF L W W L W Consider now the normalized resistance where L W 3 A=W L L W B It follows that L W L EF EF 3 EF 3 W L W WL The term on the right in [ ] is the ratio of two process parameters so define the process parameter A by the expression EF A A is more convenient to use than both σ EF and Thus the normalized resistance is given by the expression A WL A A

48 End of Lecture 8